DETAILED ACTION
This action is responsive to the application filed on 7/23/2024. Claims 1-20 are pending and have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1-20 are objected to because of the following informalities:
In regards to claim 1, line 11 amend “the storage device” to “the memory storage device” as to use language consistent with claim 1, line 9 and to correct a minor antecedent basis issue. (note: the language does not rise to a level of indefiniteness as defined in 35 USC 112(b) and therefore it has been addressed as a claim objection)
In regards to claim 1, line 14 amend “the storage device” to “the memory storage device” as to use language consistent with claim 1, line 9 and to correct a minor antecedent basis issue. (note: the language does not rise to a level of indefiniteness as defined in 35 USC 112(b) and therefore it has been addressed as a claim objection)
In regards to claim 7, line 3 amend the limitation “the corresponding memory cell included in the configurable processor controller” to “the corresponding function memory cell included in the configurable processor controller” as to use language consistent with claim 2, lines 2-3 and to correct a minor antecedent basis issue. (note: the language does not rise to a level of indefiniteness as defined in 35 USC 112(b) and therefore it has been addressed as a claim objection)
In regards to claim 11, line 9 amend “the storage device” to “the memory storage device” as to use language consistent with claim 11, line 8 and to correct a minor antecedent basis issue. (note: the language does not rise to a level of indefiniteness as defined in 35 USC 112(b) and therefore it has been addressed as a claim objection)
In regards to claim 11, line 13 amend “the storage device” to “the memory storage device” as to use language consistent with claim 11, line 8 and to correct a minor antecedent basis issue. (note: the language does not rise to a level of indefiniteness as defined in 35 USC 112(b) and therefore it has been addressed as a claim objection)
In regards to claim 17, line 2 amend the limitation “the corresponding memory cell included in the configurable processor controller” to “the corresponding function memory cell included in the configurable processor controller” as to use language consistent with claim 12, lines 3-4 and to correct a minor antecedent basis issue. (note: the language does not rise to a level of indefiniteness as defined in 35 USC 112(b) and therefore it has been addressed as a claim objection)
Claims 2-10 and 12-20 are dependent upon one or more claims above and therefore are similarly objected to at least based on their dependencies to one or more of the claims above.
Appropriate correction is required.
Claim Interpretation/Examiner Notes
Claim 11 recites the following contingent limitations: “…executing, by the dynamic memory block, a computation operation when the storage of the data elements is adjusted thereby triggering the computation operation and enabling the memory cells to function as a memory storage device and a computation device...” in lines 6-8.
The contingent limitation uses the language “when” which is contingent because it is only required to be performed if (e.g. in response to) a condition being met (e.g. computation operation is only executed when the storage of the data elements is adjusted). However, if the storage elements are not adjusted the following steps are not required to occur based on the broadest reasonable interpretation given to contingent limitations in method claims (See MPEP 2111.04(II) See Ex parte Schulhauser, Appeal 2013-007847 (PTAB April 28, 2016)).
The examiner suggests amending the claim to remove the contingent limitations stating “when” and positively recite each step of the method claim. For example, the claim limitation could be amended to “…executing, by the dynamic memory block, a computation operation [[when]] by adjusting the storage of the data elements
The examiner further asserts that claims 14-17 both include contingent limitations stating “when” that should be removed.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,045,193. Although the claims at issue are not identical, they are not patentably distinct from each other because each claim of USPAT No. 12,045,193 anticipates the claims of the instant application.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 5, 7-8 and 15-18 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
In regards to claim 5, the limitation stating “…the data elements included in the configurable processor controller operate as a binary adder to execute an addition operation; and apply the binary adder to each corresponding memory cell included in the dynamic memory block” fails to comply with the written description requirement because the original disclosure does not properly describe data elements operating as a binary adder and applying a binary adder in sufficient detail that one of ordinary skill in the art can reasonably conclude that the invention had possession of the claimed invention.
Specifically, while paragraphs [0067-0068] disclose a configurable processor controller that stores lookup table bits that are transposed to different functions, the paragraphs do not disclose that the lookup table bits operate as a binary adder nor applying a binary adder to corresponding memory cells. Rather, paragraphs [0067-0068] disclose applying lookup table bits to corresponding memory cells based on a corresponding address, wherein the address indicates the function that is to be executed. While the disclosure in paragraphs [0073-0074] use the above phrase as written it does so without providing sufficient details supporting the idea that the actual lookup table bits themselves indicate a function or operate as a binary adder that can be applied to data elements in memory cells of a memory block.
Claim 15 is similarly rejected on the same basis as claim 5 above as claim 15 includes similar limitations as discussed above with regards to claim 5 above.
Claims 16-18 are similarly rejected on the same basis as claim 15 above as claims 16-18 are dependent upon claim 15 above and therefore include similar deficiencies as claim 15.
9. In regards to claim 7, the limitation stating “…each data element stored in each corresponding function memory cell included in the configurable processor controller operate as a one-bit adder to execute an multiplication operation; apply each one-bit adder…” fails to comply with the written description requirement because the original disclosure does not properly describe data elements operating as a one-bit adder and applying each one-bit adder in sufficient detail that one of ordinary skill in the art can reasonably conclude that the invention had possession of the claimed invention.
Specifically, while paragraphs [0067-0068] disclose a configurable processor controller that stores lookup table bits that are transposed to different functions, the paragraphs do not disclose that the lookup table bits operate as a binary adder nor applying a binary adder to corresponding memory cells. Rather, paragraphs [0067-0068] disclose applying lookup table bits to corresponding memory cells based on a corresponding address, wherein the address indicates the function that is to be executed. While the disclosure in paragraphs [0077-0078] use the above phrase as written it does so without providing sufficient details supporting the idea that the actual lookup table bits themselves indicate a function or operate as one-bit adders that can be applied to data elements in memory cells of a memory block.
Claim 17 is similarly rejected on the same basis as claim 7 above as claim 17 includes similar limitations as discussed above with regards to claim 7 above.
Claims 8 and 18 are similarly rejected on the same basis as claims 7 and 17 above as claims 8 and 18 are dependent upon one of claims 7 and 17 above and therefore include similar deficiencies as claims 7 and 17 above.
10. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
11. Claims 2-10 and 12-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In regards to claim 2, lines 2-3 the limitation “each data element stored in a corresponding function memory cell” lacks clarity. The limitation lacks clarity because it is unclear if the limitation is indicating that each data element is stored in “a corresponding function memory cell”, i.e. a same single memory cell or each data element is stored in a corresponding function memory cell from a plurality of function memory cells? The examiner believes the applicant is referring to the latter and for purposes of examination will interpret the limitation as the latter.
In regards to claim 4, line 3 the limitation “store each data element in the corresponding function memory cell” lacks clarity. The limitation lacks clarity because it is unclear if the limitation is indicating that each data element is stored in “a corresponding function memory cell”, i.e. a same single memory cell indicated in claim 2, lines 2-3 or each data element is stored in a corresponding function memory cell from a plurality of function memory cells? The examiner believes that the applicant is referring to the latter and for purposes of examination will interpret the limitation as the latter. The examiner suggests amending line 3 of claim 4 to state “store each data element in each corresponding function memory cell” or “store each data element in a respective corresponding function memory cell” as to improve clarity.
In regards to claim 5, line 3 the limitation “store each data element in the corresponding function memory cell” lacks clarity. The limitation lacks clarity because it is unclear if the limitation is indicating that each data element is stored in “a corresponding function memory cell”, i.e. a same single memory cell indicated in claim 2, lines 2-3 or each data element is stored in a corresponding function memory cell from a plurality of function memory cells? The examiner believes that the applicant is referring to the latter and for purposes of examination will interpret the limitation as the latter. The examiner suggests amending line 3 of claim 5 to state “store each data element in each corresponding function memory cell” or “store each data element in a respective corresponding function memory cell” as to improve clarity.
In regards to claim 5, the limitation stating “the data elements included in the configurable processor controller operate as a binary adder to execute an addition operation; and apply the binary adder to each corresponding memory cell included in the dynamic memory block” lacks clarity. It is unclear how data elements operate as a binary adder (e.g. a digital circuit) and can be applied to other elements as a binary adder. Are the bits used to identify (i.e. lookup) an adder function at a particular address? The applicant should indicate with support from the specification, preferably using an example with regards to Fig. 3, what is meant and how the bits operate as a binary adder.
In regards to claim 6, line 3 the limitation “apply each data element in the corresponding function memory cell” lacks clarity. The limitation lacks clarity because it is unclear if the limitation is indicating that each data element is stored in “a corresponding function memory cell”, i.e. a same single memory cell indicated in claim 2, lines 2-3 or each data element is stored in a corresponding function memory cell from a plurality of function memory cells? The examiner believes that the applicant is referring to the latter and for purposes of examination will interpret the limitation as the latter. The examiner suggests amending line 3 of claim 6 to state “apply each data element in each corresponding function memory cell” or “apply each data element in a respective corresponding function memory cell” as to improve clarity.
In regards to claim 7, line 3 the limitation “store each data element in the corresponding function memory cell” lacks clarity. The limitation lacks clarity because it is unclear if the limitation is indicating that each data element is stored in “a corresponding function memory cell”, i.e. a same single memory cell indicated in claim 2, lines 2-3 or each data element is stored in a corresponding function memory cell from a plurality of function memory cells? The examiner believes that the applicant is referring to the latter and for purposes of examination will interpret the limitation as the latter. The examiner suggests amending line 3 of claim 7 to state “store each data element in each corresponding function memory cell” or “store each data element in a respective corresponding function memory cell” as to improve clarity.
In regards to claim 7, the limitation stating “each data element stored in each corresponding function memory cell included in the configurable processor controller operate as a one-bit adder to execute a multiplication operation; apply each one-bit adder …” lacks clarity. It is unclear how data elements operate as a one-bit adder (e.g. a digital circuit) and can be applied to other elements as a one-bit adder. Are the bits used to identify (i.e. lookup) an adder function at a particular address? The applicant should indicate with support from the specification, preferably using an example with regards to Fig. 3, what is meant and how the bits operate as a one-bit adder.
In regards to claim 7, lines 10 and 14 each include a recitation of “the multiplication operation” which lack clarity. The limitations lack clarity because it is unclear if the limitations are referring to a “multiplication operation” of claim 6, last line or a “multiplication operation” of claim 7, line 7?
In regards to claim 8, line 2 a recitation of “the multiplication operation” lacks clarity. The limitation lacks clarity because it is unclear if the limitation is referring to a “multiplication operation” of claim 6, last line or a “multiplication operation” of claim 7, line 7?
In regards to claim 12, lines 2-3 the limitation “each data element stored in a corresponding function memory cell” lacks clarity. The limitation lacks clarity because it is unclear if the limitation is indicating that each data element is stored in “a corresponding function memory cell”, i.e. a same single memory cell or each data element is stored in a corresponding function memory cell from a plurality of function memory cells? The examiner believes the applicant is referring to the latter and for purposes of examination will interpret the limitation as the latter.
In regards to claim 14, line 2 the limitation “storing each data element in the corresponding function memory cell” lacks clarity. The limitation lacks clarity because it is unclear if the limitation is indicating that each data element is stored in “a corresponding function memory cell”, i.e. a same single memory cell indicated in claim 12, lines 2-3 or each data element is stored in a corresponding function memory cell from a plurality of function memory cells? The examiner believes that the applicant is referring to the latter and for purposes of examination will interpret the limitation as the latter. The examiner suggests amending line 2 of claim 14 to state “storing each data element in each corresponding function memory cell” or “storing each data element in a respective corresponding function memory cell” as to improve clarity.
In regards to claim 15, line 2 the limitation “storing each data element in the corresponding function memory cell” lacks clarity. The limitation lacks clarity because it is unclear if the limitation is indicating that each data element is stored in “a corresponding function memory cell”, i.e. a same single memory cell indicated in claim 12, lines 2-3 or each data element is stored in a corresponding function memory cell from a plurality of function memory cells? The examiner believes that the applicant is referring to the latter and for purposes of examination will interpret the limitation as the latter. The examiner suggests amending line 2 of claim 15 to state “storing each data element in each corresponding function memory cell” or “storing each data element in a respective corresponding function memory cell” as to improve clarity.
In regards to claim 15, the limitation stating “the data elements included in the configurable processor controller operate as a binary adder to execute an addition operation; and apply the binary adder to each corresponding memory cell included in the dynamic memory block” lacks clarity. It is unclear how data elements operate as a binary adder (e.g. a digital circuit) and can be applied to other elements as a binary adder. Are the bits used to identify (i.e. lookup) an adder function at a particular address? The applicant should indicate with support from the specification, preferably using an example with regards to Fig. 3, what is meant and how the bits operate as a binary adder.
In regards to claim 16, line 2 the limitation “applying each data element in the corresponding function memory cell” lacks clarity. The limitation lacks clarity because it is unclear if the limitation is indicating that each data element is stored in “a corresponding function memory cell”, i.e. a same single memory cell indicated in claim 12, lines 2-3 or each data element is stored in a corresponding function memory cell from a plurality of function memory cells? The examiner believes that the applicant is referring to the latter and for purposes of examination will interpret the limitation as the latter. The examiner suggests amending line 2 of claim 16 to state “applying each data element in each corresponding function memory cell” or “applying each data element in a respective corresponding function memory cell” as to improve clarity.
In regards to claim 17, line 2 the limitation “storing each data element in the corresponding function memory cell” lacks clarity. The limitation lacks clarity because it is unclear if the limitation is indicating that each data element is stored in “a corresponding function memory cell”, i.e. a same single memory cell indicated in claim 12, lines 2-3 or each data element is stored in a corresponding function memory cell from a plurality of function memory cells? The examiner believes that the applicant is referring to the latter and for purposes of examination will interpret the limitation as the latter. The examiner suggests amending line 2 of claim 17 to state “storing each data element in each corresponding function memory cell” or “storing each data element in a respective corresponding function memory cell” as to improve clarity.
In regards to claim 17, the limitation stating “each data element stored in each corresponding function memory cell included in the configurable processor controller operate as a one-bit adder to execute a multiplication operation; apply each one-bit adder …” lacks clarity. It is unclear how data elements operate as a one-bit adder (e.g. a digital circuit) and can be applied to other elements as a one-bit adder. Are the bits used to identify (i.e. lookup) an adder function at a particular address? The applicant should indicate with support from the specification, preferably using an example with regards to Fig. 3, what is meant and how the bits operate as a one-bit adder.
In regards to claim 17, lines 9 and 12-13 each include a recitation of “the multiplication operation” which lack clarity. The limitations lack clarity because it is unclear if the limitations are referring to a “multiplication operation” of claim 16, last line or a “multiplication operation” of claim 17, line 6?
In regards to claim 18, line 2 a recitation of “the multiplication operation” lacks clarity. The limitation lacks clarity because it is unclear if the limitation is referring to a “multiplication operation” of claim 16, last line or a “multiplication operation” of claim 17, line 6?
Claims 3-10 and 13-20 are dependent upon one or more claims above and therefore are similarly rejected on the same basis as one or more claims above.
Claim Rejections - 35 USC § 102
12. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
13. Claim(s) 1 and 11 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Verma, PGPUB No. 2021/0271597 (cited on IDS filed on 7/23/2024).
In regards to claim 1, Verma discloses A system (See Fig. 2 and [0032 and 0052]) that incorporates a dynamic memory block and a configurable processor controller to enable computational processing and memory storage via the dynamic memory block and the configurable processor controller ([0053, 0056, 0063 and 0066]: wherein CIMU (element 300) is a dynamic memory block and CPU (element 210) is a configurable processor controller, and they are used to enable computational processing and memory storage (See Fig. 2)) comprising: a plurality of memory cells included in the dynamic memory block configured to: store a plurality of data elements with each data element stored in a corresponding memory cell ([0041-0042, 0056, 0059-0061]: wherein compute-in memory array (CIMA) of CIMU includes a plurality of memory bit cells configured to store corresponding data elements (i.e. matrix data elements) (See Fig. 3)) and execute a computation operation when the storage of the data elements is adjusted thereby triggering the computation operation and enabling the memory cells to function as a memory storage device and a computation device ([0042, 0056 and 0064-0066]: wherein the CIMA executes a matrix-vector multiplication when the storage of the matrix data elements is adjusted by applying vector elements to input lines of the CIMA, thereby triggering matrix-vector multiplication and enabling the memory cells to function as a memory storage device and a computation device) and a configurable processor controller configured to: transition the memory cells from the storage device to the computation device by adjusting the storage of data elements by the memory cells to execute the computation operation ([0042, 0056 and 0063-0066]: wherein CPU (element 210) is configured to transition the memory cells from the storage device to the computation device because the CPU directly accesses the memory interfaces (elements 220, 320 and 230) used to apply the vector data elements to the CIMA and therefore the CPU initiates the matrix-vector computation. Therefore, the CPU sends the vector data to the CIMA which adjusts the storage of data elements of the memory cells of the CIMA to execute the matrix-vector computation (See Fig. 3 and paragraph [0070], wherein CPU inputs input activation vectors to reshaping buffer (element 320) of CIMA)) and transition the memory cells from the computation device to the storage device by maintaining the storage of data elements by the memory cells in a static state thereby preventing storage of data elements by the memory cells from being adjusted. ([0063-0066]: wherein the CPU can use the CIMA as a normal memory using memory interface (element 340), and in-memory computing is not activated. Therefore, the data stored in the memory cells, using memory interface, would be maintained in a static state and storage of data elements in the memory cells would not be adjusted)
Claim 11 is the method claim corresponding to the system of claim 1 above and is similarly rejected on the same basis as claim 1 above.
Claim Rejections - 35 USC § 103
14. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
15. Claim(s) 2-4, 9, 12-14 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Verma, and further in view of Chawla, PGPUB No. 2021/0181828 (cited on IDS filed on 7/23/2024).
In regards to claim 2, Verma discloses The system of claim 1 (see rejection of claim 1 above) wherein the configurable processor controller (See Fig. 2, element 210) is further configured to store a plurality of data elements with each data element included in the configurable processor controller ([0053, 0059, 0063-0066 and 0070]: wherein 32-bit CPU (element 210) writes 32-bit data words to buffer (element 320) of CIMU, thus the CPU stores 32-bit data words (See Figs. 3-4))
Verma does not explicitly disclose store a plurality of data elements with each data element stored in a corresponding function memory cell included in the configurable processor controller. Verma discloses a CPU that stores 32-bit data words that are written to a compute-in-memory unit. However, Verma does not explicitly disclose the CPU including memory cells to store the plurality of data elements.
Chawla discloses a CPU to store a plurality of data elements with each data element stored in a corresponding function memory cell included in the CPU ([0021-0023]: wherein a CPU (element 120) stores data elements in SRAM memory cells of the CPU (See Fig. 1))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the CPU (configurable processor controller) of Verma to include a SRAM memory array to store data elements as disclosed in Chawla. It would have been obvious to one of ordinary skill in the art because it would have been applying a known technique (using a SRAM memory array with memory cells to store data elements in a CPU) to a known device (CPU of Verma) ready for improvement to yield predictable result (including a SRAM memory array local to a CPU as to store data elements used to implement functions) for the benefit of storing data in SRAM memory cells which can reduce latency in a CPU (MPEP 2143, Example D).
Claim 12 is the method claim corresponding to the system of claim 2 above and is similarly rejected on the same basis as claim 2 above.
In regards to claim 3, the combination of Verma and Chawla discloses The system of claim 2 (see rejection of claim 2 above) wherein the configurable processor controller is further configured to: apply each data element stored in each corresponding function memory cell included in the configurable processor controller to each data element stored in each corresponding memory cell included in the dynamic memory block via a plurality of input lines (Verma [0042, 0059-0066, 0070 and 0096]: wherein CPU (element 210) applies vector data elements to each of the matrix data elements stored in the CIMA via a plurality of input lines (See Figs. 1-3) (note: combination of Chawla discloses storing data elements in memory array cells in CPU therefore combination of references disclose the above limitation)) and adjust each data element stored in each corresponding memory cell included in the dynamic memory block with the corresponding data element in each corresponding function memory cell included in the configurable processor controller. (Verma [0042, 0056 and 0063-0066]: wherein CPU (element 210) is configured to apply the vector data elements to the CIMA in order to adjust each matrix data element stored in the memory cells of the CIMA with the data element of the vector (note: combination of Chawla discloses storing data elements in memory array cells in CPU therefore combination of references disclose the above limitation))
Claim 13 is the method claim corresponding to the system of claim 3 above and is similarly rejected on the same basis as claim 3 above. (the examiner notes that claim 13 has an additional limitation stating “triggering the computation operation by the memory cells included in the dynamic memory block with the adjustment of each data element stored in each corresponding memory cell included in the dynamic memory block with the corresponding data element in each corresponding function memory cell included in the configurable processor controller applied by the configurable processor controller via the plurality of input lines.” However the additional limitation is taught by the combination of Verma and Chawla as the combination discloses “triggering the computation operation by the memory cells included in the dynamic memory block with the adjustment of each data element stored in each corresponding memory cell included in the dynamic memory block with the corresponding data element in each corresponding function memory cell included in the configurable processor controller applied by the configurable processor controller via the plurality of input lines.” (Verma [0042, 0056 and 0063-0066]: wherein CPU (element 210) is configured to apply the vector data elements to the CIMA in order to adjust each matrix data element stored in the memory cells of the CIMA with the data element of the vector to trigger execution of the matrix-vector computation. Wherein the vector data elements are applied by the CPU (210) using input lines (note: combination of Chawla discloses storing data elements in memory array cells in CPU therefore combination of references disclose the above limitation)))
In regards to claim 4, the combination of Verma and Chawla discloses The system of claim 3 (see rejection of claim 3 above) wherein the configurable processor controller is further configured to: store each data element in the corresponding function memory cell included in the configurable processor controller so that when each data element is applied to each data element stored in each corresponding memory cell included in the dynamic memory block executes a Boolean function (Verma [0042, 0063-0066, 0078 and 0104]: wherein CPU (element 210) is configured to apply the vector data elements to the matrix data elements stored in the CIMA to perform a matrix vector computation using a Boolean function(note: combination of Chawla discloses storing data elements in memory array cells in CPU therefore combination of references disclose the above limitation)) and apply the Boolean function to the memory cells included in the dynamic memory block by applying each data element stored in each corresponding function memory cell included in the configurable processor controller to each data element stored in each corresponding memory cell included in the dynamic memory block to execute the Boolean function. (Verma [0042, 0063-0066, 0078-0082]: wherein a Boolean function is applied to the memory cells in the CIMA by applying the vector data elements to each of the matrix data elements stored in the CIMA to execute a Boolean function (AND or XNOR operation) (note: combination of Chawla discloses storing data elements in memory array cells in CPU therefore combination of references discloses the above limitation))
Claim 14 is the method claim corresponding to the system of claim 4 above and is similarly rejected on the same basis as claim 4 above.
In regards to claim 9, the combination of Verma and Chawla discloses The system of claim 3 (see rejection of claim 3 above).
The combination of Verma and Chawla thus far does not explicitly disclose wherein the configurable processor controller is a Field Programmable Gate Array (FPGA). Verma discloses that the configurable processor controller is a CPU (element 210) of a system implemented as an integrated circuit and that various features can be implemented as FPGA’s. However, Verma thus far does not explicitly disclose that the CPU (element 210) is a FPGA.
Furthermore, both Verma and Chawla disclose CPU hardware being a FPGA. (Verma [0032] | Chawla [0062])
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the CPU (configurable processor controller) of Verma to be a FPGA. It would have been obvious to one of ordinary skill in the art because it would have been applying a known technique (implementing a CPU controller as a FPGA) to a known device (CPU controller of Verma) ready for improvement to yield predictable result (implementing a CPU controller as a FPGA) for the benefit of providing flexible reconfigurable/reprogrammable computing (MPEP 2143, Example D).
Claim 19 is the method claim corresponding to the system of claim 9 above and is similarly rejected on the same basis as claim 9 above.
16. Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Verma, Chawla and further in view of NPL reference, “A Compute SRAM with Bit-Serial Integer/Floating-Point Operations for Programmable In-Memory Vector Acceleration”, hereby referred to as Wang.
In regards to claim 6, the combination of Verma and Chawla discloses “The system of claim 3” (see rejection of claim 3 above) wherein the configurable processor controller is further configured to: apply each data element in the corresponding function memory cell included in the configurable processor controller so that when each data element is applied to each data element stored in each corresponding memory cell included in the dynamic memory block each data element stored in each corresponding memory cell included in the dynamic memory block thereby executing a multiplication operation. (Verma [0042, 0056, 0063-0066 and 0078]: wherein CPU (element 210) is configured to apply the vector data elements to the matrix data elements stored in the CIMA to execute a matrix vector multiplication operation (note: combination of Chawla discloses storing data elements in memory array cells in CPU therefore combination of references discloses the above limitation))
The overall combination of Verma and Chawla does not disclose shifted thereby executing a multiplication operation. Verma discloses the memory cells implementing a multiplication operation but does not explicitly disclose the multiplication operation comprising any shifting.
Wang discloses shifting data in memory cells to execute a multiplication operation (See column 2 of page 224 and disclosure of fig. 14.2.3: wherein a CRAM (compute SRAM) performs a multiplication operation by performing an implicit shift).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the multiplication operation of Verma to perform an implicit shift as the multiplication as disclosed in Wang. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (using a compute in-memory array to perform a multiplication using an implicit shift as taught in Wang) for another (using a compute in-memory to perform a generic multiplication as taught in Verma) to yield predictable results (using a compute in-memory array to perform a multiplication using an implicit shift) (MPEP 2143, Example B).
17. Claim(s) 10 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Verma, Chawla and further in view of Mohl, PGPUB No. 2009/0119484 (cited on IDS filed on 7/23/2024).
In regards to claim 10, the combination of Verma and Chawla discloses The system of claim 9 (see rejection of claim 9 above) wherein the configurable processor controller includes each data element applied to each corresponding data element stored in the corresponding memory cell included in the dynamic memory block to trigger the computation operation of the dynamic memory block. (Verma [0042, 0056, 0063-0066, 0078 and 0104]: wherein CPU (element 210) is configured to apply the vector data elements to the matrix data elements stored in the CIMA to perform a matrix vector computation (note: combination of Chawla discloses storing data elements in memory array cells in CPU therefore combination of references discloses the above limitation))
The combination of Verma and Chawla does not disclose a lookup table included in the FPGA and each data element stored in the lookup table. The overall combination of Verma and Chawla with respect to claim 9 disclose using a FPGA that stores values in a SRAM memory, included in the FPGA, which are applied to data elements in corresponding memory cells of a dynamic memory block to trigger a computation operation. However, the combination thus far does not disclose the FPGA storing the values in a lookup table.
Mohl discloses a lookup table included in the FPGA and each data element stored in the lookup table ([0016-0017]: wherein a SRAM look-up table in an FPGA stores data values)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the SRAM memory of the FPGA of Verma and Chawla to store data values in a SRAM lookup table as disclosed in Mohl. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (using a SRAM lookup table to store data values as taught in Mohl) for another (using a generic SRAM memory to store data values as taught in combination of Verma and Chawla) to yield predictable results (using a SRAM lookup table to store data values) (MPEP 2143, Example B).
Claim 20 is the method claim corresponding to the system of claim 10 above and is similarly rejected on the same basis as claim 10 above.
Prior Art Considerations
18. Claims 5, 7-8 and 15-18 are currently only rejected under 35 USC 112(a-b), but otherwise contain allowable subject matter. However, the examiner notes that efforts to overcome the 35 USC 112(a-b) rejections will likely change the scope of the claims such that new grounds of prior art rejections may be made.
Conclusion
19. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
NPL reference “A Programmable Heterogeneous Microprocessor Based on Bit-Scalable In-Memory Computing” for teaching in-memory computing device performing matrix-vector multiplications
20. Any inquiry concerning this communication or earlier communications from the examiner should be directed to COURTNEY P SPANN whose telephone number is (571)431-0692. The examiner can normally be reached M-F, 9am-6pm, EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/COURTNEY P SPANN/Primary Examiner, Art Unit 2183