DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in People’s Republic of China on July 12, 2024. It is noted, however, that applicant has not filed a certified copy of the CN202410939662.9 application as required by 37 CFR 1.55.
Claim Objections
Claims 5 and 13 are objected to because of the following informalities:
Regarding claim 5: The claim is awkward in English. It is suggested to amend the claim as follows:
The memory device of claim 4, wherein the peripheral circuit is further configured to, in response to the block of memory cells failing to be verified after erasing , erase the block of memory cells again.
Regarding claim 13: The claim is awkward in English. It is suggested to amend the claim as follows:
The method of claim 12, further comprising, in response to the block of memory cells failing to be verified after erasing , erasing the block of memory cells again.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4, 5, 9, 12, and 13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 2001/0043492 A1).
Regarding claim 1: Lee (FIG. 7; [0048-0052]) teaches a memory device, comprising:
a block of memory cells (“a selected sector are erased simultaneously’; [0048]); and
a peripheral circuit (a row decoder; [0011]) coupled to the block of memory cells and configured to, in an erase operation:
pre-erase the block of memory cells (steps S210 with or without S220 in FIG. 7);
program the block of memory cells after pre-erasing the block of memory cells (step S230 in FIG. 7); and
erase the block of memory cells after programming the block of memory cells (step S240 and S250 in FIG. 7).
Regarding claim 4: Lee teaches the memory device of claim 1, wherein the peripheral circuit is further configured to verify the block of memory cells after erasing the block of memory cells (step S250 in FIG. 7).
Regarding claim 5: Lee teaches the memory device of claim 4, wherein the peripheral circuit is further configured to, in response to the block of memory cells after erasing failing to be verified, erase the block of memory cells again (see “No” path from S250 to S240).
Regarding claim 9: Lee (FIG. 7; [0048-0052]) teaches a method for operating a memory device comprising a block of memory cells (“a selected sector are erased simultaneously’; [0048]), the method comprising, in an erase operation:
pre-erasing the block of memory cells (steps S210 and S220 in FIG. 7);
programming the block of memory cells after pre-erasing the block of memory cells (step S230 in FIG. 7); and
erasing the block of memory cells after programming the block of memory cells (step S240 and S250 in FIG. 7).
Regarding claim 12: Lee teaches the method further comprising verifying the block of memory cells after erasing the block of memory cells (step S250 in FIG. 7).
Regarding claim 13: Lee teaches the method further comprising, in response to the block of memory cells after erasing failing to be verified, erase the block of memory cells again (see “No” path from S250 to S240).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2, 3, 8, 10, 11, and 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2001/0043492 A1) in view of Xu et al. (US 2024/0361945 A1).
Regarding claim 2: Lee does not specifically teach the memory device of claim 1, wherein the peripheral circuit is configured not to verify the block of memory cells after pre-erasing and before erasing the block of memory cells.
Xu (FIG. 2; [0039-0045]) teaches applying an erase pulse 230 immediately before applying a pre-program pulse 240 with no verify operation is needed there between (see [0040]; “a verify operation is prevented from being performed”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Xu into the device and/or method of Lee in a manner such that the peripheral circuit would be configured not to verify the block of memory cells after pre-erasing and before erasing the block of memory cells. Hence, the block of memory cells would be programmed immediately after the pre-erase. The motivation to do so would have been to prevent a verify operation as disclosed by Xu. Preventing such a verify operation would obviously save time.
Regarding claim 3: Lee teaches erasing the block of memory cells immediately after programming the block of memory cells (S240).
Lee does not specifically teach the peripheral circuit is configured to program the block of memory cells immediately after pre-erasing the block of memory cells.
Xu (FIG. 2; [0039-0045]) teaches applying an erase pulse 230 immediately before applying a pre-program pulse 240 with no verify operation is needed there between (see [0040]; “a verify operation is prevented from being performed”). Xu ([0014, 0029, 0030, 0037]) also teaches such erasing can be applied to different types of non-volatile memory devices such as NAND or NOR type that have memory blocks and are managed externally, for example, by an external controller, wherein a block is the smallest area that can be erased.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Xu into the device and/or method of Lee in a manner such that the peripheral circuit would be configured not to verify the block of memory cells after pre-erasing and before erasing the block of memory cells. Hence, the block of memory cells would be programmed immediately after the pre-erase. The motivation to do so would have been to prevent a verify operation as disclosed by Xu. Preventing such a verify operation would obviously save time.
Regarding claim 8: Lee does not specifically teach the memory device is a NAND Flash memory device
Xu (FIG. 2; [0039-0045]) teaches applying an erase pulse 230 immediately before applying a pre-program pulse 240 with no verify operation is needed there between (see [0040]; “a verify operation is prevented from being performed”). Xu ([0014, 0029, 0030, 0037]) also teaches such erasing can be applied to different types of non-volatile memory devices such as NAND or NOR type that have memory blocks and are managed externally, for example, by an external controller, wherein a block is the smallest area that can be erased.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Xu into the device and/or method of Lee in a manner such that the memory block or sector would be in a NAND type memory managed by a memory controller 9[0014] of Xu). The motivation to do so would have been to prevent a verify operation in a NAND type memory as disclosed by Xu. Preventing such a verify operation would obviously save time.
Regarding claim 10: Lee does not specifically teach the method comprising not verifying the block of memory cells after pre-erasing and before erasing the block of memory cells.
Xu (FIG. 2; [0039-0045]) teaches applying an erase pulse 230 immediately before applying a pre-program pulse 240 with no verify operation is needed there between (see [0040]; “a verify operation is prevented from being performed”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Xu into the device and/or method of Lee in a manner such that the peripheral circuit would be configured not to verify the block of memory cells after pre-erasing and before erasing the block of memory cells. Hence, the block of memory cells would be programmed immediately after the pre-erase. The motivation to do so would have been to prevent a verify operation as disclosed by Xu. Preventing such a verify operation would obviously save time.
Regarding claim 11: Lee teaches erasing the block of memory cells immediately after programming the block of memory cells (S240).
Lee does not specifically teach the method further comprising programming the block of memory cells immediately after pre-erasing the block of memory cells.
Xu (FIG. 2; [0039-0045]) teaches applying an erase pulse 230 immediately before applying a pre-program pulse 240 with no verify operation is needed there between (see [0040]; “a verify operation is prevented from being performed”). Xu ([0014, 0029, 0030, 0037]) also teaches such erasing can be applied to different types of non-volatile memory devices such as NAND or NOR type that have memory blocks and are managed externally, for example, by an external controller, wherein a block is the smallest area that can be erased.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Xu into the device and/or method of Lee in a manner such that the peripheral circuit would be configured not to verify the block of memory cells after pre-erasing and before erasing the block of memory cells. Hence, the block of memory cells would be programmed immediately after the pre-erase. The motivation to do so would have been to prevent a verify operation as disclosed by Xu. Preventing such a verify operation would obviously save time.
Regarding claims 16-19: Lee (FIG. 7; [0048-0052]) teaches a system ([0003, 0044]), comprising:
a memory device (a flash memory device) configured to store data, the memory device comprising:
a block of memory cells (“a selected sector are erased simultaneously’; [0048]); and
a peripheral circuit (a row decoder; [0011]) coupled to the block of memory cells and configured to, in an erase operation:
pre-erase the block of memory cells (steps S210 and S220 in FIG. 7);
program the block of memory cells after pre-erasing the block of memory cells (step S230 in FIG. 7);
erase the block of memory cells after programming the block of memory cells (step S240 and S250 in FIG. 7).
Lee does not specifically teach:
a memory controller coupled to the memory device and configured to control the memory device, (claim 17) wherein the memory controller is configured to send an erase command to the peripheral circuit of the memory device; and the peripheral circuit is configured to pre-erase, program, and erase the block of memory cells in response to receiving the erase command, (claim 18) wherein the peripheral circuit is configured not to verify the block of memory cells after pre-erasing and before erasing the block of memory cells, and (claim 19) the peripheral circuit is configured not to verify the block of memory cells after pre-erasing and before erasing the block of memory cells
Xu (FIG. 1, FIG. 2, FIG. 4; [0039-0047]) teaches a memory controller (115 in FIG. 1) coupled to a memory device and configured to control the memory device to apply, in response to a request to erase, an erase pulse 230 immediately before applying a pre-program pulse 240 with no verify operation being needed there between (see [0040]; “a verify operation is prevented from being performed”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Xu into the device and/or method of Lee in a manner such that the peripheral circuit, in response to an erase command from a memory controller, would perform an erase operation like that disclosed by Xu such that
a memory controller coupled to the memory device and configured to control the memory device;
the memory controller would be configured to send an erase command to the peripheral circuit of the memory device; and the peripheral circuit would be configured to pre-erase, program, and erase the block of memory cells in response to receiving the erase command; and
the peripheral circuit would be configured not to verify the block of memory cells after pre-erasing and before erasing the block of memory cells/
The motivation to do so would have been to have a memory controller supply an erase command and to prevent a verify operation as disclosed by Xu. Preventing such a verify operation would obviously save time.
Regarding claim 20: Lee teaches the memory device of claim 1, wherein the peripheral circuit is further configured to verify the block of memory cells after erasing the block of memory cells (step S250 in FIG. 7).
Claim(s) 6-7 and 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2001/0043492 A1) in view of Maejima (US 2018/00827553 A1).
Regarding claims 6-7: Lee does not specifically teach the memory device of claim 1, wherein
the memory device further comprises word lines respectively coupled to rows of the block of memory cells;
to pre-erase the block of memory cells, the peripheral circuit is configured to apply a supply voltage that is not greater than 1 volt to each of the word lines;
to erase the block of memory cells, the peripheral circuit is configured to apply the supply voltage to each of the word lines; and
(claim 7) to program the block of memory cells, the peripheral circuit is configured to apply a program voltage to each of the word lines.
Maejima (FIG. 3; FIG. 15) teaches a NAND memory device comprising word lines (WL) respectively coupled to rows of a block of memory cells (BK or SU); to erase the block of memory cells, the peripheral circuit is configured to apply a supply voltage (ground voltage VSS; FIG. 15; [0335-0367]) that is not greater than 1 volt to each of the word lines. Maejima (FIG. 14; [0297-0334]) also teaches a program operation (write operation), wherein a peripheral circuit is configured to apply a program voltage VPGM to each of the word lines when selected for programming.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Maejima into the device and/or method of Lee in a manner such that memory device would be a NAND type memory and would further comprise word lines respectively coupled to rows of the block of memory cells; to pre-erase the block of memory cells, the peripheral circuit would be configured to apply a supply voltage, ground supply voltage VSS, that is not greater than 1 volt to each of the word lines; and to erase the block of memory cells, the peripheral circuit would be configured to apply the supply voltage to each of the word lines, wherein to program the block of memory cells, the peripheral circuit would be configured to apply a program voltage like that of Maejima to each of the word lines. The motivation to do would have been to apply a bias voltage to the word lines of a block that were already known to be suitable for performing an erase operation as exemplified by Maejima.
Regarding claims 14-15: Lee does not specifically teach the method, wherein
the memory device further comprises word lines respectively coupled to rows of the block of memory cells;
pre-erasing the block of memory cells comprises applying a supply voltage that is not greater than 1 volt to each of the word lines;
erasing the block of memory cells comprises applying the supply voltage to each of the word lines; and
(claim 15) programming the block of memory cells comprises applying a program voltage to each of the word lines.
Maejima (FIG. 3; FIG. 15) teaches a NAND memory device comprising word lines (WL) respectively coupled to rows of a block of memory cells (BK or SU); to erase the block of memory cells, the peripheral circuit is configured to apply a supply voltage (ground voltage VSS; FIG. 15; [0335-0367]) that is not greater than 1 volt to each of the word lines. Maejima (FIG. 14; [0297-0334]) also teaches a program operation (write operation), wherein a peripheral circuit is configured to apply a program voltage VPGM to each of the word lines when selected for programming.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Maejima into the device and/or method of Lee in a manner such that memory device would be a NAND type memory and would further comprise word lines respectively coupled to rows of the block of memory cells; to pre-erase the block of memory cells, the peripheral circuit would be configured to apply a supply voltage, ground supply voltage VSS, that is not greater than 1 volt to each of the word lines; and to erase the block of memory cells, the peripheral circuit would be configured to apply the supply voltage to each of the word lines, wherein to program the block of memory cells, the peripheral circuit would be configured to apply a program voltage like that of Maejima to each of the word lines. The motivation to do would have been to apply a bias voltage to the word lines of a block that were already known to be suitable for performing an erase operation as exemplified by Maejima.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY W RADKE whose telephone number is (571)270-1622. The examiner can normally be reached M-F 9-6 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JAY W. RADKE
Primary Examiner
Art Unit 2827
/JAY W. RADKE/Primary Examiner, Art Unit 2827