DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: the Application filed July 23, 2024.
Claims 1-20 are pending. Claims 1, 12 and 18 are independent.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 6 and 9-12 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lu et al. (U.S. 2024/0062825; hereinafter “Lu”).
Regarding independent claim 1, Lu discloses an apparatus, comprising: a memory array comprising a plurality of physical blocks of memory cells (Fig. 7), wherein each physical block of the plurality comprises more than two erase blocks (Fig. 7: each BLK comprises a plurality of sub-blocks “Sub”), with each of the more than two erase blocks of each respective physical block comprising memory cells coupled to a same string of memory cells corresponding to the respective physical block (see Fig. 1); and
a controller (circuitry not shown in figures that perform the mapping, write operation and erase operation, see page 2, par. 0021) coupled to the memory array and configured to operate the memory array in accordance with a logical block implementation (Fig. 7: mapping of blk0 and blk1) in which each logical block comprises:
a first erase block adjacent to a first end of a particular string corresponding to a first physical block (Fig. 7: Sub0 of blk0 mapped from BLK of P1); and
a second erase block (Fig. 7: Sub2 of blk0 mapped from BLK of P3), wherein the second erase block is either:
located in the first physical block and not adjacent to a second end of the particular string corresponding to the first physical block; or
located in a second physical block and adjacent to a first end of a particular string corresponding to the second physical block (Fig. 7: Sub2 of blk0 mapped from BLK of P3).
Regarding claim 6, Lu discloses wherein each physical block comprises an even quantity of erase blocks, and wherein the logical block implementation includes grouping the erase blocks from each physical block into two respective logical blocks (Fig. 7: blk0 and blk1).
Regarding claim 9, Lu discloses wherein the first erase block of a first logical block is adjacent to the first end of the particular string corresponding to the first physical block (Fig. 7: Sub0 of blk0 mapped from BLK of P1), and
the second erase block of the first logical block is located in a second physical block and adjacent to a second end of a particular string corresponding to the second physical block (Fig. 7: Sub2 of blk0 mapped from BLK of P3).
Regarding claim 10, Lu discloses wherein the first end of the particular string corresponding to the first physical block is a source end of the particular string, and the second end of the particular string corresponding to the first physical block is a drain end of the string, and wherein the first physical block comprises:
the first erase block adjacent to the source end of the particular string;
the second erase block adjacent to the drain end of the string; and
at least one intermediate erase block located between the first erase block and the second erase block (Fig. 1 for example shows a plurality of wordlines WLs arranged in a string, wherein the string comprises a source end and a drain end, and a first group of wordlines can be adjacent to the source end, for example: adjacent to GSL, a second group of wordlines can be adjacent to the drain end, for example adjacent to SSL, and a third group of wordlines between the first and second group).
Regarding claim 11, Lu discloses wherein the memory array comprises replacement gate NAND memory cells (see page 1, par. 0002-0003).
Regarding independent claim 12, Lu discloses a method, comprising:
forming, via a controller (circuitry not shown in figures that perform the mapping, write operation and erase operation, see page 2, par. 0021) coupled to a memory array comprising a plurality of physical blocks of memory cells (Fig. 7), wherein each physical block of the plurality comprises more than two erase blocks (Fig. 7: each BLK comprises a plurality of sub-blocks “Sub”), with each of the more than two erase blocks of each respective physical block comprising memory cells coupled to a same string of memory cells corresponding to the respective physical block (see Fig. 1), logical block groupings for the erase blocks in accordance with a particular logical block implementation (Fig. 7: mapping of blk0 and blk1);
wherein forming the logical block groupings comprises grouping the erase blocks such that each logical block comprises:
a first erase block adjacent to a first end of a particular string corresponding to a first physical block (Fig. 7: Sub0 of blk0 mapped from BLK of P1); and
a second erase block (Fig. 7: Sub2 of blk0 mapped from BLK of P3), wherein the second erase block is either:
located in the first physical block and not adjacent to a second end of the particular string corresponding to the first physical block; or
located in a second physical block and adjacent to a first end of a particular string corresponding to the second physical block (Fig. 7: Sub2 of blk0 mapped from BLK of P3); and
performing an operation on the erase blocks based on the determined logical block groupings (see page 4, par. 0031-0033).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al. (U.S. 2024/0062825; hereinafter “Lu”) in view of You (U.S. 2019/0286556).
Regarding claim 2, Lu discloses the limitations with respect to claim 1.
However, Lu is silent with respect to track an amount of valid data on a per erase block bases; and dynamically group logical blocks based, at least partially, on the amount of valid data per erase block.
Similar to Lu, You teaches an apparatus comprising a memory array and a controller coupled to the memory array to operate the memory array in accordance with a logical block implementation.
Furthermore, You teaches track an amount of valid data on a per erase block bases (“amount of valid data stored”, see page 4, par. 0070); and
dynamically group logical blocks based, at least partially, on the amount of valid data per erase block (performing partial block erase operation for a selected sub-blocks, see page 4, par. 0070, Fig. 9, and see also page 8, par. 0160-0161).
Since You and Lu are from the same field of endeavor, the teachings described by You would have been recognized in the pertinent art of Lu.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of You with the teachings of Lu for the purpose of maintain the data stored in pages in the unselected sub-blocks, see You’s page 9, par. 0164.
Regarding claim 14, Lu discloses the limitations with respect to claim 12.
However, Lu is silent with respect to tracking, via the controller, an amount of valid data on an erase block bases; and dynamically adjusting, via the controller, the logical block groupings based on determined changes in the amount of valid data per erase block.
You teaches tracking, via the controller, an amount of valid data on an erase block bases (“amount of valid data stored”, see page 4, par. 0070); and
dynamically adjusting, via the controller, the logical block groupings based on determined changes in the amount of valid data per erase block (performing partial block erase operation for a selected sub-blocks, see page 4, par. 0070, Fig. 9, and see also page 8, par. 0160-0161).
Since You and Lu are from the same field of endeavor, the teachings described by You would have been recognized in the pertinent art of Lu.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of You with the teachings of Lu for the purpose of maintain the data stored in pages in the unselected sub-blocks, see You’s page 9, par. 0164.
Allowable Subject Matter
Claims 3-5, 7-8, 13 and 15-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 3, there is no teaching or suggestion in the prior art of record to provide the recited each physical block comprises three erase blocks, and wherein the logical block implementation includes grouping the three erase blocks from each of two physical blocks into three logical blocks with each of the three logical blocks corresponding to two different erase blocks.
With respect to claim 7, there is no teaching or suggestion in the prior art of record to provide the recited first erase block of a first logical block is adjacent to the first end of the particular string corresponding to the first physical block, the second erase block of the first logical block is located in the first physical block and not adjacent to the second end of the particular string corresponding to the first physical block, and the first erase block of a second logical block is adjacent to a second end of the particular string corresponding to the first physical block.
With respect to claim 13, there is no teaching or suggestion in the prior art of record to provide the recited step of determining the logical block groupings such that any erase blocks that are not adjacent to either end of the particular string corresponding to the first physical block or either end of the particular string corresponding to the second physical block are adjacent to an erase block that is adjacent to either end of the particular string corresponding to the first physical block or either end of the particular string corresponding to the second physical block.
With respect to claim 15, there is no teaching or suggestion in the prior art of record to provide the recited plurality of physical blocks comprise an even quantity of erase blocks, and wherein the particular logical block implementation comprises grouping the erase blocks such that each logical block comprises half of the erase blocks within a respective one of the at least some of the plurality of physical blocks.
With respect to claim 16, there is no teaching or suggestion in the prior art of record to provide the recited step of grouping the erase blocks to facilitate passage of a seed voltage to intermediate erase blocks in association with programming the intermediate erase blocks.
With respect to claim 17, there is no teaching or suggestion in the prior art of record to provide the recited step of forming the logical block groupings comprises forming three logical blocks out of every two physical blocks of the plurality of physical blocks.
Claims 18-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
With respect to independent claim 18, there is no teaching or suggestion in the prior art of record to provide the recited plurality of logical block groupings comprises a first grouping comprising a first erase block adjacent to a first end of the first string and a second erase block adjacent to the first erase block, a second grouping comprising third erase block adjacent to a first end of the second string and a fourth erase block adjacent to the third erase block, and a third grouping comprising a fifth erase block adjacent to a second end of the first string and a sixth erase block adjacent to a second end of the second string, in combination with the other limitations.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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/Alfredo Bermudez Lozada/Primary Examiner, Art Unit 2825