DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4, 15, 16 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin (US 2016/0155484).
Regarding claim 1, Lin discloses a memory device, comprising: a memory cell array (see Figure 2); a plurality of word lines (GWL’s, LWL’s, see Figure 2-5) coupled with the memory cell array; and a peripheral circuit (GWL, LWL decoders+drivers) coupled with the memory cell array through the plurality of word lines and comprising a drive circuit, wherein the drive circuit comprises a main driver (driver of GWL) and a plurality of word line drivers (Driver of LWL), each of the word line drivers is correspondingly coupled with each of the word lines, and the main driver is connected to n word line drivers, wherein n is an integer greater than 8 (see paragraph 0055, GWL being driven by its inherent driver is connected to 16 LWL).
Regarding claim 4, Lin discloses the memory device of claim 1, wherein the main driver is connected to 16 word line drivers (see paragraph 0055).
Regarding claim 15, Lin discloses a memory system, comprising: a memory device, comprising: a memory cell array; a plurality of word lines coupled with the memory cell array; and a peripheral circuit coupled with the memory cell array through the plurality of word lines and comprising a drive circuit, wherein the drive circuit comprises a main driver and a plurality of word line drivers, each of the word line drivers is correspondingly coupled with each of the word lines, and the main driver is connected to n word line drivers, wherein n is an integer greater than 8 (see rejection of claim 1 above); and a memory controller coupled to the memory device and configured to control the memory device (see Figure 6, 619 for example).
Regarding claims 16 and 19 recites substantially the same features as above in the method form of “forming” said device. Since the device is taught as outlined above, the generic method of simply “forming” is inherently disclosed as well.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 13 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin.
Regarding claim 13, Lin discloses the memory device of claim 1, but fails to teach wherein the memory cell array comprises a plurality of memory cells, and each memory cell comprises one vertical transistor and one capacitor.
However, this is a common and well-known memory configuration (vertical transistor DRAM) and implementing the teachings of Lin in such known devices would have been obvious at the time of filing in order to achieve the benefits described by Lin in the DRAM.
Regarding claim 14, Lin discloses the memory device of claim 1, but fails the memory cell array and the peripheral circuit are formed on different substrates, and the peripheral circuit and the memory cell array are stacked in a vertical direction.
However, this is a common and well-known memory configuration of stacked and layers circuitry and implementing the teachings of Lin in such known devices would have been obvious at the time of filing in order to achieve the benefits described by Lin in the DRAM. Further, it would have been obvious to stack the peripheral and memory circuits vertically in order to minimize lateral chip space.
Claim(s) 2, 3, 17 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Em (US 2025/0006247).
Regarding claim 2 and 17, Lin discloses the memory device of claim 1, but fails to teach wherein the main driver comprises a pre-charge circuit and an output circuit, a transistor size of a transistor in the output circuit is greater than a transistor size of a transistor in the pre-charge circuit.
However, it was known at the time of filing to provide larger main wordline drive transistors and reducing transistor count to conserve circuit area (see Em, paragraph 0037). Furthermore, Em teaches such a word line driver comprises a main driver output circuit (420 for example) with the increased transistor size and a precharge circuit 410).
Regarding claims 3 and 18, Lin as modified above discloses the memory device of claim 2, but fails to teach wherein a ratio of a transistor size of a transistor in the output circuit to a transistor size of a transistor in the pre-charge circuit ranges from 1.5 to 2.
However the size of transistors is well established in the art as result effective variable and one of ordinary skill is fully aware of how the modifications to the size of said transistors will effect performance (e.g. speed, leakage, current handling, etc.). Therefore, finding the optimal size (and therefore ratio) of sizes for the output circuit transistors would require only a routine optimization and be obvious to those having ordinary skill at the time of filing.
Allowable Subject Matter
Claims 5-12 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claims 5 and 20, the prior art fails to teach or reasonably disclose in combination all the features of the claim in combination with preceding claim limitations including a row decoder coupled to the drive circuit and configured to decode 9th-bit to 5th-bit row addresses in a row address signal of m bits to generate a main drive signal, and decode the row addresses of the lowest 4 bits in the row address signal of m bits to generate a word line drive signal, wherein m is an integer greater than 9; and the drive circuit is configured to drive a target word line based on the main drive signal and the word line drive signal.
Claims 6-12 depend from above.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
The remaining cited and attached references teach various embodiments of various embodiments of row signal line "fanning" configurations.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS KING whose telephone number is (571)272-2311. The examiner can normally be reached M-F: 9:00AM-5:30PM.
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/DOUGLAS KING/Primary Examiner, Art Unit 2824
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