DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to 04/03/2026 Amendment.
Claims 1, 3-20 are pending and examined. Claim 2 has been cancelled.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 10,204,692 to Kamata et al. (hereafter Kamata).
Regarding independent claim 1, Kamata teaches an apparatus, comprising:
an array of memory cells (FIG. 1: memory cell array 11); and
a controller coupled to the array of memory cells (FIG. 1: logic controller 16), wherein the controller is configured to:
apply a pass voltage to a wordline in the array of memory cells (FIG. 12: applying Vread to selected WL from t0-t1);
apply a read voltage to the wordline (FIG. 12: applying AR to selected WL from t1-t3); and
apply a read voltage overdrive greater than the read voltage and less than or equal to the pass voltage to the wordline during read recovery (FIG. 12: applying CR+CGkick to selected WL right at t3, wherein the magnitude of CGkick can be set to any numerical value, see 13:37-48); and
increase a precharge time during the read recovery (i.e. the given time, see 11:55-12:3. Also see annotated FIG. 12 below).
Annotated FIG. 12
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Regarding independent claim 16, Kamata teaches a method, comprising:
applying a pass voltage to a wordline in an array of memory cells (FIG. 12: applying Vread to selected WL from t0-t1);
applying a first read voltage to the wordline (FIG. 12: applying AR to selected WL from t1-t3);
applying a read voltage overdrive equal to the pass voltage to the wordline during a read recovery (FIG. 12: applying CR+CGkick to selected WL right at t3, wherein the magnitude of CGkick can be set to any numerical value, see 13:37-48. This implies CR+CGkick can be set equal to Vread);
increasing a precharge time during the read recovery (i.e. the given time, see 11:55-12:3. Also see annotated FIG. 12 below); and
applying a second read voltage to the wordline (FIG. 12: applying CR to selected WL after CGkick).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-11 are rejected under 35 U.S.C. 103 as being unpatentable over US 10,895,999 to Hsiao (hereafter Hsiao) in view of Kamata.
Kamata teaches, as applied in prior rejection of claim 1, all claimed subject matter except further limitations set forth in the following claim(s).
Regarding dependent claim 3, Hsiao teaches applying a read voltage overdrive (FIG. 7B: V(2)6 for read assisting operation) to the wordline during a read recovery (i.e. soft bit read to obtain soft information for error correction, see 12:45-13:21) in response to the number of errors exceeding a threshold number of errors (e.g. when the number of errors is greater than number of correctable errors, see 3:46-62 and 13:65-14:14), wherein the read voltage overdrive is greater than the read voltage (FIG. 7B: V(2)6>V(1)6) and greater than a highest read voltage (FIG. 7B: highest read voltage is also V(1)6).
Since Kamata and Hsiao are both from the same field of endeavor, the purpose disclosed by Hsiao would have been recognized in the pertinent art of Kamata.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to set CR+CGkick of Kamata substantially equal to V(2)6 of Hsiao for soft bit read and error correction purpose.
Regarding dependent claim 3, Hsiao teaches wherein the read recovery includes at least one of a read retry, a soft bit read, or a corrective read (FIG. 6C: soft bit is read using V(2)2 ).
Regarding dependent claim 4, Hsiao teaches wherein the wordline includes triple level cells (TLCs) (see 11:30-47).
Regarding dependent claim 5, Hsiao does not explicitly teach wherein the controller is configured to increase a read window budget by greater than 50 mV in response to applying the read voltage overdrive to TLCs. However, it would have been obvious to one with ordinary skill in the art to realize that value for increase a read window budget is often a design choice depending on the type of memory device.
Regarding dependent claim 6, Hsiao teaches wherein the wordline includes quad-level cells (QLCs) (see 11:30-47).
Regarding dependent claim 7, Hsiao does not explicitly teach wherein the controller is configured to increase a read window budget by greater than 190 mV in response to applying the read voltage overdrive to QLCs. However, it would have been obvious to one with ordinary skill in the art to realize that value for increase a read window budget is often a design choice depending on the type of memory device.
Regarding independent claim 8, Hsiao teaches an apparatus, comprising:
an array of non-volatile memory cells (FIG. 1: rewritable non-volatile memory module 220); and
a controller coupled to the array of non-volatile memory cells (FIG. 1: storage controller 210), wherein the controller is configured to:
apply a read voltage to a wordline in the array of non-volatile memory cells (FIG. 7B: e.g. reading hard bit with V(1)6);
identify a number of errors in response to applying the read voltage to the wordline (FIG. 1: via error checking and correcting circuit 214, see 3:46-62 and 13:65-14:14);
apply a read voltage overdrive (FIG. 7B: V(2)6 for read assisting operation) to the wordline greater than the read voltage (FIG. 7B: V(2)6>V(1)6) and greater than a highest read voltage (FIG. 7B: highest read voltage is also V(1)6) applied to the wordline during a read recovery (i.e. soft bit read to obtain soft information for error correction, see 12:45-13:21) in response to the number of errors exceeding a threshold number of errors (e.g. when the number of errors is greater than number of correctable errors, see 3:46-62 and 13:65-14:14); and
Hsiao does not teach the strikethrough limitations.
Kamata teaches applying a first read voltage applied to a selected word line (FIG. 12: applying AR to selected WL from t1-t3); apply a read voltage overdrive greater than the read voltage during read recovery (FIG. 12: applying CR+CGkick to selected WL right at t3); increase a precharge time during the read recovery (i.e. the given time, see 11:55-12:3. Also see annotated FIG. 12 above); and applying a second read voltage to the wordline (FIG. 12: applying CR to selected WL after CGkick).
Since Hsiao and Kamata are both from the same field of endeavor, the purpose disclosed by Kamata would have been recognized in the pertinent art of Hsiao.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to replace voltage V(2)6 applied to selected WL of Hsiao with voltage waveform between t3-t5 applied to selected WL of Kamata in order to temporary increase amount of charge on BL for better reading and sensing of memory device (see 11:55-12:3).
Regarding dependent claim 9, Hsiao teaches wherein the apparatus is a three-dimensional NAND (3D NAND) device (see 11:30-47).
Regarding dependent claim 10-11, Hsiao does explicitly teach wherein the 3D NAND device includes polysilicon (poly) channel traps. However, it would have been obvious to one with ordinary skill in the art to realize that polysilicon is commonly used as channel material in 3D NAND device ), and the applied read voltage causes detrapping of electrons in the poly channel traps.
Claims 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Hsiao in view of Kamata in view of US 11,393,533 to Zhan et al. (hereafter Zhan).
Hsiao and Kamata teach, as applied in prior rejection of claim 8, all claimed subject matter except further limitations set forth in the following claims.
Regarding dependent claims 12-13, Zhan teaches wherein the controller is configured to change trim settings in response to the number of errors exceeding the threshold number of errors; and change trim settings by increasing a precharge time (see 10:61-11:9).
Since Hsiao, Kamata and Zhan are both from the same field of endeavor, the purpose disclosed by Zhan would have been recognized in the pertinent art of Hsiao and Kamata.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to change the trim settings by increasing precharge time as suggested by Zhan in order to improve the number of errors in read operation in the memory device of Hsiao.
Regarding dependent claims 14-15, Zhan does not explicitly teach wherein the precharge time is greater than 2 microseconds in response to the wordline including triple level cells (TLCs), and wherein the precharge time is greater than 5 microseconds in response to the wordline including quad-level cells (QLCs). However, it would have been obvious to one with ordinary skill in the art to realize that value for increase precharge time is often a design choice depending on the type of memory device.
Claims 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kamata.
Regarding dependent claims 17-20, Kamata does not explicitly describe the recited features. However, there are similarity in applying voltages to selected word line between Kamata and FIG. 4 of the present invention.
It would have been obvious to one with ordinary skill in the art to realize that a recitation of the intended use of the claimed invention must result in a method difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art method is capable of performing the intended use, then it meets the claim. MPEP § 2114.
Response to Arguments
Applicant's arguments filed 04/03/2026 have been fully considered but they are not persuasive.
Examiner kindly refers Applicant to above rejection for details.
Claims 1, 3-20 maintain rejected.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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May 15, 2026
/VANTHU T NGUYEN/Primary Examiner, Art Unit 2824
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