DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 10-11 and 14-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shim et al. (US 2019/0378825).
Regarding claim 1, Shim discloses a package comprising:
a first substrate (100, fig. 1 and paragraph 0015);
an integrated device coupled to the first substrate (300, fig. 1 and paragraph 0015), wherein the integrated device comprises a plurality of back side metallization interconnects (CP3, fig. 1 and paragraph 0024); and
a second substrate (500,fig. 1 and paragraph 0030) coupled to the first substrate through a first plurality of solder interconnects (512, fig. 1 and paragraph 0035), wherein the second substrate is coupled to the plurality of back side
metallization interconnects through a second plurality of solder interconnects (514, fig. 1 and paragraph 0035).
Regarding claim 2, Shim further discloses an encapsulation layer located
between the first substrate and the second substrate (400, fig. 1 and paragraph 0015).
Regarding claim 3, Shim further discloses wherein the second plurality of solder interconnects (514, fig. 1) touch the plurality of back side metallization interconnects (CP3, fig. 1 and paragraph 0035).
Regarding claim 4, Shim further discloses wherein the second substrate comprises:
at least one dielectric layer; and
a plurality of interconnects (500, fig. 1 and paragraph 0031).
Regarding claim 5, Shim further discloses wherein the second plurality of solder interconnects is coupled to the plurality of interconnects (fig. 1).
Regarding claim 10, Shim further discloses an encapsulation layer located between the first substrate and the second substrate (400, fig. 1 and paragraph 0028);
and
an underfill located between the integrated device and the first substrate (340, fig. 1 and paragraph 0046).
Regarding claim 11, Shim further discloses wherein the underfill includes a different material or a different composition from the encapsulation layer located between the first substrate and the second substrate (paragraphs 0028, 0046).
Regarding claim 14, Shim further discloses wherein the integrated device is coupled to the first substrate through a plurality of pillar interconnects and/or a third plurality of solder interconnects (305, fig. 1 and paragraph 0023).
Regarding claim 15, Shim further discloses wherein the second substrate includes a cavity (fig. 1 and paragraphs 0004-0006), and
wherein the cavity of the second substrate is at least partially filled with an
encapsulation layer (400, fig. 1 and paragraph 0028, note: limitations are met by flipping the first substrate and the second substrate).
Regarding claim 16, Shim further discloses wherein the second plurality of solder interconnects is located at least partially in the cavity of the second substrate (fig. 1).
Regarding claim 17, Shim further discloses wherein the integrated device comprises a die substrate, and wherein the die substrate is free of any through substrate vias (300, fig. 1 and paragraph 0025, note: Shim discloses the chip may include a chip via 330, therefore implies optional, as such, no via is anticipated)
Regarding claim 18, Shim further discloses wherein the plurality of back side metallization interconnects is coupled to a surface of the die substrate (fig. 1).
Regarding claim 19, Shim further discloses wherein an electrical path through the plurality of back side metallization interconnects does not extend through the die substrate (paragraph 0024).
Regarding claim 20, Shim further discloses wherein an electrical path to and/or from the integrated device only extend through a front side of the integrated device (fig. 1 and paragraph 0023).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-9 and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Shim et al. (US 2019/0378825).
Regarding claims 6-9, Shim discloses the package of claim 4 as mentioned above. Shim does not explicitly disclose the use of post interconnects as claimed in claims 6-9. However, the interchangeability of pad interconnects and post interconnects and pillar interconnects was well known in the art at the time of filing and would therefore be deemed obvious to one of ordinary skill in the art at the time of filing.
Regarding claims 12-13, Shim discloses the package of claim 1 as mentioned above and further discloses a second integrated device or package (600, fig. 1 and paragraph 0032) coupled to the second substrate through a plurality of bond wires (610, fig. 1 and paragraph 0032). Shim does not disclose solder interconnects. However, the interchangeability of bond wire interconnects and solder interconnects was well known in the art at the time of filing and would therefore be deemed obvious to one of ordinary skill in the art at the time of filing.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent Application Publication 2021/0280507 discloses a relevant stacked package.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS M MENZ whose telephone number is (571)272-1877. The examiner can normally be reached Monday-Friday 8:00am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DOUGLAS M MENZ/ Primary Examiner, Art Unit 2897 7/19/26
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