DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 11 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Zhang CN 11465128.
As to claim 1, Zhang teaches A semiconductor device, comprising: a substrate (101 and item 103 see e.g. figure 2); a doped region on the substrate (item 107); a gate structure on the substrate (item 111,113, 115 and 119); an insulating layer covering the gate structure and the doped region (figure 3 item 121); a first contact extending through the insulating layer and connected to the gate structure (figures 9-13 item 155); and a first film formation inhibition pattern disposed between the gate structure and the first contact, wherein the first film formation inhibition pattern includes a halogen element :
The gate contact 155 may comprise a conductive material, such as W, Al, Cu, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Co, Ni, or a combination thereof, and the like. In some embodiments, the gate contact 155 comprises tungsten. The gate contact 155 may be formed by any suitable method, such as CVD, plasma enhanced CVD (PECVD), MOCVD, thermal CVD, PVD, ALD, and the like. In some embodiments, a thermal CVD process is used to perform a deposition process from bottom to top. WF6 and H2 can be used as a process gas (when tungsten is to be grown) to perform a deposition process from down to up, and the resulting gate electrode contact 155 comprises fluorine. In some embodiments, the width W2 of the grid electrode contact 155 across the bottom surface of the grid electrode contact 155 is in the range of 8.5nm to 9.7nm, and the width W3 of the grid electrode contact 155 is measured to be flush with the top surface of the ESL 121, and is in the range of 10.9nm 11.6nm However, any suitable size can be used.
Fluorine is a halogen.
Since the contact is multiple atomic layer fluorine portions of the tungsten are between the gate and the remaining portion of the contact. Thus, the outer surface of the contact is a film formation inhibition pattern.
b. As to claim 11, Zhang teaches wherein the first film formation inhibition pattern is extended into a space between the insulating layer and the first contact (the outer portion of item 155 is between the insulating layer and the inner portion of item 155.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-5 and 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Nakahata (6635938).
b. As to claims 2 and 12, Zhang teaches A semiconductor device, comprising: a substrate (101 and item 103 see e.g. figure 2); a doped region on the substrate (item 107); a gate structure on the substrate (item 111,113, 115 and 119); an insulating layer covering the gate structure and the doped region (figure 3 item 121); a first contact extending through the insulating layer and connected to the gate structure (figures 9-13 item 155); and a first film formation inhibition pattern disposed between the gate structure and the first contact, wherein the first film formation inhibition pattern includes a halogen element :
The gate contact 155 may comprise a conductive material, such as W, Al, Cu, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Co, Ni, or a combination thereof, and the like. In some embodiments, the gate contact 155 comprises tungsten. The gate contact 155 may be formed by any suitable method, such as CVD, plasma enhanced CVD (PECVD), MOCVD, thermal CVD, PVD, ALD, and the like. In some embodiments, a thermal CVD process is used to perform a deposition process from bottom to top. WF6 and H2 can be used as a process gas (when tungsten is to be grown) to perform a deposition process from down to up, and the resulting gate electrode contact 155 comprises fluorine. In some embodiments, the width W2 of the grid electrode contact 155 across the bottom surface of the grid electrode contact 155 is in the range of 8.5nm to 9.7nm, and the width W3 of the grid electrode contact 155 is measured to be flush with the top surface of the ESL 121, and is in the range of 10.9nm 11.6nm However, any suitable size can be used.
Since the contact is multiple atomic layer fluorine portions of the tungsten are between the gate and the remaining portion of the contact. Thus, the outer surface of the contact is a film formation inhibition pattern.
Zhang further teaches wherein the gate structure comprises: a gate metal pattern (items 109 and 113)
(Next, a gate structure 109 is formed over the channel region of the semiconductor fin 103 in the opening between the gate spacers 111. Each gate structure 109 may be, for example, a metal gate structure including a gate electrode, one or more work function layers around the gate electrode, and a gate dielectric layer in the vicinity of the work function layer. In some embodiments, the gate dielectric layer comprises one or more dielectric layer, such as silicon oxide, silicon nitride, metal oxide, metal silicate and one or more layers. The gate electrode may have a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or a plurality of layers thereof. For example, although a single-layer gate electrode is shown in FIG. 1 A, the gate electrode may include any number of liner, any number of work function adjusting layer and filling material. Each feature of the gate structure 109 may be deposited, and then planarized by, for example, chemical mechanical polishing (CMP), so that the top surface of the features of the gate structure, 109, is flush with the top surface of the gate spacer 111. Then, the material of the gate structure 109 may be recessed using, for example, one or more wet or dry etching processes.);
and a gate capping pattern on the gate metal pattern (item 115), wherein the first contact is provided to extend through the insulating layer and the gate capping pattern and is extended to a level that is lower than a bottom surface of the gate capping pattern (figures 9 and 10 item 150/155).
Fluorine is a halogen.
Zhang teaches it is a FET and the gate dielectric (FIG. 1 A depicts a perspective view of a semiconductor component 100, such as a FinFET component according to some embodiments. FIG. 1 B depicts a detailed cross-sectional view of the region 500 shown in FIG. 1 A.)
Zhang does not explicitly state the gate insulating pattern under the metal gate between the channel and the metal gate.
This is well known the art to form Metal oxide semiconductor transistor see e.g. Nakahata item 6a between item 1 and 7.
Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to provide a gate insulator between the metal gate and the fin to provide the finfet of Zhang as a metal oxide semiconductor transistor allowing conventional designs and techniques to provide expected outcomes of functional transistors.
b. As to claim 3, Zhang teaches wherein the gate metal pattern comprises a recess defined at an upper portion of the gate metal pattern, wherein the first contact is provided at the recess, wherein the first film formation inhibition pattern is interposed between side and bottom surfaces of the recess and the first contact (see figures 10-12 item 113 is divots or Rougned which acts as a recess).
c. AS to claim 4, Zhang teaches wherein the gate capping pattern comprises silicon nitride
(Referring further to FIG. 1 A and FIG. 1B, a cover layer 115 (e.g., silicon nitride) is formed over the cover layer 113, also referred to as a sacrificial layer. The cover layer 115 may be used to cover the cover layer 113 during subsequent deposition of the etch stop layer (see FIG. 2). In some embodiments, the cover layer 115 is formed in a range of 12 nm to 29 nm of the height H2. The mask layer 115 may be deposited by any suitable process.)
and an interface between the gate capping pattern and the first film formation inhibition pattern includes a halogen element The outer surface of the contact is between the cap and the remaining portion of the contact.
d. As to claim 5, Zhang teaches that the gate and gate contact comprise tungsten.
The gate electrode may have a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or a plurality of layers thereof.
The gate contact 155 may comprise a conductive material, such as W, Al, Cu, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Co, Ni, or a combination thereof, and the like. In some embodiments, the gate contact 155 comprises tungsten.
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to form the contact and gate from tungsten to use conventional and known materials to provide expected outcomes of low resistance functional transistors.
d. As to claim 13, Zhang teaches wherein the first film formation inhibition pattern is interposed between the first contact and the insulating layer the outer portion of the contact which comprises Fluorine is between the insulator and inner portions of the contact.
Allowable Subject Matter
Claim 6 and 14 objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Prior art fails to teach and or suggest further comprising: a source/drain pattern extending through the insulating layer and connected to the doped region; and a second film formation inhibition pattern disposed between the insulating layer and the source/drain pattern, wherein the second film formation inhibition pattern includes a halogen element.
While Chouksey teaches treating the diffusion barriers with halogen around the silicide (paragraph 14). This would imply the barriers of 119 would contain fluorine figure 3, the contact through the insulating layer, item 165 figure 17, would not be treated with a halogen.
Claims 18-20 are allowed.
Zhang teaches As to claim 1 Zhang teaches A semiconductor device, comprising: a substrate (101 and item 103 see e.g. figure 2); a doped region on the substrate (item 107); a gate structure on the substrate (item 111,113, 115 and 119); an insulating layer covering the gate structure and the doped region (figure 3 item 121); a first contact extending through the insulating layer and connected to the gate structure (figures 9-13 item 155); and a first film formation inhibition pattern disposed between the gate structure and the first contact, wherein the first film formation inhibition pattern includes a halogen element :
The gate contact 155 may comprise a conductive material, such as W, Al, Cu, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Co, Ni, or a combination thereof, and the like. In some embodiments, the gate contact 155 comprises tungsten. The gate contact 155 may be formed by any suitable method, such as CVD, plasma enhanced CVD (PECVD), MOCVD, thermal CVD, PVD, ALD, and the like. In some embodiments, a thermal CVD process is used to perform a deposition process from bottom to top. WF6 and H2 can be used as a process gas (when tungsten is to be grown) to perform a deposition process from down to up, and the resulting gate electrode contact 155 comprises fluorine. In some embodiments, the width W2 of the grid electrode contact 155 across the bottom surface of the grid electrode contact 155 is in the range of 8.5nm to 9.7nm, and the width W3 of the grid electrode contact 155 is measured to be flush with the top surface of the ESL 121, and is in the range of 10.9nm 11.6nm However, any suitable size can be used. Zhang further teaches an isolation region on the substrate item 105.
Fluorine is a halogen.
Since the contact is multiple atomic layer fluorine portions of the tungsten are between the gate and the remaining portion of the contact. Thus, the outer surface of the contact is a film formation inhibition pattern.
For substantially the same reason as claims 6 and 14 Zhang in view of Chouskey do not suggest a source/drain contact extending through the insulating layer, connected to the source/drain pattern, and disposed on the source/drain pattern; a first film formation inhibition pattern disposed between the insulating layer and the gate contact; and a second film formation inhibition pattern disposed between the insulating layer and the source/drain pattern, wherein a level of a top surface of the source/drain pattern is higher than a level of a top surface of the gate metal pattern, and the first and second film formation inhibition patterns include a halogen element.
Huang 201901578405 teaches doping barriers with fluorine that are in contact with the source drain (item 238) but precludes Fluorine from around the gate thus Huang would teach away from Zhang.
Conclusion
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/MATTHEW L. REAMES/
Primary Examiner
Art Unit 2896
/MATTHEW L REAMES/ Primary Examiner, Art Unit 2896
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