DETAILED ACTION
Examiner’s Note
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs, columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 8-10 and 13-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Rabkin et al. (US 20140252454 A1, hereinafter Rabkin’454).
Regarding independent claim 1, Rabkin’454 teaches, “An apparatus (fig. 1-18; ¶ [0001] - ¶ [0211]), comprising:
a first source/drain region (‘S/D’, fig. 11B) and a second source/drain region (‘Source/drain’) formed on a substrate (‘Substrate’, fig. 9);
a channel (‘Body’) separating the first source/drain region and the second source/drain region;
a gate (507) separated from the channel by a gate dielectric material (505), wherein:
the first source/drain region, the second source/drain region, the channel and the gate form a vertical thin film transistor (TFT) (504);
a first end of the channel (lower end) is coupled to the first source/drain region (‘S/D’) and extends beyond a first end of the gate (507); and
a second end of the channel (upper end) is coupled to the second source/drain region (‘Source/drain’) and does not extend beyond a second end of the gate (upper end) that is opposite the first end of the gate;
a contact (526) in the substrate coupled to the first source/drain region (‘S/D’); and
a sense line (‘vertically oriented bit line’, ¶ [0163]) coupled to the second source/drain region”.
Regarding claim 2, Rabkin’454 further teaches, “The apparatus of claim 1, wherein the first source/drain region (‘S/D’) is outside a gate region and the second source/drain region (‘Source/drain’) is within the gate region”.
Regarding independent claim 8, Rabkin’454 teaches, “A memory device (fig. 1-18; ¶ [0001] - ¶ [0211]), comprising:
an array of memory cells, wherein the array of memory cells includes a plurality of vertical thin film transistors (TFTs) (‘3D memory array’, ¶ [0027], ¶ [0159] - ¶ [0160], figs. 1, 11B), wherein each of the vertical TFTs (504) includes:
a semiconductor material, wherein the semiconductor material includes a first source/drain region (‘S/D’, fig. 11B), a second source/drain region (‘Source/drain’), and a channel (‘Body’) separating the first source/drain region and the second source/drain region; and
a gate (504) separated from the channel by a gate dielectric material (505), wherein:
a first end of the channel (lower end) is coupled to the first source/drain region (‘S/D’) and extends beyond a first end of the gate (507); and
a second end of the channel (upper end) is coupled to the second source/drain region (‘Source/drain’) and does not extend beyond a second end of the gate (upper end) that is opposite the first end of the gate”.
Regarding claim 9, Rabkin’454 further teaches, “The memory device of claim 8, wherein the gate dielectric material is an oxide material (¶ [0193])”.
Regarding claim 10, Rabkin’454 further teaches, “The memory device of claim 8, wherein the semiconductor material is a polysilicon material (¶ [0159])”.
Regarding claim 13, Rabkin’454 further teaches, “The memory device of claim 8, wherein the array memory cells is a three-dimensional vertical array of memory cells (‘3D memory array’, ¶ [0027], ¶ [0159] - ¶ [0160], figs. 1, 11B)”.
Regarding claim 14, Rabkin’454 further teaches, “The memory device of claim 8, wherein each memory cell (¶ [0170], figs. 6, 12A) in the array of memory cells includes a horizontal access line (536), a storage material coupled to the horizontal access line, and a dielectric material (534) coupled to the storage material in a horizontal direction”.
Regarding independent claim 15, Rabkin’454 teaches, “A method (fig. 1-18; ¶ [0001] - ¶ [0211]), comprising:
forming a dielectric material (inter metal dielectric layer, fig. 16A) on a substrate material (‘substrate layers’, ¶ [0188]);
forming a semiconductor material (1618, 1621, 1622, 1624, fig. 16B-16D) on the dielectric material;
forming a plurality of vertical openings (between adjacent pillars 1625 in fig. 16E) through the semiconductor material to form vertical thin film transistors (TFTs) having vertical sidewalls adjacent the plurality of vertical openings,
wherein each of the vertical TFTs includes a first source/drain region (fig. 11B, 16E), a second source/drain region, and a channel separating the first source/drain region and the second source/drain region;
forming a gate dielectric material (1628, fig. 16F) in the vertical openings;
forming a gate electrode material (507, fig. 16G) over the vertical TFTs and the gate dielectric material (1628), wherein the gate dielectric material separates the gate electrode material and the channel; and
recessing the gate electrode material (fig. 16G, ¶ [0194]) from the vertical TFTs to form a gate (507),
wherein:
a first end of the channel is coupled to the first source/drain region and extends beyond a first end of the gate; and a second end of the channel is coupled to the second source/drain region and does not extend beyond a second end of the gate that is opposite the first end of the gate (see fig. 16G with fig. 11B)”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 3-7, 11-12 and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Rabkin’454.
Regarding claim 3-7, 11-12 and 19-20, the instant claims describe functional/operational language of the claimed device in the independent claim 1. As described above, Rabkin’454 teaches all the elements of the claimed apparatus and the subject limitations do not make the claimed structure different from the one described in the prior art. This functional/operational language is merely a way to operate the same analogous device structure.
A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). See MPEP § 2144.02.
Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). “When the PTO shows a sound basis for believing that the products of the applicant and the prior art are the same, the applicant has the burden of showing that they are not.” In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990). Therefore, the prima facie case can be rebutted by evidence showing that the prior art products do not necessarily possess the characteristics of the claimed product. In re Best, 562 F.2d at 1255, 195 USPQ at 433. See MPEP 2112.01.
While features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function alone. If the examiner has a "reason to believe" that a functional limitation can be performed inherently without modification by the prior art structure, the examiner should establish a prima facie case, and then shift the burden to the applicant to prove otherwise. See In re Swinehart, 169 USPQ 226 (CCPA 1971); In re Schreiber, 44 USPQ2d 1429 (Fed. Cir. 1997).
Regarding claims 16-18, Rabkin’454 teaches the claimed elements e.g., gate, dielectric material and vertical TFT. While the cited prior art does not explicitly disclose the particular claimed value, the teachings therein would have led one of ordinary skill in the art at the time of invention to discover the claimed value during routine experimentation and optimization.
The Applicant has not presented persuasive evidence that the claimed values are for a particular purpose that is critical to the overall claimed invention (i.e., the invention would not work without the specific claimed values). Also, the applicant has not shown that the claimed values produce a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. Thus, because it has been held that where “the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation" (see MPEP 2144.05; In re Aller, 220 F.2d 454, 456, 105 USPQ 223, 225 (CCPA 1955)), it would have been obvious to add the claimed values to the rest of the claimed invention.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M HOQUE whose telephone number is (571)272-6266 and email address is mohammad.hoque@uspto.gov. The examiner can normally be reached 9AM-7PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached on (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817
Prosecution Insights