DETAILED ACTION
This action is responsive to communications: application field on 05/08/2026.
Applicant amended claims 1, 4, 7-8, 11, 14-15, and 18; cancelled claims 5, 12, and 19; added new claims 21-23. Claims 1-4, 6-11, 13-18, and 20-23 are pending. Claims 1, 8, and 15 are independent.
Examiner Notes
A) MPEP 2163 guidelines teach that drawing and specification must be examined to assess whether an originally-filed claim has adequate support in the written disclosure and/or the drawings. Possession may be shown by a clear depiction of the invention in detailed drawings. B) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. C) Per MPEP 2173.04 “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. D) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. Per MPEP 2141.02 VI prior art must be considered in its entirety. E) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103.
Notice of Pre-AIA or AIA Status
3. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Domestic Priority
4. See ADS for domestic CON priority details.
Applicant is requested to check other claim informality, language issues (e.g. antecedent issues, redundant limitation issues, grammar issues) for all claims to expedite prosecution since informality scrutiny in this office action is not exhaustive and applicant’s co-operation is sought in this regard.
Claim Rejections - 35 USC § 112
5. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. — The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
6a. Claims 1, 8, and 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential elements, such omission amounting to a gap between the elements. Such omission is tantamount to omitting essential structural cooperative relationships of elements also. See MPEP § 2172.01. A claim which omits subject matter disclosed to be essential to the invention as described in the specification or in other statements of record may be rejected as failing to claim the subject matter that the inventor or a joint inventor regards as the invention (See In re Mayhew, 527 F.2d 1229, 188 USPQ 356 (CCPA 1976); In re Venezia, 530 F.2d 956, 189 USPQ 149 (CCPA 1976); and In re Collier, 397 F.2d 1003, 158 USPQ 266 (CCPA 1968)). Such essential matter may include missing elements, steps or necessary structural cooperative relationships of elements described by the applicant(s) as necessary to practice the invention. For example, In re Mayhew, the Court of Customs and Patent Appeals (CCPA) held that claims were not enabled under 35 U.S.C. § 112 because they omitted a cooling bath and its specific location, which were deemed essential elements based on the specification. The court found that the specification indicated these elements were critical for the invention to function as described, and their omission from the claims rendered them not supported by an enabling disclosure. Fact pattern is similar in our particular context for the instant application.
For claim 1, 8, and 15, omitted elements are described in bold in association with each limitation:
Claim 1:
first trigger includes one or more of:
determining that a number of program/erase cycles of the memory subsystem satisfies a program/erase cycle threshold; and
determining that an amount of time passed following the configuring the size of the write buffer as the first amount of volatile memory satisfies a time threshold;
(Missing elements, steps or necessary structural cooperative relationships of elements are: sudden events (e.g. power loss, measurements), vehicles of function (back-up capacitor capacity, states, degradation state), and correlation with first trigger, second trigger. Due to omission of elements (related to first and second trigger), described functional events are vague, ambiguous and subject to numerous multiple interpretations hence indefinite)
Claim 8
first trigger includes one or more of:
determining that a number of program/erase cycles of the memory subsystem satisfies a program/erase cycle threshold; and
determining that an amount of time passed following the configuring the size of the write buffer as the first amount of volatile memory satisfies a time threshold;
(See above in claim 1)
Claim 15:
first trigger includes one or more of:
determining that a number of program/erase cycles of the memory subsystem satisfies a program/erase cycle threshold; and
determining that an amount of time passed following the configuring the size of the write buffer as the first amount of volatile memory satisfies a time threshold;
(See above in claim 1)
See art rejection for the interpretation of the limitations.
6b. All dependent claims inclusive of Claims 1-4, 6-11, 13-18, and 20-23 are rejected under this category. See art rejection for the interpretation of the art rejected claims.
Claim Rejections - 35 USC § 103
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
8. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
9. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
10. Claims 1-4, 6-11, 13-18, and 20 is/are rejected under 35 U.S.C. 103 as being obvious over Merry et al. (US 2008/0189452 A1), in view of Zheng et al. (US 2015/0363272 A1).
Regarding independent claim 1, Merry teaches a method (para [0006], Abstract: method of employing “variable-size write buffer”) comprising:
configuring a size of a write buffer (Fig. 1: 135 “write buffer”. See Abstract: “variable-size write buffer”) as a first amount of volatile memory (para [0006], para [0020]: e.g. write buffer maximum size),
wherein the write buffer stores data to be written to non-volatile memory (para [0006], Abstract);
detecting a first trigger to update the size of the write buffer (para [0039], para [0042]: e.g. monitored operating condition are used to update size of write buffer. See also para [0022], para [0023], para [0044]),
wherein the first trigger includes one or more of:
determining that a number of program/erase cycles of the memory subsystem satisfies a program/erase cycle threshold; and (para [0039]: e.g., condition (i) or combination "...controller...may...select the appropriate buffer size...based on any one or more of the following...usage statistics reflective of the wear state, and thus the expected remaining life, of the non-volatile memory...". Monitoring this condition measures capability of backup device (used in case of power loss) see para [0042] teaches "...charge status of the battery...")
determining that an amount of time passed following the configuring the size of the write buffer as the first amount of volatile memory satisfies a time threshold; and (para [0039]: e.g., condition (d) or combination of the multiple conditions listed. Interpreted in light of Specification para [0035], indicating the capacitor’s performance is measured and that is used to determine whether to resize the buffer; here, Merry has measured the battery as explained in para [0006] and para [0042]: degradation status or charge status of “backup power source” is below “…threshold…” which is indicative of data written to non-volatile memory following a power loss event i.e. Merry determines based upon the backup power source “performance” the amount of data that can be written is less than the current size of buffer. See also Fig. 1 and Fig. 2)
in response to detecting the first trigger, reducing the size of the write buffer to a second amount of volatile memory (see para [0042], para [0006]: Merry’s controller will update the size of the write buffer based upon the charge level on the battery i.e. “capacitor performance”. When performing such update to the size of the buffer, the controller knows the amount of data to be written based upon the current battery charge level would be less than the current write buffer size, which is why will reduce the write buffer size when batter’s charge level is less than a threshold, as explained in para [0042] so that the risk of data loss can be reduced as explained in para [0006]. When charge level is less than threshold, meaning less can be written than would be expected based on that battery’s threshold amount, then write buffer size is reduced. Threshold amount, which represents the amount of data that is expected to be written to the device in a power loss).
Merry is silent with respect to using specific data back-up scheme during power loss and silent with respect to back-up device degradation performance details.
Zheng teaches detecting a first trigger to update the size of the write buffer (detecting power-loss interruption requiring data back-up. para [0127]-para [0131),
wherein the first trigger includes measuring an amount of data that can be written from the write buffer to the non-volatile memory in a power loss based upon current capacitor performance (para [0038]: “capacitor” used in reserve power source. See also para [0127]-para [0131])
Merry and Zheng are in the same field of endeavor since Zheng teaches a system (Fig. 2: 200 computing system with “adaptive back-up mechanism”. See Fig. 7 adaptive back-up operation and Fig. 6 illustrated components and functionality) comprising: a plurality of memory devices (Fig. 2: 206, 204); and a processing device (Fig. 2: 208 local memory controller), operatively coupled with the plurality of memory devices (See Fig. 2), to: allot a first amount of volatile memory to a write buffer (para [0130]: “write buffer entry size 782” when normal calculated volatile memory utility is used, see Fig. 7:702. See also para [0104], para [0093]-para [0094]), wherein the write buffer stores batches of data to be written to non-volatile memory (“write buffer entries” or “write entry”, see e.g. para [0102] and para [0103]. Data back-up during “…normal operation or without detecting the power failure…”); detect a trigger (Fig. 7: 710 “detect change”) to update the allotment of volatile memory to the write buffer (Fig. 7: 710 in context of para [0106]: “…detect change module … monitors or detects conditions that can affect backing up the data from the volatile memory…to the nonvolatile memory. para [0080]: “…adaptive back-up system … provides modification to the transfer mechanism for the volatile memory …for backing up data when the power failure … detected…”); and in response to the trigger (e.g. “power failure” Fig. 7: 710, 706, 708, 710, 712), reduce the volatile memory allotted (para [0130]: “write buffer entry size 782”) to the write buffer to a second amount (Equation 1 and equation 2 in context of para [0128]-para [0131]: “write entry size” is reduced to maximize “write entries commit” within calculated available backup time. See also “…The calculate buffer size module … determines the amount of data in the volatile memory… to be backed up….”). Thus, Merry and Zheng are in analogous field of art.
Employing Zheng ‘s capacitor with calculation module and dynamic reliability checking enables precise calculation of buffer size and at the same time maximizes data throughput/ increases data transmission speed.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Zheng into the teachings of Merry such that backup capacitors for power-loss can be employed in the method and apparatus in order reduce risk of data loss and increase operational speed.
Regarding claim 2, Merry and Zheng teach the method of claim 1. Merry teaches further comprising: detecting a second trigger to update the size of the write buffer (see in context of para [0023], para [0039], para [0044]: multiple monitoring parameters are discussed); and in response to the second trigger, reducing the size of the write buffer from the second amount to a third amount (see para [0021], Fig. 1: various buffer size and combinations).
Merry is silent with respect to remaining provisions of this claim as it pertains to serially utilizing two triggers to adjust buffer size.
Zheng teaches wherein the processing device is further to: detect a second trigger to update the size of the write buffer (Zheng Fig. 7 loop algorithm teaches multiple triggers can be used sequentially to configure buffer size); and
in response to detecting the second trigger, reduce the size of the write buffer from the second amount to a third amount (see Fig. 7 loop in context of equation 1, equation 2: multiple triggers can be input together in equation to calculate optimal size of buffer).
Zheng and Merry are in analogous field of art.
Employing Zheng’s algorithmic method enables precise calculation of buffer size and at the same time maximizes data throughput/ increases data transmission speed.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Zheng into the teachings of Merry such that a robust method with additional software algorithm for controlling the write buffer size can be employed in order to in order reduce risk of data loss and increase operational speed.
Regarding claim 3, Merry and Zheng teach the method of claim 2. Merry teaches wherein the second trigger includes receiving an input (monitored parameters, see e.g. para [0039]) to update the size of the write buffer (see details in para [0039]. See also para [0022], para [0023], para [0044]. See Abstract “…adjusting the size of the write buffer based on monitored operating conditions, such as the temperature, the stability/consistency of a power signal received from the host system, and/or the elapsed time since the storage subsystem was last powered up….”. Monitored params are used to reduce or adjust size of write buffer).
Regarding claim 4, Merry and Zheng teach the method of claim 2. Merry teaches
the second trigger includes one or more of:
determining that the amount of time passed following the configuring the size of the write buffer as the first amount of volatile memory satisfies the time threshold; and determining that the number of program/erase cycles of the memory subsystem satisfies the program/erase cycle threshold. (See in context of para [0039], (a-i) and para [0044] in combination).
Regarding claim 6, Merry and Zheng teach the method of claim 1. Merry teaches further comprising:
receiving a write command from a host system (para [0031], para [0033]-para [0034]),
the write command including data (Fig. 2, para [0020], para [0033]-para [0034]);
writing the data to the write buffer (Fig. 1, Fig. 2 and para [0006], para [0019], para [0020]); and
writing data from the write buffer to the non-volatile memory (Fig. 1, Fig. 2 and para [0006], para [0019], para [0020]).
Regarding claim 7, Merry and Zheng teach the method of claim 1. Merry teaches the second amount of volatile memory corresponds to an amount of volatile memory that can be written from the write buffer to the non-volatile memory in a power loss based on degraded capacitor performance. (para [0042]: based on “back-up power source” degradation and remaining capability, buffer size is reduced adjusted. See para [0021]-para [0023], para [0006], para [0042], para [0044]: reduced buffer size. para [0042]: back-up power source).
Regarding independent claim 8, Merry teaches a non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to (Non transitory computer-readable medium is conventional item used conventionally to store computer programs to perform generic computer functions that are well-understood, routine, and conventional activities previously known to the pertinent industry):
configure a size of a write buffer of a memory subsystem (Fig. 1: 135 “write buffer”. See Abstract: “variable-size write buffer”. See Fig. 1) as a first amount of volatile memory (para [0006], para [0020]: e.g. write buffer maximum size),
wherein the write buffer stores data to be written to non-volatile memory (para [0006], Abstract);
detect a first trigger to update the size of the write buffer (para [0042], para [0022], para [0023]: e.g. monitored operating condition are used to update size of write buffer. See also para [0039], para [0044]),
wherein the first trigger includes one or more of:
determining that a number of program/erase cycles of the memory subsystem satisfies a program/erase cycle threshold; and (para [0039]: e.g., condition (i) or combination "...controller...may...select the appropriate buffer size...based on any one or more of the following...usage statistics reflective of the wear state, and thus the expected remaining life, of the non-volatile memory...". Monitoring this condition measures capability of backup device (used in case of power loss) see para [0042] teaches "...charge status of the battery...")
determining that an amount of time passed following the configuring the size of the write buffer as the first amount of volatile memory satisfies a time threshold;
in response to detecting the first trigger, reduce the size of the write buffer to a second amount of volatile memory (para [0039]: e.g., condition (d) or combination of the multiple conditions listed. Interpreted in light of Specification para [0035], indicating the capacitor’s performance is measured and that is used to determine whether to resize the buffer; here, Merry has measured the battery as explained in para [0006] and para [0042]: degradation status or charge status of “backup power source” is below “…threshold…” which is indicative of data written to non-volatile memory following a power loss event i.e. Merry determines based upon the backup power source “performance” the amount of data that can be written is less than the current size of buffer. See also Fig. 1 and Fig. 2).
Merry is silent with respect to using specific data back-up scheme during power loss and silent with respect to back-up device degradation performance details.
Zheng teaches detecting a first trigger to update the size of the write buffer (detecting power-loss interruption requiring data back-up. para [0127]-para [0131),
wherein the first trigger includes measuring an amount of data that can be written from the write buffer to the non-volatile memory in a power loss based upon current capacitor performance (para [0038]: “capacitor” used in reserve power source. See also para [0127]-para [0131])
Merry and Zheng are in the same field of endeavor since Zheng teaches a system (Fig. 2: 200 computing system with “adaptive back-up mechanism”. See Fig. 7 adaptive back-up operation and Fig. 6 illustrated components and functionality) comprising: a plurality of memory devices (Fig. 2: 206, 204); and a processing device (Fig. 2: 208 local memory controller), operatively coupled with the plurality of memory devices (See Fig. 2), to: allot a first amount of volatile memory to a write buffer (para [0130]: “write buffer entry size 782” when normal calculated volatile memory utility is used, see Fig. 7:702. See also para [0104], para [0093]-para [0094]), wherein the write buffer stores batches of data to be written to non-volatile memory (“write buffer entries” or “write entry”, see e.g. para [0102] and para [0103]. Data back-up during “…normal operation or without detecting the power failure…”); detect a trigger (Fig. 7: 710 “detect change”) to update the allotment of volatile memory to the write buffer (Fig. 7: 710 in context of para [0106]: “…detect change module … monitors or detects conditions that can affect backing up the data from the volatile memory…to the nonvolatile memory. para [0080]: “…adaptive back-up system … provides modification to the transfer mechanism for the volatile memory …for backing up data when the power failure … detected…”); and in response to the trigger (e.g. “power failure” Fig. 7: 710, 706, 708, 710, 712), reduce the volatile memory allotted (para [0130]: “write buffer entry size 782”) to the write buffer to a second amount (Equation 1 and equation 2 in context of para [0128]-para [0131]: “write entry size” is reduced to maximize “write entries commit” within calculated available backup time. See also “…The calculate buffer size module … determines the amount of data in the volatile memory… to be backed up….”). Thus, Merry and Zheng are in analogous field of art.
Employing Zheng ‘s capacitor with calculation module and dynamic reliability checking enables precise calculation of buffer size and at the same time maximizes data throughput/ increases data transmission speed.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Zheng into the teachings of Merry such that backup capacitors for power-loss can be employed in the method and apparatus in order reduce risk of data loss and increase operational speed.
Regarding claim 9, Merry and Zheng teach the non-transitory computer-readable storage medium of claim 8, wherein the processing device is further to: detect a second trigger to update the write buffer configuration; and in response to the second trigger, reduce the size of the write buffer from the second amount to a third amount. (this claim is drafted as in non-transitory computer-readable medium format, substantially identical to the method recited in claim 2, and is therefore rejected for the same reasons as claim 2).
Regarding claim 10, Merry and Zheng teach the non-transitory computer-readable storage medium of claim 9, wherein the second trigger includes receiving an input to update the size of the write buffer. (this claim is drafted as in non-transitory CRM format, substantially identical to the method recited in claim 3, and is therefore rejected for the same reasons as claim 3)
Regarding claim 11, Merry and Zheng teach the non-transitory computer-readable storage medium claimed. (This claim is drafted as in non-transitory CRM format, substantially identical to the method recited in claims 1-4, and is therefore rejected for the same reasons as claims 1-4)
Regarding claim 13, Merry and Zheng teach the non-transitory computer-readable storage medium of claim 8, wherein the processing device is further to: receive a write command from a host system, the write command including data; write the data to the write buffer; and write data from the write buffer to the non-volatile memory. (this claim is drafted as in non-transitory CRM format, substantially identical to the method recited in claim 6, and is therefore rejected for the same reasons as claim 6)
Regarding claim 14, Merry and Zheng teach the non-transitory computer-readable storage medium described. (this claim is drafted as in non-transitory CRM format, substantially identical to the method recited in claims 1-5, and is therefore rejected for the same reasons as claims 1-5)
Regarding independent claim 15, Merry teaches a system (Fig. 1 storage system) comprising:
a plurality of memory devices (Fig. 1: 116, para [0047]: “…nonvolatile storage 116 may comprise a plurality of solid-state storage devices coupled to the controller...”); and
a processing device (Fig. 1: 110, 114), operatively coupled with the plurality of memory devices (Fig. 1: 116), to:
configure a size of a write buffer (Fig. 1: 135 “write buffer”. See Abstract: “variable-size write buffer”) as a first amount of volatile memory (para [0006], para [0020]: e.g. write buffer maximum size),
wherein the write buffer stores data to be written to non-volatile memory (para [0006]);
detect a first trigger to update the size of the write buffer (para [0042], para [0022], para [0023]: e.g. monitored operating condition are used to update size of write buffer. See also para [0039], para [0044]),
wherein the first trigger includes one or more of:
determining that a number of program/erase cycles of the memory subsystem satisfies a program/erase cycle threshold (para [0039]: e.g., condition (i) or combination "...controller...may...select the appropriate buffer size...based on any one or more of the following...usage statistics reflective of the wear state, and thus the expected remaining life, of the non-volatile memory...". Monitoring this condition measures capability of backup device (used in case of power loss) see para [0042] teaches "...charge status of the battery..."); and
determining that an amount of time passed following the configuring the size of the write buffer as the first amount of volatile memory satisfies a time threshold (para [0039]: e.g., condition (d) or combination of the multiple conditions listed. Interpreted in light of Specification para [0035], indicating the capacitor’s performance is measured and that is used to determine whether to resize the buffer; here, Merry has measured the battery as explained in para [0006] and para [0042]: degradation status or charge status of “backup power source” is below “…threshold…” which is indicative of data written to non-volatile memory following a power loss event i.e. Merry determines based upon the backup power source “performance” the amount of data that can be written is less than the current size of buffer. See also Fig. 1 and Fig. 2);
in response to detecting the first trigger, reduce the size of the write buffer to a second amount of volatile memory (see para [0042], para [0006]: Merry’s controller will update the size of the write buffer based upon the charge level on the battery i.e. “capacitor performance”. When performing such update to the size of the buffer, the controller knows the amount of data to be written based upon the current charge level would be less than the current write buffer size, which is why will reduce the write buffer size when batter’s charge level is less than a threshold, as explained in para [0042] so that the risk of data loss can be reduced as explained in para [0006]. When charge level is less than threshold, meaning less can be written than would be expected based on that battery’s threshold amount, then write buffer size is reduced. Threshold amount, which represents the amount of data that is expected to be written to the device in a power loss),
wherein the second amount of volatile memory corresponds to an amount of volatile memory that can be written from the write buffer to the non-volatile memory in a power loss based on degraded capacitor performance. (para [0042]: based on “back-up power source” degradation and remaining capability, buffer size is reduced adjusted. See para [0021]-para [0023], para [0006], para [0042], para [0044]: reduced buffer size. para [0042]: back-up power source).
Merry is silent with respect to using “capacitor” in data back-up scheme during power loss and silent with respect to using the back-up capacitor degradation performance in the method and apparatus.
Zheng teaches wherein second amount corresponds to an estimated degraded performance of capacitors (para [0038]: “capacitor” used as reserve power source) that allow for completion of writing of the data to be written to the non-volatile memory from the write buffer during a power loss (para [0038], para [0127]-para [0131]).
Merry and Zheng are in the same field of endeavor since Zheng teaches a system (Fig. 2: 200 computing system with “adaptive back-up mechanism”. See Fig. 7 adaptive back-up operation and Fig. 6 illustrated components and functionality) comprising: a plurality of memory devices (Fig. 2: 206, 204); and a processing device (Fig. 2: 208 local memory controller), operatively coupled with the plurality of memory devices (See Fig. 2), to: allot a first amount of volatile memory to a write buffer (para [0130]: “write buffer entry size 782” when normal calculated volatile memory utility is used, see Fig. 7:702. See also para [0104], para [0093]-para [0094]), wherein the write buffer stores batches of data to be written to non-volatile memory (“write buffer entries” or “write entry”, see e.g. para [0102] and para [0103]. Data back-up during “…normal operation or without detecting the power failure…”); detect a trigger (Fig. 7: 710 “detect change”) to update the allotment of volatile memory to the write buffer (Fig. 7: 710 in context of para [0106]: “…detect change module … monitors or detects conditions that can affect backing up the data from the volatile memory…to the nonvolatile memory. para [0080]: “…adaptive back-up system … provides modification to the transfer mechanism for the volatile memory …for backing up data when the power failure … detected…”); and in response to the trigger (e.g. “power failure” Fig. 7: 710, 706, 708, 710, 712), reduce the volatile memory allotted (para [0130]: “write buffer entry size 782”) to the write buffer to a second amount (Equation 1 and equation 2 in context of para [0128]-para [0131]: “write entry size” is reduced to maximize “write entries commit” within calculated available backup time. See also “…The calculate buffer size module … determines the amount of data in the volatile memory… to be backed up….”). Thus, Merry and Zheng are in analogous field of art.
Employing Zheng’s “capacitor” with associated modules for buffer size calculation and dynamic reliability tracking enables precise calculation of optimal buffer size with maximized data throughput rate i.e. improves data transmission speed.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Zheng into the teachings of Merry such that capacitors as back-up power source can be employed in the apparatus in order to increase operational speed.
Regarding claim 16, Merry and Zheng teach the system of claim 15. Merry teaches wherein the processing device is further to:
detect a second trigger to update the write buffer configuration (see in context of para [0023], para [0039], para [0044]: multiple monitoring parameters are discussed); and
in response to the second trigger, reduce the size of the write buffer from the second amount to a third amount (see para [0021], Fig. 1: various buffer size and combinations).
Merry is silent with respect to remaining provisions of this claim as it pertains to serially utilizing two triggers to adjust buffer size.
Zheng teaches wherein the processing device is further to: detect a second trigger to update the size of the write buffer (Zheng Fig. 7 loop algorithm teaches multiple triggers can be used sequentially); and
in response to detecting the second trigger, reduce the size of the write buffer from the second amount to a third amount (see Fig. 7 loop and equation 1, equation 2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Zheng into the teachings of Merry such that a robust method for controlling the write buffer size can be employed in order to control reliability of the device and improve operational speed.
Regarding claim 17, Merry and Zheng teach the system of claim 16. Merry teaches wherein the second trigger includes receiving an input (para [0039]: monitored parameters) to update the size of the write buffer (see details in para [0039]. See Abstract “…adjusting the size of the write buffer based on monitored operating conditions, such as the temperature, the stability/consistency of a power signal received from the host system, and/or the elapsed time since the storage subsystem was last powered up….”. Monitored params are used to reduce or adjust size of write buffer. See also para [0022], para [0023], para [0044]).
Regarding claim 18, Merry and Zheng teach the system of claim as described (See in context of para [0039], (a-i) in combination encompasses the limitation. For example, “…length of time since the last power signal anomaly was detected…” satisfies this limitation. See also method claim 4).
Regarding claim 20, Merry and Zheng teach the system of claim 15. Merry teaches wherein the processing device is further to:
receive a write command from a host system (para [0031], para [0033]-para [0034]),
the write command including data (Fig. 2, para [0020], para [0033]-para [0034]);
write the data to the write buffer (Fig. 1, Fig. 2 and para [0006], para [0019], para [0020]); and
write data from the write buffer to the non-volatile memory (Fig. 1, Fig. 2 and para [0006], para [0019], para [0020]).
New added claims are rejected under 112b and art rejection is not produced.
Double Patenting
11. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
12. Claims 1, 8, and 15 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. US 12073873 B2. Although the claims at issue are not identical, they are not patentably distinct from each other.
(Applicant has not replied sufficiently to the NSDP double patenting rejection and previous rejections are being maintained)
Analysis is not shown. Relied upon from non-final rejection and combination of claims.
Response to Arguments
Applicant has not replied sufficiently to the NSDP double patenting rejection and previous rejections are being maintained.
Applicant’s arguments with respect to claim(s) have been considered but are partly moot because new ground of rejection added based on existing references. See new formulated rejection.
Applicant's arguments (based on new amendments dated 05/08/2026) filed has been fully considered but they are not persuasive because applicant has not considered prior art in its entirety. Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim. Other passages and figures may apply as well. Applicant must fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner while including in such consideration the cited prior art references in their entirety as potentially teaching all or part of the claimed invention. Per MPEP 2141.02 VI prior art must be considered in its entirety.
In addition, rejection of new amended limitations does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Prior Art Not Relied Upon
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure:
Bianco (US 20210191646 A1): Fig. 1-Fig. 5 disclosure applicable
Boyd (US 2021/0089225 A1): Fig. 1-Fig. 9 disclosure applicable.
SHIN (US 2022/0269434 A1): Fig. 1-Fig. 10 disclosure applicable.
It is suggested that applicant consider all prior arts made of record.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUSHFIQUE SIDDIQUE whose telephone number is (571)270-0424. The examiner can normally be reached 7:00 am-4:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander George Sofocleous can be reached on (571) 272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825
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