DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/7/2024, 10/7/2024, 10/29/2024, 11/01/2024, 1/29/2025, 5/14/2025 and 7/17/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 5-7, 9 and 12 objected to because of the following informalities: the claim appears to have a typographical error, "The device of claim 1". For the purpose of examination, the examiner will interpret the above limitation as " The device of claim [[1]]2".
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-3, 5-6, 9-19 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Mizukami et al. US 2013/0313573 in view of Lemaitre et al. (“Low-temperature, site selective graphitization of SiC via ion implantation and pulsed laser annealing” , Appl. Phys. Lett. 100, 193105 (2012)), Mieczkowski et al. US 2016/0093748 and Masato JP2015153789.
Re claim 2, Mizukami teaches a device (10, fig1, [33]), comprising:
a solid body (14 n-, fig1, [34]) having a first conductivity type (n-type, [34]);
an implanted region (18 adjacent to 20, fig1, [40]) of a second conductivity type (p-type, [40]) different from the first conductivity type (n-type, [34]) extending into a first surface of the solid body (top surface of 14, fig1), the implanted region including a second surface (top surface of 18 in contact with 24, fig1) co-planar with the first surface of the solid body (top surface of 14, fig1);
an anode (24, fig1, [41]) on the first surface of the solid body, the anode having a first face (bottom surface of 24, fig1, [41]) opposite the first surface of the solid body (top surface of 14, fig1); and
Mizukami teaches region 18 is desirably set to make characteristics of a contact with the first electrode an ohmic contact or close to an ohmic contact ([38]).
Mizukami does not explicitly show an ohmic contact region, including a first carbon-rich layer and extending into the implanted region;
Lemaitre teaches selectively graphitize SiC region via silicon sublimation to form few-layer graphene over large areas with nanoscale precision (page 193105-1 right col).
Masato teaches P-type SiC region (8, fig11, [20]) makes ohmic contact with surface electrode (4, fig11, [20]) via few-layer graphene (6, fig11, [20]) formed by sublimation of Si from surface of SiC .
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Mizukame, Lemaitre and Masato to create ohmic contact using graphene formed by pulse laser annealing. The motivation to do so is to create ohmic contact to reduce on-resistance of PN diode part and improve surge current resistance (Mizukami, [50]) with nanoscale precision (page 193105-1 right col).
Mizukami does not explicitly show a passivation layer on the first face, the passivation layer including an opening that exposes a central region of the anode, the passivation layer overlapping the ohmic contact region.
Mieczkowski teaches a passivation layer (50, fig8, [54]) on the first face (top surface of 22, fig8, [37]), the passivation layer including an opening (space between 50, fig8) that exposes a central region of the anode (26, fig8, [28]), the passivation layer overlapping the ohmic contact region (30 under 50, fig8).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Mizukame modified above and Mieczkowski to add a passivation layer over the layer 22 and anode 24 of Mizukami fig1 as in Mieczkowski fig8. The motivation to do so is to protect the top surface of the Schottky diode from deteriorating effect (Mieczkowski, [45, 54).
Re claim 3, Mizukami modified above teaches the device of claim 2, wherein the device is a merged PiN-Schottky device (Mizukami, 10, fig1, [33]).
Re claim 5, Mizukami modified above teaches the device of claim [[1]]2, further comprising a cathode (Mizukami, 26, fig1, [41]) on a second surface of the solid body (Mizukami, bottom surface of 14, fig1) opposite the first surface (Mizukami, top surface of 14, fig1).
Re claim 6, Mizukami modified above teaches the device of claim [[1]]2, further comprising a second carbon-rich layer (Masato, top part of few-layer graphene 6, fig11, [20]) on the first carbon-rich layer (Masato, bottom part of few-layer graphene 6, fig11, [20]), the first and second carbon-rich layers including graphite.
Re claim 9, Mizukami modified above teaches the device of claim [[1]]2, wherein the ohmic contact region (Mizukami, 18 adjacent to 20 with graphene formed by laser annealing, fig1, [40]) and the implanted region (Mizukami, 18 adjacent to 20, fig1, [40]) have a same shape and a same depth of extension into the first surface of the solid body.
Re claim 10, Mizukami modified above teaches the device of claim 5, further comprising a substrate (Mizukami, 12 n+, fig1, [34]) between the solid body (Mizukami, 14 n- as SiC, fig1, [34]) and the cathode (Mizukami, 26, fig1, [41]), the substrate having the first conductivity type (Mizukami, 12 n+, fig1, [34]) and a first doping concentration greater than a second doping concentration of the solid body (Mizukami, 14 n- as SiC, fig1, [34]).
Re claim 11, Mizukami modified above teaches the device of claim 5, wherein the solid body has a first thickness from the first surface of the solid body to the second surface of the solid body in the range of 5 µm and 15 µm (Mizukami, 14, fig1, [55]).
Re claim 12, Mizukami modified above teaches the device of claim [[1]]2, further comprising a protection ring (Mizukami, 20 p+, fig1, [40]) of the second conductivity type (Mizukami, p-type, [40]) extending into the first surface of the solid body, the protection ring being coplanar with the first surface of the solid body (Mizukami, top surface of 20 coplanar with top surface of 14, fig1).
Re claim 13, Mizukami teaches a device (10, fig1, [33]), comprising:
an active layer (14 n-, fig1, [34]) of a first conductivity type (n-type, [34]), the active layer including a first surface opposite a second surface (top surface of 14, fig1) along a first direction (direction along d, fig1);
a Schottky diode (PIN diode, fig1, [33]) in the active layer;
a first implanted region (18 p+ adjacent to 20, fig1, [40]) extending into the active layer along the first direction, the first implanted region having a second conductivity type (p-type, [40]) that is different from the first conductivity type,
an anode layer (24, fig1, [41]) on the first surface of the active layer, the anode layer having a first face (bottom surface of 24, fig1, [41]) opposite the first surface of the active layer (top surface of 14, fig1) along the first direction;
Mizukami teaches region 18 is desirably set to make characteristics of a contact with the first electrode an ohmic contact or close to an ohmic contact ([38]).
Mizukami does not explicitly show the first implanted region including a first ohmic contact.
Lemaitre teaches selectively graphitize SiC region via silicon sublimation to form few-layer graphene over large areas with nanoscale precision (page 193105-1 right col).
Masato teaches P-type SiC region (8, fig11, [20]) makes ohmic contact with surface electrode (4, fig11, [20]) via few-layer graphene (6, fig11, [20]) formed by sublimation of Si from surface of SiC .
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Mizukame, Lemaitre and Masato to create ohmic contact using graphene formed by pulse laser annealing. The motivation to do so is to create ohmic contact to reduce on-resistance of PN diode part and improve surge current resistance (Mizukami, [50]) with nanoscale precision (page 193105-1 right col).
Mizukami does not explicitly show a passivation layer on the first face, the passivation layer aligned with the first ohmic contact along the first direction and including a gap that is aligned with a central region of the active layer.
Mieczkowski teaches a passivation layer (50, fig8, [54]) on the first face (top surface of 22, fig8, [37]), the passivation layer aligned with the first ohmic contact along the first direction (side wall of 50 aligned with 30 adjacent to 38, fig8) and including a gap (space between 50, fig8) that is aligned with a central region of the active layer (center part of 22 under 26, fig8, [37]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Mizukame modified above and Mieczkowski to add a passivation layer over the layer 22 and anode 24 of Mizukami fig1 as in Mieczkowski fig8. The motivation to do so is to protect the top surface of the Schottky diode from deteriorating effect (Mieczkowski, [45, 54).
Re claim 14, Mizukami modified above teaches the device of claim 13, wherein the first ohmic contact includes carbon (Masato, few-layer graphene 6, fig11, [20]).
Re claim 15, Mizukami modified above teaches the device of claim 13, further comprising a second implanted region (Mizukami, 20 p+ or inner ring 18 p+, fig1, [40]) of the second conductivity type (Mizukami, p-type, [40]) extending into the active layer along the first direction (Mizukami, along d, fig1), spaced from the first implanted region (Mizukami, 18 outer ring, fig1 and 2, [40]) along a second direction (Mizukami, direction along A-A, fig 2) transverse to the first direction by the central region of the active layer (Mizukami, fig1 and 2),
Re claim 16, Mizukami modified above teaches the device of claim 15, wherein the second implanted region (Mizukami, 20 p+ or inner ring 18 p+, fig1, [40]) has the second conductivity type (Mizukami, p-type, [40]) and includes: a third surface (Mizukami, top surface of 20 p+ or inner ring 18 p+, fig1, [40]); and a second ohmic contact including carbon (Mizukami, few-layer graphene on top of 20 p+ or inner ring 18 p+, fig1, [40]), the third surface being coplanar with the first surface of the active layer (Mizukami, fig1).
Re claim 17, Mizukami modified above teaches the device of claim 16, wherein the passivation layer entirely covers the first and second ohmic contacts along the first direction (Mieczkowski, 50 covers top surface of 30 and 38, fig8).
Re claim 18, Mizukami teaches a device (10, fig1, [33]), comprising:
a substrate (12, fig1, [34]);
a drift layer of a first conductivity type (14 n-, fig1, [34]) on the substrate, the drift layer including a face (top surface of 14, fig1);
a first embedded region (18 adjacent to 20, fig1 and 2, [40]) extending into the face of the drift layer along a first direction (Mizukami, along d, fig1),
the first embedded region having a second conductivity type (p-type, [40]) different from the first conductivity type (n-type, [34])
a second embedded region (18 in center region, fig1 and 2, [40]) in the drift layer along the first direction (Mizukami, along d, fig1), spaced from the first embedded region (18 adjacent to 20, fig1 and 2, [40]) along a second direction (Mizukami, direction along A-A, fig 2) transverse to the first direction (Mizukami, along d, fig1),
a first conductive layer (24, fig1, [41]) on the face of the drift layer (top surface of 14, fig1), the first conductive layer having a first face (bottom surface of 24, fig1, [41]) opposite the first side of the drift layer (top surface of 14, fig1);
Mizukami teaches region 18 is desirably set to make characteristics of a contact with the first electrode an ohmic contact or close to an ohmic contact ([38]).
Mizukami does not explicitly show the first embedded region including a first ohmic contact between the face of the drift layer and the substrate along the first direction; the second embedded region including a second ohmic contact between the face of the drift layer and the substrate;
Lemaitre teaches selectively graphitize SiC region via silicon sublimation to form few-layer graphene over large areas with nanoscale precision (page 193105-1 right col).
Masato teaches P-type SiC region (8, fig11, [20]) makes ohmic contact with surface electrode (4, fig11, [20]) via few-layer graphene (6, fig11, [20]) formed by sublimation of Si from surface of SiC .
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Mizukame, Lemaitre and Masato to create ohmic contact using graphene formed by pulse laser annealing. The motivation to do so is to create ohmic contact to reduce on-resistance of PN diode part and improve surge current resistance (Mizukami, [50]) with nanoscale precision (page 193105-1 right col).
Mizukami does not explicitly show a passivation layer on the first face, the passivation layer including an opening that exposes a central region of the first conductive layer, the opening extending from the first ohmic contact to the second ohmic contact.
Mieczkowski teaches a passivation layer (50, fig8, [54]) on the first face (top surface of 22, fig8, [37]), the passivation layer including an opening (space between 50, fig8) that exposes a central region of the first conductive layer (26, fig8, [28]), the openingextending from the first contact to the second contact (space between 50 extending from left to right in region 14, fig8).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Mizukame modified above and Mieczkowski to add a passivation layer over the layer 22 and anode 24 of Mizukami fig1 as in Mieczkowski fig8. The motivation to do so is to protect the top surface of the Schottky diode from deteriorating effect (Mieczkowski, [45, 54).
Re claim 19, Mizukami modified above teaches the device of claim 18, further comprising a second conductive layer (Mizukami, 26, fig1, [41]) on a first surface of the substrate (Mizukami, bottom surface of 12, fig1, [34]) opposite the drift layer (Mizukami, 14 n-, fig1, [34]).
Re claim 21, Mizukami modified above teaches the device of claim 18, wherein the first ohmic contact includes a plurality of carbon-rich layers (Masato, few-layer graphene 6, fig11, [20]).
Claim(s) 20 is rejected under 35 U.S.C. 103 as being unpatentable over Mizukami et al. US 2013/0313573 in view of Lemaitre et al. (“Low-temperature, site selective graphitization of SiC via ion implantation and pulsed laser annealing” , Appl. Phys. Lett. 100, 193105 (2012)), Mieczkowski et al. US 2016/0093748, Masato JP2015153789 and Mauder et al. US 2010/0117725.
Re claim 20, Mizukami does not explicitly show the device of claim 19, wherein the substrate has a thickness in the range of 50µm and 350 µm along the first direction between the first surface of the substrate and the drift layer.
Mauder teaches region 12 with thickness of greater than 50 µm and less than 500 µm (12, fig1, [28])
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Mizukame modified above and Mauder to form a resistance layer with sufficient thickness. The motivation to do so is to minimize losses of diode and buffer heat loss at high pulse (Mauder, [25, 30,43]).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 2-21 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-20 of U.S. Patent No. 11670685. Although the claims at issue are not identical, they are not patentably distinct from each other because the subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter.
Re claim 2, U.S. Patent No. 11670685 teaches a device (claim 1), comprising:
a solid body (claim 1) having a first conductivity type (claim 1);
an implanted region (claim 1) of a second conductivity type (claim 1) different from the first conductivity type extending into a first surface of the solid body (claim 1), the implanted region including a second surface co-planar with the first surface of the solid body (claim 1);
an ohmic contact region (claim 1), including a first carbon-rich layer and extending into the implanted region (claim 1);
an anode (claim 1) on the first surface of the solid body, the anode having a first face opposite the first surface of the solid body (claim 1); and
a passivation layer (claim 1) on the first face, the passivation layer including an opening that exposes a central region of the anode (claim 1), the passivation layer overlapping the ohmic contact region (claim 1).
Re claim 13, U.S. Patent No. 11670685 a device (claim 10), comprising:
an active layer (claim 10) of a first conductivity type (claim 10), the active layer including a first surface opposite a second surface along a first direction (claim 10);
a Schottky diode in the active layer (claim 10);
a first implanted region (claim 10) extending into the active layer along the first direction, the first implanted region having a second conductivity type that is different from the first conductivity type (claim 10), the first implanted region including a first ohmic contact (claim 10);
an anode layer (claim 10) on the first surface of the active layer, the anode layer having a first face opposite the first surface of the active layer along the first direction (claim 10); and
a passivation layer on the first face (claim 10), the passivation layer aligned with the first ohmic contact along the first direction and including a gap that is aligned with a central region of the active layer (claim 10).
Re claim 18, U.S. Patent No. 11670685 a device (claim 6), comprising:
a substrate (claim 6);
a drift layer of a first conductivity type on the substrate (claim 6), the drift layer including a face (claim 6);
a first embedded region (claim 6) extending into the face of the drift layer along a first direction, the first embedded region having a second conductivity type (claim 6) different from the first conductivity type and including a first ohmic contact (claim 6) between the face of the drift layer and the substrate along the first direction;
a second embedded region (claim 6) in the drift layer along the first direction, spaced from the first embedded region along a second direction transverse to the first direction (claim 6), the second embedded region including a second ohmic contact between the face of the drift layer and the substrate (claim 6);
a first conductive layer (claim 6) on the face of the drift layer, the first conductive layer having a first face opposite the first side of the drift layer (claim 6); and
a passivation layer (claim 6) on the first face, the passivation layer including an opening that exposes a central region of the first conductive layer (claim 6), the opening extending from the first ohmic contact to the second ohmic contact (claim 6).
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Allowable Subject Matter
Claim 4, 7 and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and with a timely filed terminal disclaimer to overcome the current nonstatutory double patenting rejection.
Specifically, the limitations are material to the inventive concept of the application in hand to form a SiC PIN diode with low on resistance, high thermal conductivity and operating frequency.
Conclusion
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/XIAOMING LIU/Examiner, Art Unit 2812
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