Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. (see MPEP § 606.01).
This may result in slightly longer titles, but the loss in brevity of title will be more than offset by the gain in its informative value in indexing, classifying, searching, etc.
The following title is suggested:
“
Specification
Number of figures submitted does not match the number of figures listed under Brief Description of Drawings in the specification. All of the figures with alphabets should be listed separately. For example, ‘Figs. 1A-1C’ should be ‘Figs. 1A, 1B and 1C’.
In particular, ‘Figures. 3A-3F’ in the page 5 is objected.
See MPEP 500 - Receipt and Handling of Mail and Papers, MPEP 507 - Drawing Review in the Office of Patent Application Processing (OPAP). This labeling convention ensures clarity and consistency in referencing figures throughout the patent application and publication. Improper labeling may result in an objection from OPAP and require correction.
Appropriate correction is required.
Claim Objections
Claims 12 and 20 are objected to because of the following informalities:
Each claim begins with a capital letter and ends with a period. See MPEP § 608.01(m).
Appropriate correction is required.
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 13–18 are rejected under 35 U.S.C. 112(a) for failing to comply with the written description requirement.
Claim 13 recites, inter alia, “a field plate element on the insulation layer, the field plate element being coplanar with the first surface of the first portion.”
The Specification provides written-description support for a field-plate element on the insulation layer. In particular, the Specification describes field-plate element 18′ as extending as a continuation of gate metallization 18b toward drain terminal 22 and on insulation layer 17. Thus, the rejection is not based on the recitation of the field-plate element itself or its location on the insulation layer.
However, the Specification and drawings do not provide adequate written-description support for the further limitation that “the field plate element [is] coplanar with the first surface of the first portion.” Although the Specification describes the location and extension of field-plate element 18′ relative to gate metallization 18b, insulation layer 17, and drain terminal 22, it does not describe the field-plate element as being coplanar with the first surface of the first portion, nor does it otherwise expressly identify such a coplanar relationship.
The drawings likewise do not clearly and unambiguously disclose the claimed coplanar relationship. While the drawings illustrate the relative positioning of the gate metallization, field-plate element, and insulation layer, they do not establish that the particular field-plate element and the recited first surface of the first portion have the specific coplanar relationship now required by claim 13.
Moreover, although the disclosure elsewhere expressly uses coplanar relationships, those relationships concern different structural features. For example, the parent disclosure recites a side surface of the gate metallization being coplanar with a surface of the gate dielectric layer in the trench, rather than a field-plate element being coplanar with a first surface of a first portion of the gate metallization. Thus, the disclosed coplanarity does not provide written-description support for the different coplanar relationship presently recited in claim 13.
Accordingly, the disclosure does not reasonably convey to one of ordinary skill in the art that the inventor had possession, as of the filing date, of the claimed configuration in which the field plate element is coplanar with the first surface of the first portion. Therefore, claim 13 fails to comply with the written description requirement of 35 U.S.C. 112(a).
Claims 14–18 depend from claim 13 and incorporate the unsupported limitation. Accordingly, claims 14–18 are rejected under 35 U.S.C. 112(a) for the same reason.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of the first paragraph of 35 U.S.C. 112(b):
CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 2 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
First issue — unclear scope and boundaries of the “first opening”:
Claim 2 recites “a first opening extending from the first surface of the insulation layer to the second surface of the insulation layer.” The claim subsequently recites “a gate metallization in the first opening on the heterostructure and on the insulation layer,” and further requires “the passivation layer being in the first opening between the first conductive terminal and the gate metallization along the second direction.”
It is unclear what structural region constitutes the claimed “first opening” and, particularly, what the boundaries and extent of the first opening are. The initial recitation defines the first opening with respect to the first and second surfaces of the insulation layer along the first direction, thereby indicating an opening extending through the thickness of the insulation layer. However, the claim subsequently requires the passivation layer to be “in the first opening” and “between the first conductive terminal and the gate metallization along the second direction,” wherein the second direction is transverse to the first direction.
Thus, it is unclear whether the claimed “first opening” is (1) an opening extending through the insulation layer in which the gate metallization is disposed, (2) a laterally extending region between the first conductive terminal and the gate metallization in which the passivation layer is disposed, or (3) a single continuous opening encompassing both regions.
This ambiguity is material because the location and extent of the “first opening” determine the required spatial relationships among the insulation layer, first conductive terminal, gate metallization, heterostructure, dielectric layer, and passivation layer. Accordingly, the Examiner would be required to speculate as to the boundaries of the “first opening” in determining the scope of claim 2.
Second issue — unclear scope of “the dielectric layer entirely covering the first surface of the insulation layer”:
Claim 2 further recites “a dielectric layer between the gate metallization and the heterostructure and between the gate metallization and the insulation layer, the dielectric layer entirely covering the first surface of the insulation layer.”
The scope of the limitation “the dielectric layer entirely covering the first surface of the insulation layer” is unclear when considered together with the previously recited “first opening extending from the first surface of the insulation layer to the second surface of the insulation layer” and the gate metallization disposed “in the first opening.”
Specifically, it is unclear whether “entirely covering the first surface of the insulation layer” requires the dielectric layer to extend continuously across the entire first surface, including across or over the location of the first opening, or whether the dielectric layer is required to cover only the portions of the first surface at which the insulation layer remains after formation of the first opening.
If the dielectric layer is required to extend continuously across the location of the first opening, it is unclear how such an arrangement is consistent with the gate metallization being “in the first opening.” Conversely, if the first opening is excluded from the requirement that the dielectric layer “entirely” cover the first surface, the claim does not identify such an exclusion or otherwise define which portions of the first surface must be covered.
The Specification does not resolve this ambiguity with reasonable certainty. The Specification describes formation of gate dielectric layer 18a followed by formation of gate metallization 18b on the gate dielectric layer, but further states that portions of gate dielectric layer 18a not protected by gate metallization 18b may either be removed or retained. Thus, different extents of the gate dielectric layer are contemplated by the disclosure, further rendering it unclear what structural extent is required by the claim language “entirely covering the first surface of the insulation layer.”
Accordingly, for at least the two reasons set forth above, the metes and bounds of claim 2 cannot be determined with reasonable certainty, and claim 2 is indefinite under 35 U.S.C. 112(b).
Claim 6 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 6 depends from claim 2 and therefore incorporates all of the limitations of claim 2.
First issue — unclear relationship between the first portion of the gate metallization, the dielectric layer, and the heterostructure:
Claim 2 requires “a dielectric layer between the gate metallization and the heterostructure.” Claim 6, however, further requires that “the gate metallization includes a first portion in the first opening directly on the heterostructure along the first direction.”
These limitations appear inconsistent. Specifically, it is unclear how the first portion of the gate metallization can be “directly on the heterostructure,” as required by claim 6, while a dielectric layer is simultaneously disposed “between the gate metallization and the heterostructure,” as required by parent claim 2.
If the dielectric layer is positioned between the first portion of the gate metallization and the heterostructure, the first portion does not appear to be directly on the heterostructure. Conversely, if the first portion of the gate metallization is directly on the heterostructure with no intervening material, it is unclear how the dielectric layer required by claim 2 can be positioned between the gate metallization and the heterostructure at that location.
The Specification does not resolve this inconsistency. Rather, the Specification describes gate dielectric layer 18a as electrically insulating gate metallization 18b from barrier layer 16 of the heterostructure and further describes gate metallization 18b as being formed on gate dielectric layer 18a.
Accordingly, it is unclear whether the claimed first portion of the gate metallization is required to directly contact the heterostructure or whether the dielectric layer is required to intervene between the first portion of the gate metallization and the heterostructure.
Second issue — unclear relationship between the second portion of the gate metallization, the dielectric layer, and the insulation layer:
Claim 2 further requires the dielectric layer to be “between the gate metallization and the insulation layer.” Claim 6, however, requires that the gate metallization include “a second portion directly on the insulation layer along the first direction.”
These limitations likewise appear inconsistent. Specifically, it is unclear how the second portion of the gate metallization can be “directly on the insulation layer,” as required by claim 6, while a dielectric layer is simultaneously disposed “between the gate metallization and the insulation layer,” as required by parent claim 2.
If the dielectric layer is positioned between the second portion of the gate metallization and the insulation layer, the second portion does not appear to be directly on the insulation layer. Conversely, if the second portion of the gate metallization directly contacts the insulation layer with no intervening material, it is unclear how the dielectric layer required by claim 2 can be disposed between the gate metallization and the insulation layer at that location.
The Specification does not resolve this inconsistency. The disclosed gate metallization 18b is formed on gate dielectric layer 18a, rather than being described as directly contacting the underlying insulation layer.
Accordingly, it is unclear whether the claimed second portion of the gate metallization is required to directly contact the insulation layer or whether the dielectric layer is required to intervene between the second portion of the gate metallization and the insulation layer.
Therefore, for at least the two reasons set forth above, the structural relationships among the gate metallization, dielectric layer, heterostructure, and insulation layer cannot be determined with reasonable certainty. The Examiner would be required to speculate as to which of the apparently inconsistent limitations controls. Accordingly, the metes and bounds of claim 6 cannot be determined with reasonable certainty, rendering claim 6 indefinite under 35 U.S.C. 112(b).
Claim 8 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 8 depends from claim 7, which depends from claim 2, and therefore incorporates all of the limitations of claims 2 and 7.
Claim 8 recites that “the insulation layer is entirely separated from the passivation layer by the dielectric layer.”
Issue — unclear scope of “entirely separated from the passivation layer by the dielectric layer”:
It is unclear what structural relationship is required by the recitation that the insulation layer is “entirely separated” from the passivation layer by the dielectric layer.
Claim 2 requires the dielectric layer to be between the gate metallization and the insulation layer and to “entirely covering the first surface of the insulation layer.” Claim 7 further requires the passivation layer to be directly in contact with the dielectric layer. Claim 8 then requires the insulation layer to be “entirely separated” from the passivation layer by the dielectric layer.
It is unclear whether “entirely separated” requires the dielectric layer to physically intervene between the insulation layer and the passivation layer at every location at which the insulation layer and passivation layer would otherwise face or contact one another, such that no portion of the insulation layer may directly contact any portion of the passivation layer, or whether “entirely separated” refers only to separation along the first surface of the insulation layer recited in claim 2.
The distinction is material because the insulation layer has surfaces and boundaries other than the recited first surface, particularly adjacent to the first opening. Claim 8 does not specify whether the dielectric layer must also separate the passivation layer from such other surfaces or boundaries of the insulation layer in order for the insulation layer to be “entirely separated” from the passivation layer.
The Specification does not clearly define the term “entirely separated” or otherwise establish the extent of dielectric material required to satisfy this limitation. Moreover, the Specification provides that portions of gate dielectric layer 18a that are not protected by gate metallization 18b may either be removed or retained, thereby contemplating different extents of the dielectric layer.
Accordingly, it cannot be determined with reasonable certainty whether claim 8 requires complete physical isolation of the insulation layer from the passivation layer at all locations, or only separation at a particular surface or region. The metes and bounds of claim 8 are therefore unclear, rendering claim 8 indefinite under 35 U.S.C. 112(b).
Claim 10 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 10 depends from claim 2 and recites “wherein the gate metallization includes a first surface facing the first conductive terminal along the second direction, the first surface of the gate metallization being coplanar with a first surface of the dielectric layer.”
Issue — unclear identity of “a first surface of the dielectric layer”:
Claim 10 identifies the first surface of the gate metallization by requiring that the surface face the first conductive terminal along the second direction. However, the claim does not correspondingly identify which physical surface or portion of the dielectric layer constitutes the recited “first surface of the dielectric layer.”
This ambiguity is significant in view of parent claim 2, which requires the dielectric layer to be disposed between the gate metallization and the heterostructure, between the gate metallization and the insulation layer, and to entirely cover the first surface of the insulation layer. Thus, the claimed dielectric layer extends in different structural relationships relative to the gate metallization, heterostructure, and insulation layer.
Claim 10 does not specify which surface or portion of this dielectric layer is required to be coplanar with the first surface of the gate metallization. Accordingly, it is unclear what particular structural relationship must exist between the dielectric layer and the gate metallization to satisfy the recited coplanarity.
The ambiguity is material because determination of whether the claimed surfaces are “coplanar” necessarily depends upon identification of the particular surface of the dielectric layer being compared with the first surface of the gate metallization. Without such identification, the Examiner would be required to speculate as to which surface or portion of the dielectric layer is intended to satisfy the limitation.
Accordingly, the metes and bounds of claim 10 cannot be determined with reasonable certainty, rendering claim 10 indefinite under 35 U.S.C. 112(b).
Claim 12 is rejected under 35 U.S.C. 112(b) as indefinite because the claim is incomplete and fails to particularly point out and distinctly claim the subject matter regarded as the invention.
Claim 12 does not set forth a complete claim limitation or otherwise conclude in a manner that defines the scope of the claimed subject matter. The claim is facially incomplete and does not even terminate as a complete claim.
Because essential claim language is missing, the metes and bounds of claim 12 cannot be determined with reasonable certainty. The Examiner cannot ascertain what additional structural or functional limitation Applicant intended to recite, nor can the Examiner determine whether any omitted language was intended to further limit, qualify, or otherwise modify the subject matter inherited from the parent claim.
Accordingly, any attempt to construe claim 12 would require the Examiner to speculate as to Applicant’s intended claim language. Such speculation is improper and would not provide a reliable basis for determining the scope of the claim or for comparing the claimed subject matter with the prior art.
Therefore, claim 12 is not susceptible to a meaningful examination on the merits with respect to the prior art in its present form. No prior-art rejection of claim 12 is made because the scope of the claim cannot be determined with sufficient certainty to permit a proper prior-art analysis. Applicant is required to amend claim 12 to provide a complete and definite claim before substantive examination of claim 12 can be completed.
Claim 13 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Issue — unclear scope and boundaries of the “first opening”:
Claim 13 recites “a first opening extending from the first surface of the insulation layer to the heterostructure.” Claim 13 subsequently recites a gate metallization “in the first opening” and further requires “a passivation layer in the first opening between the first conductive terminal and the first portion of the gate metallization along the second direction.”
It is unclear what structural region constitutes the claimed “first opening” and, particularly, what the boundaries and extent of the first opening are.
The initial recitation defines the first opening as extending from the first surface of the insulation layer to the heterostructure, thereby defining the opening with respect to the thickness of the insulation layer along the first direction. However, the claim subsequently requires the passivation layer to be “in the first opening” and positioned “between the first conductive terminal and the first portion of the gate metallization along the second direction,” wherein the second direction is transverse to the first direction.
Accordingly, it is unclear whether the “first opening” is (1) an opening extending through the insulation layer to the heterostructure in which the gate metallization is disposed, (2) a laterally extending region between the first conductive terminal and the first portion of the gate metallization in which the passivation layer is disposed, or (3) a single continuous opening encompassing both regions.
This ambiguity is material because the extent of the “first opening” determines the required spatial relationships among the insulation layer, first conductive terminal, gate metallization, dielectric layer, heterostructure, and passivation layer. The Examiner would therefore be required to speculate as to the boundaries of the claimed first opening when determining whether a particular structure falls within the scope of claim 13.
Accordingly, the metes and bounds of claim 13 cannot be determined with reasonable certainty, rendering claim 13 indefinite under 35 U.S.C. 112(b).
Claim 14 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 14 depends from claim 13 and recites “wherein the passivation layer is directly on the first and second conductive terminals, the gate terminal, and the heterostructure.”
Issue — lack of antecedent basis and unclear identity of “the gate terminal”:
The recitation of “the gate terminal” in claim 14 lacks antecedent basis. Parent claim 13 does not previously recite or define a “gate terminal.” Rather, claim 13 recites a “gate metallization” including a first portion in the first opening and a field plate element on the insulation layer.
Accordingly, it is unclear what structure is intended by “the gate terminal” in claim 14. In particular, it is unclear whether “the gate terminal” refers to the “gate metallization” recited in claim 13, to only a portion of the gate metallization, to a combination of the gate metallization and dielectric layer, or to some other gate structure.
This ambiguity is material because claim 14 requires the passivation layer to be “directly on” the unidentified “gate terminal.” Without a clear identification of the structure constituting the “gate terminal,” it cannot be determined with reasonable certainty which structure must directly contact the passivation layer in order to satisfy claim 14.
Although the Specification uses the term “gate terminal” in describing certain embodiments, the use of that terminology in the Specification does not establish which of the structures specifically recited in claim 13 is intended to constitute “the gate terminal” for purposes of claim 14.
Accordingly, the lack of antecedent basis for “the gate terminal” renders the required structural relationship between the passivation layer and the claimed gate structure unclear. Therefore, the metes and bounds of claim 14 cannot be determined with reasonable certainty, rendering claim 14 indefinite under 35 U.S.C. 112(b).
Claim 16 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 16 depends from claim 13 and recites “wherein the dielectric layer is coplanar with an interface between the heterostructure and the insulation layer.”
Issue — unclear meaning of the dielectric layer being “coplanar with” the interface:
It is unclear what structural relationship is required by the recitation that “the dielectric layer is coplanar with an interface between the heterostructure and the insulation layer.”
The claimed dielectric layer is a layer having a physical thickness and, therefore, necessarily includes multiple surfaces or boundaries. In contrast, the recited “interface between the heterostructure and the insulation layer” identifies a boundary between two structures. Claim 16 does not identify any particular surface, boundary, or portion of the dielectric layer that is required to be coplanar with the recited interface.
Accordingly, it is unclear whether claim 16 requires (1) a surface of the dielectric layer to be coplanar with the interface between the heterostructure and the insulation layer, (2) a portion of the dielectric layer to extend in the same plane as that interface, or (3) some other positional relationship between the dielectric layer and the interface.
This ambiguity is particularly significant in view of parent claim 13, which recites the dielectric layer “on the heterostructure” and “entirely covering the first surface of the insulation layer.” The additional requirement of claim 16 that the dielectric layer itself be “coplanar with” the interface does not clearly identify which portion or surface of the dielectric layer establishes the claimed coplanar relationship.
Thus, the claim does not provide a reasonably certain structural boundary for determining whether a dielectric layer having a finite thickness satisfies the recited “coplanar” relationship. The Examiner would be required to speculate as to which surface or portion of the dielectric layer is intended to be coplanar with the interface between the heterostructure and the insulation layer.
Accordingly, the metes and bounds of claim 16 cannot be determined with reasonable certainty, rendering claim 16 indefinite under 35 U.S.C. 112(b).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Examiner conducted a comprehensive analysis of obviousness analysis including the Graham v. Deere analysis for each claim by (A) determining the scope and content of a reference claim relative to the claim in the application at issue; (B) determining the differences between the scope and content of the reference claim as determined in (A) and the claim in the application at issue; (C) determining the level of ordinary skill in the pertinent art; and (D) evaluation any objective indicia of nonobviousness.
The examiner has concluded that there is issue of double patenting rejection in the current application. This is because the claims in this application are deemed to be patentably does not distinct from any claims in a potential double patenting reference. Moreover, the examined application's claim is either anticipated or obvious over the reference claim(s).
Claims 2-4, 6 and 11 are rejected on the ground of nonstatutory double patenting as being unpatentable over U.S. Patent No. 11316038 (hereinafter Pat-38) in view of Saito et al. (US 20170077277; in the IDS on 10/7/24).
Regarding claim 2. Claim 10 of the Pat-38 recites a high-electron-mobility transistor (HEMT) comprising a heterostructure having a first surface; a first dielectric layer partially on the first surface of the heterostructure; an opening in the first dielectric layer exposing the first surface of the heterostructure; first and second electrodes extending in electrical contact with the heterostructure; a gate electrode covering a portion of the exposed surface of the heterostructure and extending between the first and second electrodes, wherein the gate electrode includes a gate metallization; a second dielectric layer on the heterostructure and on the first dielectric layer; and a passivation layer extending between the gate electrode and the first electrode and over the first dielectric layer, gate electrode, first electrode, and second electrode.
For purposes of comparison with instant claim 2, the first dielectric layer of claim 10 of the ’Pat-38 corresponds to the claimed insulation layer; the first and second electrodes correspond to the claimed first and second conductive terminals, respectively; the gate electrode including the gate metallization corresponds to the claimed gate terminal including the gate metallization; and the second dielectric layer corresponds to the claimed dielectric layer. Claim 10 of the Pat-38 also expressly recites a passivation layer disposed between the gate electrode and first electrode in the opening and extending over the gate electrode and first and second electrodes.
Thus, claim 10 of the Pat-38 teaches substantially the claimed HEMT arrangement, including the insulation layer and opening, first and second conductive terminals, gate terminal including gate metallization, dielectric layer, and passivation layer.
But claim 10 of the Pat-38 does not expressly recite (1) a substrate, a buffer layer on the substrate, and the heterostructure on the buffer layer, and (2) the dielectric layer entirely covering the first surface of the insulation layer.
However, Saito teaches these additional features. In particular, Saito teaches a semiconductor device having substrate 10 and buffer layer 12 disposed on substrate 10, with semiconductor structure 14, including semiconductor layers 14a and 14b, disposed over buffer layer 12 (Fig. 1; [0038], [0040]). Saito further teaches insulation layer 20 disposed on the semiconductor structure (Fig. 1; [0044]).
Saito additionally teaches dielectric layer 30 associated with the gate structure (Fig. 1; [0048]). As illustrated in Fig. 1, dielectric layer 30 extends over the upper surface of insulation layer 20 and continues into gate recess 16, such that dielectric layer 30 is disposed between the gate metallization and the underlying semiconductor structure and between the gate metallization and insulation layer 20. Further, dielectric layer 30 extends continuously across the upper surface of insulation layer 20, thereby teaching the limitation that the dielectric layer entirely covers the first surface of the insulation layer.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the HEMT of claim 10 of the Pat-38 in view of Saito by providing the heterostructure over a buffer layer disposed on a substrate and by extending the gate dielectric layer over the first surface of the insulation layer as taught by Saito. Such modification would have involved the use of known HEMT substrate/buffer and gate-dielectric arrangements in the HEMT of claim 10 of the Pat-38 according to their established functions, with a reasonable expectation of success.
Accordingly, instant claim 2 does not define a patentably distinct invention over claim 10 of Pat-38 in view of Saito, and claim 2 is rejected on the ground of nonstatutory obviousness-type double patenting.
Regarding claim 3, claims 10–11 of the Pat-38 in view of Saito teach the limitations of claim 3. Specifically, claim 11 of the Pat-38 further teaches the additional limitation of claim 3. Thus, claim 11 teaches the additional limitation recited in instant claim 3, while claim 10 of the Pat-38 in view of Saito teaches the limitations inherited from claim 2. Accordingly, instant claim 3 does not define a patentably distinct invention over claims 10–11 of the Pat-38 in view of Saito.
Regarding claim 4, claims 10–11 of the Pat-38 in view of Saito teach the limitations of claim 4. Specifically, Saito further teaches that heterostructure 14 includes GaN channel layer 14a and AlGaN barrier layer 14b (Saito, [0038]). Thus, Saito teaches the additional GaN channel-layer and AlGaN barrier-layer limitations recited in instant claim 4. Accordingly, instant claim 4 does not define a patentably distinct invention over claims 10–11 of the Pat-38 in view of Saito.
Regarding claim 6, claim 10 of the Pat-38 in view of Saito teaches the structural arrangement corresponding to the limitations of claim 6. Specifically, Saito teaches gate metallization 50/51a having a first portion extending into gate recess 16 over heterostructure 14 and a second portion extending over insulation layer 20 (Saito, Fig. 1). Dielectric layer 30 is interposed between the gate metallization and the heterostructure and between the gate metallization and insulation layer 20.
Thus, Saito teaches the claimed first and second portions of the gate metallization with respect to their respective positions over the heterostructure and insulation layer. However, because instant claim 6 recites these portions as being “directly on” the heterostructure and insulation layer while parent claim 2 requires the dielectric layer therebetween, claim 6 is indefinite for the reasons separately set forth under 35 U.S.C. § 112(b).
Regarding claim 11, claim 10 of the Pat-38 in view of Saito teaches the limitations of claim 11. Specifically, Saito teaches the insulation layer is between the gate metallization and the second conductive terminal along the second direction.. Thus, the combination of claim 10 of the Pat-38 and Saito teaches the additional limitation recited in instant claim 11.
Accordingly, for the same reasons set forth above with respect to claim 2, instant claim 11 does not define a patentably distinct invention over claim 10 of the Pat-38 in view of Saito.
Claims 13-15 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 10 of U.S. Patent No. 11316038 (hereinafter “the Pat-38”) in view of Dora et al. (US 20120223320).
Claim 10 of the Pat-38 claims a high-electron-mobility transistor (HEMT) comprising a heterostructure having a first surface; a first dielectric layer partially on the first surface of the heterostructure; an opening in the first dielectric layer exposing the first surface of the heterostructure; first and second electrodes extending in electrical contact with the heterostructure; a gate electrode covering a portion of the exposed surface of the heterostructure and extending between the first and second electrodes, wherein the gate electrode includes a gate metallization; a second dielectric layer on the heterostructure and on the first dielectric layer; and a passivation layer extending between the gate electrode and the first electrode and over the first dielectric layer, gate electrode, first electrode, and second electrode.
For purposes of comparison with instant claim 13, the first dielectric layer of claim 10 of the Pat-38 corresponds to the claimed insulation layer; the first and second electrodes correspond to the claimed first and second conductive terminals, respectively; the gate electrode including the gate metallization corresponds to the claimed gate terminal including the gate metallization; and the second dielectric layer corresponds to the claimed dielectric layer. Claim 10 of the Pat-38 further recites a passivation layer disposed between the gate electrode and first electrode in the opening and extending over the first dielectric layer, gate electrode, and first and second electrodes.
Thus, claim 10 of the Pat-38 teaches substantially the underlying HEMT arrangement of instant claim 13, including the heterostructure, insulation layer and opening, first and second conductive terminals, gate terminal including gate metallization, dielectric layer, and passivation layer.
But claim 10 of the Pat-38 does not expressly teach the particular field-plate configuration of instant claim 13, including a field plate element on the insulation layer and the field plate element being coplanar with the first surface of the first portion.
However, Dora teaches these additional field-plate features. In particular, Dora teaches an electrode-defining insulation layer 33 and an electrode 34 having an extending portion that functions as a field plate. Dora further teaches that the electrode may be a gate electrode of a transistor. Dora further describes the stepped configuration of the electrode-defining layer and extending electrode portion.
More particularly, Fig. 5 of Dora illustrates insulation layer 33 having portions disposed on opposite sides of the gate-region opening and gate/field-plate electrode 34 extending over the underlying heterostructure and laterally over insulation layer 33 in a stepped configuration. The right-hand portion of insulation layer 33 corresponds to the claimed first portion. As illustrated in Fig. 5, the intermediate or middle step of field-plate electrode 34 has a substantially horizontal upper surface that lies in the same plane as the upper/top surface of the right-hand portion of insulation layer 33. Accordingly, Fig. 5 teaches the claimed relationship in which the field plate element is coplanar with the first surface of the first portion.
Dora further illustrates conductive terminals 28 extending through respective openings in insulation layer 33 and into/contacting the underlying semiconductor structure. Thus, Dora's field-plate arrangement is structurally compatible with the through-insulation-layer conductive-terminal arrangement recited in instant claim 13.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the gate metallization of the HEMT of claim 10 of the Pat-38 to include the field-plate configuration taught by Dora. Dora expressly teaches using an extending portion of an electrode as a field plate and teaches that such an electrode may constitute a gate electrode of a transistor. One of ordinary skill in the art therefore would have had reason to provide the gate metallization of the HEMT of claim 10 of the Pat-38 with Dora's laterally extending stepped field-plate configuration in order to obtain the known electric-field-control function provided by a field plate. Such modification would have involved applying a known HEMT field-plate configuration according to its established function, with a reasonable expectation of success.
In the resulting combination, the gate metallization includes a portion associated with the gate opening and a field-plate element extending laterally on the insulation layer, with the stepped geometry taught by Dora providing the claimed relationship in which the field plate element is coplanar with the first surface of the first portion.
Accordingly, instant claim 13 does not define a patentably distinct invention over claim 10 of Pat-38 in view of Dora, and claim 13 is rejected on the ground of nonstatutory obviousness-type double patenting.
Regarding claim 14, claim 10 of the Pat-38 in view of Dora teaches the limitations of claim 14. Specifically, claim 10 of the Pat-38 further teaches a passivation layer on and contacting the first surface of the heterostructure exposed by the first dielectric layer, the passivation layer being beside the gate electrode and the first electrode in the opening and covering the second portion of the first surface. Thus, claim 10 of the Pat-38 teaches the additional passivation-layer contact and positional relationship recited in instant claim 14, while claim 10 of the Pat-38 in view of Dora teaches the limitations inherited from claim 13.
Accordingly, instant claim 14 does not define a patentably distinct invention over claim 10 of the Pat-38 in view of Dora.
Regarding claim 15, claims 10–11 of the Pat-38 in view of Dora teach the limitations of claim 15. Specifically, claim 11 of the Pat-38 further teaches the additional limitation recited in instant claim 15. Thus, claim 11 of the Pat-38 teaches the additional subject matter recited in instant claim 15, while claim 10 of the Pat-38 in view of Dora teaches the limitations inherited from claim 13, including the field-plate configuration and coplanar relationship discussed above.
Accordingly, instant claim 15 does not define a patentably distinct invention over claims 10–11 of the Pat-38 in view of Dora.
Claim 19 is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 10 and 14 of U.S. Patent No. 11,316,038 (hereinafter “the Pat-38”) in view of Inoue et al. (US 20140353720).
Claim 10 of the Pat-38 claims a high-electron-mobility transistor (HEMT) comprising a heterostructure having a first surface; a first dielectric layer partially on the first surface of the heterostructure; an opening in the first dielectric layer exposing the first surface of the heterostructure; first and second electrodes extending in electrical contact with the heterostructure; a gate electrode covering a portion of the exposed first surface of the heterostructure and extending between the first and second electrodes, wherein the gate electrode includes a gate metallization; a second dielectric layer on the heterostructure and on the first dielectric layer; and a passivation layer extending between the gate electrode and the first electrode and over the first dielectric layer, gate electrode, first electrode, and second electrode.
Claim 10 further recites that the passivation layer is on and contacting the first surface of the heterostructure exposed by the first dielectric layer, is disposed beside the gate electrode and the first electrode in the opening, and covers the second portion of the first surface of the heterostructure.
For purposes of comparison with instant claim 19, the first dielectric layer of claim 10 of the Pat-38 corresponds to the claimed insulation layer; the first and second electrodes correspond to the claimed first and second conductive terminals, respectively; and the gate electrode including the gate metallization corresponds to the claimed gate terminal including the gate metallization. Thus, claim 10 teaches substantially the underlying HEMT structure and the claimed passivation-layer arrangement of instant claim 19.
Claim 14 of the Pat-38 further teaches the claimed field-plate arrangement. Specifically, claim 14 recites “a field-plate metal layer extending on the passivation layer and above the gate and first electrodes, the passivation layer electrically insulating the field-plate metal layer from the gate and first electrodes.” Accordingly, claims 10 and 14 of the Pat-38 together teach a HEMT having the claimed gate and conductive-terminal arrangement, the passivation layer, and a field-plate metal layer disposed on the passivation layer.
But Claims 10 and 14 of the Pat-38 do not expressly recite the additional limitation of instant claim 19 requiring a dielectric layer on the field-plate metal layer and the passivation layer.
However, Inoue teaches this additional dielectric-layer arrangement. In particular, Inoue teaches a HEMT having gate electrode GE provided with a field-plate electrode FP. Inoue expressly explains that field-plate electrode FP is formed as part of gate electrode GE and extends from the gate structure toward drain electrode DE. Inoue, [0111].
Inoue further teaches forming an insulating layer IL1 over the gate structure. Specifically, Inoue teaches that insulating layer IL1, which may be a silicon oxide film, is formed on gate electrode GE, insulating film IF1, and barrier layer BA. Inoue, [0114]. Because field-plate electrode FP is expressly a portion of gate electrode GE, formation of IL1 on gate electrode GE necessarily places IL1 on field-plate electrode FP. As further illustrated in Fig. 16, the insulating layer extends over the field-plate structure and over the adjacent underlying device region toward drain electrode DE.
Inoue additionally confirms that the gate electrode GE has insulating layer IL1 thereon and that the device may include a further insulating layer IL2 over the upper device structure. Inoue, [0093]. Thus, Inoue demonstrates that providing an insulating/dielectric layer over a gate-associated field-plate electrode was a known HEMT structure.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the HEMT defined by claims 10 and 14 of the Pat-38 by providing a dielectric layer over the field-plate metal layer and the adjacent passivation layer, as taught by Inoue. Claims 10 and 14 already provide the underlying HEMT, passivation layer, and field-plate metal layer on the passivation layer, while Inoue teaches forming an insulating/dielectric layer over a gate-associated field-plate structure and adjacent device regions.
One of ordinary skill in the art would have recognized the use of such an overlying dielectric layer as a conventional insulating arrangement for electrically insulating and protecting the underlying gate/field-plate structure. The modification would merely apply Inoue's known dielectric-over-field-plate arrangement to the field-plate structure already claimed in claims 10 and 14 of the Pat-38, with the respective components performing their established insulating and field-control functions and with a reasonable expectation of success.
In the resulting combination, the HEMT of claims 10 and 14 of the Pat-38 would include the field-plate metal layer on the passivation layer, as expressly required by claim 14, together with a dielectric layer disposed on the field-plate metal layer and the adjacent passivation layer, as taught by Inoue.
Accordingly, instant claim 19 does not define a patentably distinct invention over claims 10 and 14 of the Pat-038 in view of Inoue, and claim 19 is rejected on the ground of nonstatutory obviousness-type double patenting.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-7 and 9-18 are rejected under 35 U.S.C. 103 as being unpatentable over Inoue et al. (US 20150145004) in view of Chowdhury (US 20140231823).
Regarding claim 2, Inoue discloses a device comprising a substrate (S) and a buffer layer (BU) on the substrate (Inoue, ¶[0087], Fig. 1); and a heterostructure (BA + CH) on the buffer layer, wherein channel layer CH and barrier layer BA collectively form the heterostructure (Inoue, ¶[0087], Fig. 1). Inoue further teaches that channel layer CH includes GaN (Inoue, ¶[0108]) and barrier layer BA includes AlGaN (Inoue, ¶[0109]), thereby forming the recited heterostructure.
Inoue further discloses an insulation layer (IF1a) on the heterostructure, wherein IF1a is an N-rich silicon nitride film (Inoue, ¶[0097], Fig. 1). As shown in Fig. 1, insulation layer IF1a has a first surface (top surface) opposite a second surface (bottom surface) along a first direction (vertical direction).
Inoue further discloses a first opening (OA1) extending from the first surface of insulation layer IF1a to the second surface of insulation layer IF1a (Inoue, ¶[0094], Fig. 1).
Inoue further discloses first and second conductive terminals (SE and DE) extending along the first direction through insulation layer IF1a, wherein source electrode SE and drain electrode DE are disposed on opposite sides of gate electrode GE (Inoue, ¶¶[0092], [0096], Fig. 1). First opening OA1 is positioned between SE and DE along a second direction (horizontal direction) transverse to the first direction, as shown in Fig. 1. Inoue further teaches that SE and DE make ohmic contact with barrier layer BA (Inoue, ¶[0083]).
Inoue further discloses a gate terminal on the heterostructure and on the insulation layer, the gate terminal including a gate metallization (GE) in first opening OA1 on the heterostructure and on the insulation layer (Inoue, ¶¶[0087], [0093]-[0095], Fig. 1). Inoue further teaches that field plate electrode FP is provided as a part of gate electrode GE (Inoue, ¶[0121], Fig. 1). Accordingly, GE including FP corresponds to the claimed gate metallization.
Inoue further discloses a dielectric layer (GI + IF1b) between the gate metallization and the heterostructure and between the gate metallization and the insulation layer. Specifically, Inoue discloses Si-rich silicon nitride film IF1b disposed over N-rich silicon nitride film IF1a (Inoue, ¶¶[0097]-[0099], Fig. 1). As shown in Fig. 1, IF1b extends continuously over and entirely covers the first/top surface of insulation layer IF1a. Inoue further discloses gate insulation film GI in the gate-opening region (Inoue, ¶[0120], Fig. 1), wherein GI extends into the gate-opening region along the exposed semiconductor structure and contacts the insulating structure. Accordingly, IF1b and GI collectively form a dielectric structure extending over the first surface of IF1a and into the gate-opening region. As further shown in Fig. 1, the GI portion of the dielectric structure is between gate metallization GE and the underlying BA/CH heterostructure, while the IF1b portion is between gate metallization GE/FP and insulation layer IF1a. Thus, Inoue teaches a dielectric layer between the gate metallization and the heterostructure and between the gate metallization and the insulation layer, the dielectric layer entirely covering the first surface of the insulation layer, as recited in claim 2.
Inoue further discloses a passivation layer (IL1) on the first and second conductive terminals, the gate terminal, and the heterostructure (Inoue, ¶[0103], Fig. 1). Inoue further teaches forming IL1 over gate electrode GE, source electrode SE, drain electrode DE, the insulating structure, and exposed barrier layer BA (Inoue, ¶[0125], Fig. 1).
Particularly, Inoue teaches the claimed relationship wherein the passivation layer is in the first opening between the first conductive terminal and the gate metallization along the second direction. As shown in Fig. 1, gate metallization GE defines a valley-shaped region within opening OA1, and passivation layer IL1 extends downward into and occupies the valley-shaped region within OA1. Accordingly, IL1 is not merely above or adjacent to opening OA1; rather, at least a portion of IL1 is physically located within the spatial boundaries of first opening OA1. Further, the portion of IL1 within OA1 is laterally positioned between first conductive terminal SE and gate metallization GE along the horizontal/second direction. Thus, Fig. 1 shows the structural relationship SE → IL1 within OA1 → GE along the second direction. Accordingly, Inoue teaches “the passivation layer being in the first opening between the first conductive terminal and the gate metallization along the second direction,” as recited in claim 2.
But, although Inoue teaches source and drain electrodes SE and DE extending through the overlying insulation structure and making ohmic contact with the underlying semiconductor structure, Inoue does not expressly disclose the first conductive terminal extending along the first direction entirely through the insulation layer and into the heterostructure and the second conductive terminal extending along the first direction entirely through the insulation layer and into the heterostructure, as recited in claim 2. Inoue teaches removing insulating film IF1 from the source and drain electrode formation regions to expose barrier layer BA, forming electrode metal over the exposed BA, and heat treating the metal/semiconductor interface to establish ohmic contact (Inoue, ¶¶[0122]-[0124]).
However, Chowdhury teaches these additional features. Chowdhury discloses a III-N HEMT having a heterostructure comprising III-N layers 11 and 12 having different compositions, with a two-dimensional electron gas (2DEG) channel 19 induced in channel layer 11 near the interface between channel layer 11 and barrier layer 12 (Chowdhury, ¶[0014], Fig. 4). Chowdhury further discloses source and drain contacts 14 and 15, respectively (Chowdhury, ¶[0032], Fig. 4). As shown in Fig. 4, source and drain contacts 14 and 15 extend along the vertical/first direction entirely through the overlying insulation layer 21 and into the III-N heterostructure comprising layers 11 and 12. Thus, Chowdhury teaches first and second conductive terminals extending along the first direction entirely through the insulation layer and into the heterostructure, as recited in claim 2.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the source and drain contact configuration of Inoue according to the known source and drain contact configuration taught by Chowdhury, such that Inoue's source and drain electrodes SE and DE extend entirely through the insulation layer and into the underlying III-N heterostructure. Both Inoue and Chowdhury relate to III-N HEMT devices having source and drain contacts electrically coupled to an underlying III-N heterostructure and conductive channel. Inoue already teaches removing insulating material from the source and drain electrode formation regions to expose barrier layer BA, forming source and drain electrode metal over the exposed BA, and establishing ohmic contact with the semiconductor structure (Inoue, ¶¶[0122]-[0124]), while Chowdhury teaches a known III-N HEMT source/drain contact configuration in which source and drain contacts 14 and 15 extend through insulation layer 21 and into the III-N heterostructure to provide electrical contact to 2DEG channel 19 (Chowdhury, ¶¶[0014], [0032], Fig. 4).
Accordingly, one of ordinary skill in the art would have been motivated to employ Chowdhury's known embedded source/drain contact configuration in Inoue, thereby extending Inoue's source and drain electrodes into the III-N heterostructure while maintaining the ohmic electrical coupling to the underlying conductive channel sought by both references. Such a modification represents the application of a known III-N HEMT contact geometry to the corresponding source and drain contacts of Inoue for the same electrical-contact function, with a reasonable expectation of success.
Accordingly, Inoue in view of Chowdhury teaches or suggests all of the limitations of claim 2.
Regarding claim 3, Inoue in view of Chowdhury discloses the device of claim 2. Inoue further teaches a heterostructure comprising channel layer CH and barrier layer BA (Inoue, ¶[0087], Fig. 1). Inoue specifically teaches that channel layer CH is GaN (Inoue, ¶[0108]) and that barrier layer BA is AlGaN (Inoue, ¶[0109]). Thus, Inoue teaches the additional GaN channel-layer and AlGaN barrier-layer limitations recited in claim 3. Accordingly, Inoue in view of Chowdhury teaches or suggests all of the limitations of claim 3.
Regarding claim 4, Inoue in view of Chowdhury discloses the device of claim 3. Inoue further teaches that the heterostructure comprises GaN channel layer CH and AlGaN barrier layer BA (Inoue, ¶¶[0108]-[0109], Fig. 1). Specifically, Inoue teaches that channel layer CH is formed of GaN (¶[0108]) and barrier layer BA is formed of AlGaN (¶[0109]). Thus, Inoue teaches the additional GaN channel-layer and AlGaN barrier-layer limitations recited in claim 4. Accordingly, Inoue in view of Chowdhury teaches or suggests all of the limitations of claim 4.
Regarding claim 5, Inoue in view of Chowdhury discloses the device of the claim 3. Chowdhury further teaches a two-dimensional electron gas (2DEG) channel 19 induced in channel layer 11 near the interface between channel layer 11 and barrier layer 12, and source and drain contacts 14 and 15 electrically coupled to the 2DEG channel 19 (Chowdhury, ¶[0014]). Thus, Chowdhury teaches the additional limitation recited in claim 5. Accordingly, Inoue in view of Chowdhury teaches or suggests all of the limitations of claim 5.
Regarding claim 6, Inoue in view of Chowdhury discloses the device of claim 2. Chowdhury further discloses gate metallization 59 having a first portion disposed in opening 51 directly on the heterostructure along the first direction and a second portion disposed in opening 53 directly on insulation layer 33 along the first direction (Chowdhury, ¶¶[0029]-[0030]). Specifically, the portion of gate metallization 59 in opening 51 extends directly to the underlying heterostructure, while the portion of gate metallization 59 in opening 53 is directly on insulation layer 33. Thus, Chowdhury teaches the additional limitation that the gate metallization includes a first portion in the first opening directly on the heterostructure along the first direction and a second portion directly on the insulation layer along the first direction, as recited in claim 6. Accordingly, Inoue in view of Chowdhury teaches or suggests all of the limitations of claim 6.
Regarding claim 7, Inoue in view of Chowdhury discloses the device of claim 2. Inoue further discloses passivation layer IL1 directly contacting dielectric layer IF1b, gate metallization GE, first and second conductive terminals DE and SE, and the heterostructure BA/CH, as shown in Fig. 1. Inoue teaches that IL1 is formed over gate electrode GE, source electrode SE, and drain electrode DE (Inoue, ¶[0103]), and further teaches forming IL1 over GE, the insulating structure, and exposed barrier layer BA (Inoue, ¶[0125]). As particularly shown in Fig. 1, IL1 directly contacts IF1b, GE, DE, SE, and exposed BA of the heterostructure without an intervening layer at the respective interfaces. Thus, Inoue teaches the additional limitation that the passivation layer is directly in contact with the dielectric layer, the gate metallization, the first and second conductive terminals, and the heterostructure, as recited in claim 7. Accordingly, Inoue in view of Chowdhury teaches or suggests all of the limitations of claim 7.
Regarding claim 9, Inoue in view of Chowdhury discloses the device of claim 3. Inoue further discloses that the dielectric layer and the passivation layer are directly on barrier layer BA. Specifically, as shown in Fig. 1, the GI portion of the dielectric layer comprising IF1b and GI is directly on barrier layer BA in the gate-opening region, while passivation layer IL1 is directly on exposed barrier layer BA adjacent to gate electrode GE (Inoue, ¶¶[0120], [0125], Fig. 1). Thus, Inoue teaches that the dielectric layer and the passivation layer are directly on the barrier layer, as recited in claim 9. Accordingly, Inoue in view of Chowdhury teaches or suggests all of the limitations of claim 9.
Regarding claim 10, Inoue in view of Chowdhury discloses the device of claim 2. Chowdhury further discloses gate metallization 59 having a first surface facing first conductive terminal 14 along the second direction, as shown in Fig. 4, particularly in region 55. Chowdhury further discloses dielectric layer 33 ([0032]) adjacent to gate metallization 59. As shown in Fig. 4, gate metallization 59 has a stepped configuration, wherein the upper surface of the step immediately below the topmost step of gate metallization 59 is coplanar with the top surface of dielectric layer 33. Thus, Chowdhury teaches that the gate metallization includes a first surface facing the first conductive terminal along the second direction, the first surface of the gate metallization being coplanar with a first surface of the dielectric layer, as recited in claim 10. Accordingly, Inoue in view of Chowdhury teaches or suggests all of the limitations of claim 10.
Regarding claim 11, Inoue in view of Chowdhury discloses the device of claim 2. Inoue further discloses insulation layer IF1a positioned between gate metallization GE and second conductive terminal SE along the second direction, as shown in Fig. 1. Specifically, Fig. 1 shows IF1a extending laterally between GE and SE, wherein the horizontal direction corresponds to the claimed second direction. Thus, Inoue teaches the additional limitation that the insulation layer is between the gate metallization and the second conductive terminal along the second direction, as recited in claim 11. Accordingly, Inoue in view of Chowdhury teaches or suggests all of the limitations of claim 11.
Regarding claim 12, Inoue in view of Chowdhury discloses the device of claim 10. Inoue further discloses a first surface (top surface) of gate metallization GE, as shown in Fig. 1. However, as discussed above with respect to the rejection under 35 U.S.C. 112(b), claim 12 is incomplete and fails to define the scope of the claimed subject matter with reasonable certainty. Because the claim is incomplete, the Examiner cannot ascertain the full scope of claim 12 without speculating as to the omitted claim language. Accordingly, claim 12 is not susceptible to a meaningful prior-art examination in its present form. Upon correction of claim 12 to provide a complete and definite claim, the claim will be examined for patentability over the prior art.
Regarding claim 13, Inoue discloses a device comprising a heterostructure (BA + CH) on a buffer layer, wherein channel layer CH and barrier layer BA collectively form the heterostructure (Inoue, ¶[0092], Fig. 1); an insulation layer (IF1a) on the heterostructure, wherein IF1a is an N-rich silicon nitride film contacting barrier layer BA (Inoue, ¶¶[0097], [0099], Fig. 1), the insulation layer having a first surface (top surface of IF1a) opposite the heterostructure along a first direction (vertical direction) (Fig. 1); and a first opening (OA1) extending from the first surface of insulation layer IF1a to the heterostructure (Inoue, ¶¶[0093]-[0094], Fig. 1).
Inoue further discloses first and second conductive terminals (SE and DE) extending along the first direction through the insulation layer, wherein source electrode SE and drain electrode DE are provided on opposite sides of gate electrode GE over barrier layer BA (Inoue, ¶[0096], Fig. 1). First opening OA1 is positioned between SE and DE along a second direction (horizontal direction) transverse to the first direction, as shown in Fig. 1.
Inoue further discloses a dielectric layer (GI + IF1b) on the heterostructure and entirely covering the first surface of insulation layer IF1a. Specifically, Inoue discloses Si-rich silicon nitride film IF1b disposed over N-rich silicon nitride film IF1a (Inoue, ¶¶[0097]-[0099], Fig. 1). As shown in Fig. 1, IF1b extends continuously over and entirely covers the first/top surface of IF1a. Inoue further discloses gate insulation film GI in the gate-opening region (Inoue, ¶[0120], Fig. 1), wherein GI extends into the opening along the exposed semiconductor structure and contacts the insulating structure. Accordingly, IF1b and GI collectively form the dielectric structure extending over the first surface of IF1a and into the gate-opening region, thereby teaching a dielectric layer on the heterostructure and entirely covering the first surface of the insulation layer.
Inoue further discloses a gate metallization (GE) in first opening OA1 (Inoue, ¶¶[0093], [0095], Fig. 1), the gate metallization including a first portion (the portion of GE facing first conductive terminal SE) in the first opening having a first surface (top surface of the first portion) opposite the dielectric layer along the first direction and a second surface (lateral surface of the first portion) transverse to the first surface. As shown in Fig. 1, the second surface faces first conductive terminal SE along the second direction and extends entirely from the first/top surface of the first portion to the dielectric layer along the first direction.
Inoue further discloses a field plate element (FP) on the insulation layer (Inoue, ¶[0095], Fig. 1). Inoue further teaches that gate electrode GE is patterned to provide field plate electrode FP as a part of gate electrode GE (Inoue, ¶[0121], Fig. 1). As shown in Fig. 1, FP extends laterally over insulation layer IF1a, with dielectric layer IF1b disposed between FP and IF1a along the first direction. Further, the top surface of field plate element FP is coplanar with the first/top surface of the first portion of gate metallization GE. Thus, Inoue teaches a field plate element on the insulation layer, the field plate element being coplanar with the first surface of the first portion, the dielectric layer being between the field plate element and the insulation layer along the first direction, as recited in claim 13.
Inoue further discloses a passivation layer (IL1) on the device structure (Inoue, ¶[0103], Fig. 1). Inoue further teaches forming IL1 over gate electrode GE, source electrode SE, drain electrode DE, insulating film IF1, and exposed barrier layer BA (Inoue, ¶[0125], Fig. 1). Particularly, as shown in Fig. 1, gate metallization GE defines a valley-shaped region within opening OA1, and passivation layer IL1 extends downward into and occupies the valley-shaped region within OA1. Accordingly, at least a portion of IL1 is physically located within the spatial boundaries of first opening OA1. Further, the portion of IL1 within OA1 is laterally positioned between first conductive terminal SE and the first portion of gate metallization GE along the second direction. Thus, Inoue teaches a passivation layer in the first opening between the first conductive terminal and the first portion of the gate metallization along the second direction, as recited in claim 13.
But, although Inoue teaches source and drain electrodes SE and DE extending through the overlying insulating structure and contacting the underlying semiconductor structure, Inoue does not expressly disclose the first and second conductive terminals extending “into the heterostructure,” as recited in claim 13. Inoue teaches removing insulating film IF1 from the source and drain electrode formation regions to expose barrier layer BA and subsequently forming SE and DE over the exposed BA (Inoue, ¶¶[0122]-[0123]).
However, Chowdhury teaches this additional feature. Chowdhury discloses a III-N HEMT having a heterostructure comprising III-N layers 11 and 12, with a two-dimensional electron gas (2DEG) channel 19 induced in channel layer 11 near the interface between channel layer 11 and barrier layer 12 (Chowdhury, ¶¶[0014], [0029], Fig. 4). Chowdhury further discloses source and drain contacts 14 and 15, respectively, disposed on opposite sides of the gate (Chowdhury, ¶[0032], Fig. 4). As shown in Fig. 4, source and drain contacts 14 and 15 extend along the vertical direction through the overlying insulating structure and into the III-N heterostructure comprising layers 11 and 12. Thus, Chowdhury teaches first and second conductive terminals extending along the first direction through the insulation layer and into the heterostructure, as recited in claim 13.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the source and drain contact configuration of Inoue according to the known source and drain contact configuration taught by Chowdhury, such that Inoue's source and drain electrodes SE and DE extend through the insulation layer and into the underlying III-N heterostructure. Both Inoue and Chowdhury relate to III-N HEMT devices having source and drain contacts electrically coupled to an underlying III-N heterostructure and conductive channel. Inoue already teaches removing the insulating material to expose barrier layer BA, forming source and drain electrode metal over the exposed BA, and establishing ohmic contact with the semiconductor structure (Inoue, ¶¶[0122]-[0124]), while Chowdhury teaches a known III-N HEMT source/drain contact configuration in which source and drain contacts 14 and 15 extend into the III-N heterostructure to provide electrical contact to the 2DEG channel (Chowdhury, ¶[0032], Fig. 4). Accordingly, one of ordinary skill in the art would have been motivated to employ Chowdhury's known embedded source/drain contact configuration in Inoue to provide electrical contact to the underlying conductive channel, with a reasonable expectation of success.
Regarding claim 14, Inoue in view of Chowdhury discloses the device of claim 13. As discussed above with respect to the rejection under 35 U.S.C. 112(b), for purposes of prior-art examination, “the gate terminal” is interpreted as referring to the gate metallization recited in claim 13. Inoue further discloses passivation layer IL1 directly on first and second conductive terminals SE and DE, gate metallization GE, and the heterostructure BA/CH (Inoue, ¶¶[0103], [0125], Fig. 1). Specifically, Inoue teaches IL1 formed over gate electrode GE, source electrode SE, and drain electrode DE (Inoue, ¶[0103]) and further teaches forming IL1 over GE, the insulating structure, and exposed barrier layer BA (Inoue, ¶[0125]). As shown in Fig. 1, IL1 directly contacts SE, DE, GE, and exposed barrier layer BA of the BA/CH heterostructure. Thus, Inoue teaches the passivation layer directly on the first and second conductive terminals, the gate terminal, and the heterostructure, as recited in claim 14 under the foregoing interpretation. Accordingly, Inoue in view of Chowdhury teaches or suggests all of the limitations of claim 14.
Regarding claim 15, Inoue in view of Chowdhury discloses the device of claim 13. Inoue further discloses that the heterostructure includes a channel layer (CH) and a barrier layer (BA) between the channel layer CH and insulation layer IF1a (Inoue, ¶¶[0087], [0108]-[0109], Fig. 1). Specifically, Inoue teaches that channel layer CH comprises GaN (Inoue, ¶[0108]) and barrier layer BA comprises AlGaN (Inoue, ¶[0109]), thereby forming the heterostructure. As shown in Fig. 1, barrier layer BA is disposed over channel layer CH and between channel layer CH and insulation layer IF1a. Thus, Inoue teaches “the heterostructure includes a channel layer and a barrier layer between the channel layer and the insulation layer,” as recited in claim 15. Accordingly, Inoue in view of Chowdhury teaches or suggests all of the limitations of claim 15.
Regarding claim 16, Inoue in view of Chowdhury discloses the device of claim 13. Inoue further discloses that the dielectric layer (GI + IF1b) is coplanar with an interface between the heterostructure (BA/CH) and insulation layer IF1a, as shown in Fig. 1. Specifically, Inoue discloses N-rich silicon nitride film IF1a and Si-rich silicon nitride film IF1b (Inoue, ¶¶[0097]-[0099], Fig. 1). As shown in Fig. 1, the lateral surfaces of IF1a and IF1b terminate at the top surface of barrier layer BA, and the lateral surface of IF1b is coplanar with the interface formed between barrier layer BA and insulation layer IF1a. Thus, a surface of the dielectric layer is coplanar with the interface between the heterostructure and the insulation layer. Accordingly, Inoue teaches “the dielectric layer is coplanar with an interface between the heterostructure and the insulation layer,” as recited in claim 16. Therefore, Inoue in view of Chowdhury teaches or suggests all of the limitations of claim 16.
Regarding claim 17, Inoue in view of Chowdhury discloses the device of claim 13. Inoue further discloses that the dielectric layer (GI + IF1b) entirely physically separates gate metallization GE/FP from insulation layer IF1a and from the heterostructure BA/CH, as shown in Fig. 1. Specifically, Inoue discloses Si-rich silicon nitride film IF1b over insulation layer IF1a (Inoue, ¶¶[0097]-[0099], Fig. 1), wherein IF1b is physically interposed between field plate portion FP of gate metallization GE and insulation layer IF1a. Inoue further discloses gate insulation film GI in the gate-opening region (Inoue, ¶[0120], Fig. 1), wherein GI is physically interposed between gate metallization GE and the underlying heterostructure BA/CH. Inoue further teaches that field plate electrode FP is provided as a part of gate electrode GE (Inoue, ¶[0121], Fig. 1). Accordingly, the dielectric structure comprising IF1b and GI continuously intervenes between gate metallization GE/FP and insulation layer IF1a and between gate metallization GE and the underlying heterostructure BA/CH, such that the gate metallization does not directly contact either the insulation layer or the heterostructure. Thus, Inoue teaches “the dielectric layer entirely physically separates the gate metallization from the insulation layer and from the heterostructure,” as recited in claim 17. Accordingly, Inoue in view of Chowdhury teaches or suggests all of the limitations of claim 17.
Regarding claim 18, Inoue in view of Chowdhury discloses the device of claim 13. Inoue further discloses that a distance between first conductive terminal SE and gate metallization GE is constant along the first direction from the first surface of the first portion of GE to the dielectric layer, as shown in Fig. 1. Specifically, the first portion of gate metallization GE has a substantially vertical side surface facing first conductive terminal SE along the second direction, and first conductive terminal SE has a corresponding surface extending along the first direction. As shown in Fig. 1, these facing surfaces extend substantially parallel to one another such that the lateral distance between SE and the first portion of GE remains constant along the first/vertical direction from the first/top surface of the first portion to the dielectric layer. Thus, Inoue teaches “a distance between the first conductive terminal and the gate metallization is a constant along the first direction from the first surface of the first portion to the dielectric layer,” as recited in claim 18. Accordingly, Inoue in view of Chowdhury teaches or suggests all of the limitations of claim 18.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Inoue (US 20150145004) in view of Chowdhury (US 20140231823), and further in view of Saito (US 20170077277).
Regarding claim 8, Inoue in view of Chowdhury discloses the device of claim 7. But, Inoue in view of Chowdhury does not disclose the insulation layer is entirely separated from the passivation layer by the dielectric layer.
However, Saito further discloses an insulation layer (first film 20; [0044]) entirely separated from a passivation layer (second film 22; [0047]) by a dielectric layer (first oxide film 30; [0048]), as shown in Fig. 1. Specifically, Saito teaches that second film 22 is provided on first film 20 ([0047]) and that first oxide film 30 is provided between first film 20 and second film 22 ([0048]). Saito further teaches that first oxide film 30 is a gate insulating film including, for example, silicon oxide or aluminum oxide ([0048]). Accordingly, Fig. 1 shows first oxide film 30 intervening between first film 20 and second film 22 such that insulation layer 20 is entirely separated from passivation layer 22 by dielectric layer 30, as recited in claim 8.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Inoue in view of Chowdhury to include the intervening dielectric-layer arrangement taught by Saito, such that the insulation layer is entirely separated from the passivation layer by the dielectric layer, because Saito teaches positioning dielectric first oxide film 30 between first film 20 and second film 22. Such a modification would have provided a known dielectric separation between the underlying insulation layer and the overlying passivation layer, thereby providing electrical insulation between the respective layers, using a known semiconductor-layer arrangement to obtain the predictable insulating function of the intervening dielectric material.
Accordingly, Inoue in view of Chowdhury and further in view of Saito teaches or suggests all of the limitations of claim 8.
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Inoue et al. (US 20150145004; hereinafter “Inoue-004”) in view of Chowdhury et al. (US 20140231823), and further in view of Inoue et al. (US 20140353720; hereinafter “Inoue-720”).
Regarding claim 19, Inoue-004 discloses a device comprising a heterostructure (BA + CH), wherein channel layer CH and barrier layer BA collectively form the heterostructure (Inoue-004, ¶[0087], Fig. 1). Inoue-004 further teaches that channel layer CH includes GaN (Inoue-004, ¶[0108]) and barrier layer BA includes AlGaN (Inoue-004, ¶[0109]), thereby forming the recited heterostructure.
Inoue-004 further discloses an insulation layer (IF1a) on the heterostructure, wherein IF1a is an N-rich silicon nitride film (Inoue-004, ¶¶[0097]-[0099], Fig. 1). As shown in Fig. 1, insulation layer IF1a has a first surface (top surface) opposite a second surface (bottom surface) along a first direction (vertical direction).
Inoue-004 further discloses a first opening (OA1) extending from the first/top surface of insulation layer IF1a to the second/bottom surface of insulation layer IF1a (Inoue-004, ¶¶[0093]-[0094], Fig. 1).
Inoue-004 further discloses a plurality of conductive terminals, including source electrode SE and drain electrode DE, extending along the first direction through insulation layer IF1a (Inoue-004, ¶¶[0092], [0096], Fig. 1). Source electrode SE and drain electrode DE are positioned on opposite sides of gate electrode GE, with first opening OA1 positioned therebetween along a second direction (horizontal direction) transverse to the first direction, as shown in Fig. 1.
Inoue-004 further discloses a gate metallization (GE) between the first and second conductive terminals SE and DE in first opening OA1 on the heterostructure (Inoue-004, ¶¶[0093]-[0095], Fig. 1).
Inoue-004 further discloses the claimed gate dielectric layer (GI + IF1b) between gate metallization GE and the heterostructure, the gate dielectric layer entirely covering the first surface of insulation layer IF1a. Specifically, Inoue-004 teaches that gate electrode GE is arranged via gate insulation film GI, that Si-rich silicon nitride film IF1b is arranged on the gate-insulation-film GI side, and that N-rich silicon nitride film IF1a is arranged on the barrier-layer BA side (Inoue-004, ¶[0099], Fig. 1). Inoue-004 further teaches gate insulation film GI in the gate-opening region (Inoue-004, ¶[0120], Fig. 1).
As shown in Fig. 1, GI extends along the exposed semiconductor surface in the gate-opening region between gate metallization GE and the underlying BA/CH heterostructure, while IF1b extends over and entirely covers the first/top surface of insulation layer IF1a. Accordingly, GI and IF1b collectively form the claimed gate dielectric layer, wherein the GI portion is disposed between gate metallization GE and the heterostructure and the IF1b portion entirely covers the first surface of insulation layer IF1a. Thus, Inoue-004 teaches “a gate dielectric layer between the gate metallization and the heterostructure, the gate dielectric layer entirely covering the first surface of the insulation layer,” as recited in claim 19.
Inoue-004 further discloses a passivation layer (IL1) on the plurality of conductive terminals, gate metallization GE, the gate dielectric layer, and directly on the heterostructure (Inoue-004, ¶¶[0103], [0125], Fig. 1). Specifically, Inoue-004 teaches IL1 formed over gate electrode GE, source electrode SE, and drain electrode DE (Inoue-004, ¶[0103]) and further teaches forming IL1 over GE, the insulating structure, and exposed barrier layer BA (Inoue-004, ¶[0125]). As shown in Fig. 1, IL1 overlies SE and DE, GE, and the gate dielectric structure and directly contacts exposed barrier layer BA of the BA/CH heterostructure.
Of particular significance, Inoue-004 further teaches the claimed relationship wherein the passivation layer is in the first opening between the first conductive terminal and the gate metallization along the second direction. As shown in Fig. 1, gate metallization GE defines a valley-shaped region within opening OA1, and passivation layer IL1 extends downward into and occupies the valley-shaped region within OA1. Accordingly, IL1 is not merely above or adjacent to opening OA1; rather, at least a portion of IL1 is physically located within the spatial boundaries of first opening OA1. Further, the portion of IL1 within OA1 is laterally positioned between the first conductive terminal and gate metallization GE along the horizontal/second direction. Thus, Inoue-004 teaches “the passivation layer being in the first opening between the first conductive terminal and the gate metallization along the second direction,” as recited in claim 19.
But, although Inoue-004 teaches source and drain electrodes SE and DE extending through the overlying insulation structure and making ohmic contact with the underlying semiconductor structure, Inoue-004 does not expressly disclose the plurality of conductive terminals extending along the first direction entirely through the insulation layer and into the heterostructure, as recited in claim 19.
However, Chowdhury teaches this additional feature. Chowdhury discloses a III-N HEMT having a heterostructure comprising III-N layers 11 and 12, with a two-dimensional electron gas (2DEG) channel 19 induced in channel layer 11 near the interface between channel layer 11 and barrier layer 12 (Chowdhury, ¶[0014], Fig. 4). Chowdhury further discloses source and drain contacts 14 and 15, respectively (Chowdhury, ¶[0032], Fig. 4). As shown in Fig. 4, source and drain contacts 14 and 15 extend along the vertical/first direction entirely through the overlying insulation layer and into the III-N heterostructure comprising layers 11 and 12. Thus, Chowdhury teaches the recited plurality of conductive terminals extending along the first direction entirely through the insulation layer and into the heterostructure.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the source and drain contact configuration of Inoue-004 according to the known source and drain contact configuration taught by Chowdhury, such that Inoue-004's source and drain electrodes SE and DE extend entirely through the insulation layer and into the underlying III-N heterostructure. Both Inoue-004 and Chowdhury relate to III-N HEMT devices having source and drain contacts electrically coupled to an underlying III-N heterostructure and conductive channel. Accordingly, one of ordinary skill in the art would have been motivated to employ Chowdhury's known embedded source/drain contact configuration in Inoue-004 to provide electrical contact to the underlying conductive channel, with predictable results and a reasonable expectation of success.
But, Inoue-004 in view of Chowdhury does not disclose a field-plate metal layer on the passivation layer and a dielectric layer on the field-plate metal layer and the passivation layer, as additionally recited in claim 19.
However, Inoue-720 teaches these additional features. Inoue-720 discloses a field-plate metal layer (FP) disposed on the passivation layer and a dielectric layer (IL2) disposed on field-plate metal layer FP and the passivation layer, as shown in Fig. 16 (Inoue-720, ¶¶[0093], [0111], [0113], Fig. 16). Thus, Inoue-720 teaches “a field-plate metal layer on the passivation layer; and a dielectric layer on the field-plate metal layer and the passivation layer,” as recited in claim 19.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the device of Inoue-004 in view of Chowdhury to include the field-plate and overlying dielectric arrangement taught by Inoue-720. Inoue-004 and Inoue-720 both concern semiconductor transistor structures employing field-plate arrangements and dielectric/passivation layers associated with the gate and drain regions. One of ordinary skill in the art would have recognized the field-plate arrangement of Inoue-720 as a known field-plate configuration suitable for incorporation into the corresponding transistor structure of Inoue-004 to provide the known electrical-field-management function of a field plate while electrically insulating and passivating the field-plate structure, with predictable results and a reasonable expectation of success.
Accordingly, Inoue-004 in view of Chowdhury and further in view of Inoue-720 teaches or suggests all of the limitations of claim 19.
Regarding claim 21, Inoue-004 in view of Chowdhury and further in view of Inoue-720 discloses the device of claim 19. Inoue-004 further teaches the claimed relative dimensional relationship. As shown in Fig. 25, Inoue-004 defines the lateral gate-source spacing as Lgs, the lateral gate dimension as Lg, and the lateral extension of field plate FP as Lfp. Thus, the relevant first dimension extending along the second/horizontal direction corresponds to approximately Lgs + Lg, whereas the second dimension of field-plate metal layer FP along the same direction corresponds to Lfp.
Inoue-004 expressly provides numerical values for these dimensions in Fig. 26. For the Type-II device, Lgs = 1 μm, Lg = 1 μm, and Lfp = 1 μm. Accordingly, the first dimension is approximately Lgs + Lg = 1 μm + 1 μm = 2 μm, whereas the second dimension of field-plate metal layer FP is Lfp = 1 μm. Thus, 2 μm > 1 μm, demonstrating a known field-plate arrangement in which the relevant dielectric-region dimension along the second direction is greater than the dimension of the field-plate metal layer along the same direction (Inoue-004, Figs. 25-26).
As discussed above with respect to claim 19, Inoue-720 further discloses dielectric layer IL2 on field-plate metal layer FP and the passivation layer, with IL2 extending laterally beyond FP and directly contacting the passivation layer in portions adjacent to FP. Thus, Inoue-720 teaches the additionally recited relationship wherein “the dielectric layer is directly in contact with the passivation layer.”
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, when incorporating the field-plate metal layer FP and overlying dielectric layer IL2 of Inoue-720 into the device of Inoue-004 in view of Chowdhury as set forth above with respect to claim 19, to provide the dielectric layer with a lateral dimension greater than the lateral dimension of the field-plate metal layer, consistent with the known relative field-plate/dielectric geometry taught by Inoue-004.
Inoue-004 expressly demonstrates such a known dimensional relationship in Figs. 25-26, including a Type-II configuration having a relevant first dimension of approximately 2 μm relative to a field-plate dimension of 1 μm. Applying this known relative dimensional arrangement to the IL2/FP structure of Inoue-720 would have involved selection of known relative dimensions for corresponding dielectric and field-plate structures and would have yielded the predictable result of IL2 extending laterally beyond FP and directly contacting the underlying passivation layer in the region outside FP.
Thus, the combined teachings disclose “the dielectric layer has a first dimension along the second direction greater than a second dimension of the field-plate metal layer along the second direction, and the dielectric layer is directly in contact with the passivation layer,” as recited in claim 21.
Accordingly, Inoue-004 in view of Chowdhury and further in view of Inoue-720 teaches or suggests all of the limitations of claim 21.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Changhyun Yi whose telephone number is (571)270-7799. The examiner can normally be reached Monday-Friday: 10A-3P.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Changhyun Yi/Primary Examiner, Art Unit 2812
Prosecution Insights