DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8, 10-12, and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KANG et al. (US PG Pub 2021/0210476, hereinafter Kang).
Regarding claim 1, figure 2B of Kang discloses a stack of microelectronic devices, comprising:
first bond pads (122 on the right) located proximate to, and distributed along, a first side of a first major surface of a first microelectronic device (120), each bond pad located proximate to, and distributed along, the first side of the major surface of the first microelectronic device being a first bond pad;
other bond pads (122 on the bottom) located proximate to, and distributed along, another, perpendicular side of the first major surface of the first microelectronic device, each bond pad located proximate to, and distributed along, the other side of the first major surface of the first microelectronic device being an other bond pad; and
second bond pads (132 on the left) located proximate to, and distributed along, a second side of a second major surface of a second microelectronic device (130) on which the first microelectronic device is supported, the second bond pads located proximate to a third side of the first microelectronic device opposite the first side;
wherein a first pitch of the first bond pads is greater than an other pitch of the other bond pads;
wherein the first pitch of the first bond pads is at least substantially equal to a second pitch of the second bond pads;
wherein the first bond pads and the second bond pads are offset from one another in a direction parallel to a first shortest distance between adjacent first bond pads by a pitch one-half of the first pitch of the first bond pads and of the second pitch of the second bond pads.
Note: An arbitrary subset of the bond pads shown in figure 2B can be chosen to read on the claimed bond pads, such that the limitations regarding the first (second, other) pitch and offset is met. This interpretation will be applied to the remainder of the claims.
Regarding claim 2, figure 2B of Kang discloses the second microelectronic device (130) is laterally and longitudinally offset from the microelectronic device (120).
Regarding claim 3, figure 2B of Kang discloses a line extending perpendicular to the first shortest distance between adjacent first bond pads, and intersecting a given first bond pad or second bond pad at any point, is free from intersection with any other first bond pad or second bond pad.
Regarding claim 4, figure 2B of Kang discloses the first bond pads (122 on the right) alternate with the second bond pads (132 on the left) as distance changes between the first side and the third side, as measured in a direction parallel to the first shortest distance.
Regarding claim 5, figure 2B of Kang discloses one of the first bond pads (122 on the right) is interposed between each adjacent pair of the second bond pads (132 on the left) and one of the second bond pads is interposed between each adjacent pair of the first bond pads, as measured in a direction parallel to the first shortest distance.
Regarding claim 6, figure 2B of Kang discloses the first shortest distance between adjacent first bond pads (122 on the right) is greater than a greatest first width of each one of the first bond pads, as measured in the direction parallel to the first shortest distance.
Regarding claim 7, figure 2B and 9 of Kang discloses the stack of microelectronic devices is supported on a substrate (192) and wherein a second shortest distance between adjacent second bond pads is greater than a greatest other width of each land of the substrate positioned and configured for connection to one of the first bond pads, the second bond pads, or the other bond pads, as measured in the direction parallel to the first shortest distance between adjacent first bond pads.
Regarding claim 8, figure 2B of Kang discloses the first pitch is between about 2 times and about 5 times greater than the other pitch.
Regarding claim 10, figure 2B of Kang discloses a stack of microelectronic devices supported on a substrate, the stack of microelectronic devices comprising:
a first row of bond pads (122 on the right) located proximate to, and distributed along, a first side of a first major surface of a first microelectronic device (120), each bond pad located proximate to, and distributed along, the first side of the major surface of the first microelectronic device being in the first row of bond pads;
an other row of bond pads (122 on the bottom) located proximate to, and distributed along, another, perpendicular side of the first major surface of the first microelectronic device, each bond pad located proximate to, and distributed along, the other side of the first major surface of the first microelectronic device being in the other row of bond pads; and
a second row of bond pads (132 on the left) located proximate to, and distributed along, a second side of a second major surface of a second microelectronic device (130) on which the first microelectronic device is supported, the second row of bond pads located proximate to a third side of the first microelectronic device opposite the first side;
wherein a first pitch of the bond pads in the first row of bond pads is greater than an other pitch of the bond pads in the other row of bond pads;
wherein the first pitch of the bond pads in the first row of bond pads is at least substantially equal to a second pitch of the bond pads in the second row of bond pads;
wherein the bond pads in the first bond pad row and the bond pads in the second bond pad row are offset from one another in a direction parallel to a first shortest distance between adjacent bond pads in the first bond pad row by a pitch one-half of the first pitch of the bond pads in the first bond pad row and of the second pitch of the bond pads in the second bond pad row.
Regarding claim 11, figure 2B of Kang discloses a processor (¶ 78); and
a memory device (¶ 78); wherein one or more of the processor and the memory device comprises a microelectronic device package including a stack of microelectronic devices comprising:
a first bond pad row (122 on the right) located proximate to, and extending along at least substantially an entirety of, a first side of a first major surface of a first microelectronic device, each bond pad located proximate to, and extending along at least substantially the entirety of, the first side of the major surface of the first microelectronic device being in the first bond pad row;
an other bond pad row (122 on the bottom) located proximate to, and extending along at least substantially an entirety of, an other side of the first major surface of the first microelectronic device, the other side oriented perpendicular to the first side, each bond pad located proximate to, and extending along at least substantially the entirety of, the other side of the first major surface of the first microelectronic device being in the other bond pad row, a first pitch between bond pads of the first bond pad row being greater than an other pitch of bond pads of the other bond pad row; and
a second bond pad row (132 on the left) located proximate to, and extending along at least substantially an entirety of, a second side of a second major surface of a second microelectronic device (130) on which the first microelectronic device is positioned, the second side located opposite the first side;
wherein the first pitch of the bond pads of the first bond pad row is at least substantially equal to a second pitch of the bond pads of the second bond pad row;
wherein bond pads of the first bond pad row and bond pads of the second bond pad row are offset from one another in a direction parallel to the first and second bond pad rows by a pitch one-half of the first pitch between bond pads of the first bond pad row and of the second pitch between bond pads of the second bond pad row.
Regarding claim 12, figure 2B of Kang discloses an overhang distance of the first microelectronic device relative to the second microelectronic device is equal to two times an integer or zero plus one, multiplied by the first pitch of the bond pads of the first bond pad row, less a first offset between a fourth edge of the microelectronic device opposite the other bond pad row and a geometric center of a closest first bond pad, as measured in a direction parallel to a first shortest distance between adjacent bond pads of the first bond pad row, plus a second offset between the other side of the microelectronic device and a geometric center of a closest bond pad of the first bond pad row, as measured in the direction parallel to the first shortest distance.
Regarding claim 19, figure 2B of Kang discloses the second microelectronic device (130) is laterally and longitudinally offset from the microelectronic device (120).
Regarding claim 20, figure 2B of Kang discloses a fourth bond pad row (132 on top) located proximate to, and extending along at least substantially an entirety of, a fourth side of the first major surface of the first microelectronic device (120), the fourth side located opposite the other side; and wherein one or more of the bond pads of the other bond pad row is aligned with a corresponding one or more of the bond pads of the fourth bond pad row in a direction at least substantially parallel to a first shortest distance between adjacent first bond pads.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9 and 13-18 are rejected under 35 U.S.C. 103 as being unpatentable over Kang.
Regarding claim 9, Kang does not explicitly disclose at least some of the first bond pads are operably coupled to circuitry of the microelectronic device for connection to a reference voltage; and
at least some of the other bond pads are operably coupled to circuitry of the microelectronic device for connection to a data signal or clock channel.
However, reference voltages and data signal/clock channels are well known in the art and it would have been obvious to operably couple the first/other bond pads to such circuity to form a functioning memory device.
Regarding claim 13, Kang does not explicitly disclose an other stack of microelectronic devices, each of the stack of microelectronic devices and the other stack of microelectronic devices supported on a substrate, the other stack of microelectronic devices comprising:
a third microelectronic device comprising an other first bond pad row located proximate to an other first side of a major surface of the third microelectronic device; and
a fourth microelectronic device stacked above the third microelectronic device, the fourth microelectronic device comprising an other second bond pad row located proximate to an other second, opposite side of the other stack of microelectronic devices;
wherein a pitch between bond pads of the other first bond pad row is substantially equal to a pitch of the second bond pad row; and
wherein bond pads of the other first bond pad row and the other second bond pad row are offset from one another in a direction parallel to the other first and second bond pad rows by a pitch one-half of the pitch between bond pads of each of the first and second bond pad rows.
However, it would have been obvious to include the claimed third and fourth devices on the substrate in order to form a high density memory device and also since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8
Regarding claim 14, figure 2B of Kang discloses some of the bond pads of the first bond pad row of the first microelectronic device are interposed in the direction between bond pads of the other second bond pad row of the fourth microelectronic device; and
some of the bond pads of the second bond pad row of the second microelectronic device are interposed in the direction between corresponding bond pads of the other first bond pad row of the third microelectronic device.
Regarding claim 15, figures 2B and 8 of Kang discloses other first wire bonds (142) extending from bond pads of the other first bond pad row of the third microelectronic device in a first direction to lands of the substrate interposed between the second microelectronic device and the third microelectronic device; and
second wire bonds (144) extending from the bond pads of the second bond pad row of the second microelectronic device in a second, opposite direction to the first direction and to lands of the substrate interposed between the second microelectronic device and the third microelectronic device, the other first wire bonds alternating with the second wire bonds along the direction parallel to a first shortest distance between the adjacent bond pads of the first bond pad row.
Regarding claim 16, figure 2B of Kang discloses the first pitch of the bond pads of the first bond pad row of the microelectronic device is twice a pitch of the lands of the substrate.
Regarding claim 17, Kang does not explicitly disclose at least some of the bond pads of the first bond pad row, the other first bond pad row, the second bond pad row, and the other second bond pad row are operably coupled to circuitry of the first microelectronic device, the second microelectronic device, the third microelectronic device, or the fourth microelectronic device for connection to a reference voltage via the lands of the substrate interposed between the stack of microelectronic devices and the other stack of microelectronic devices.
However, reference voltages are well known in the art and it would have been obvious to operably couple the bond pads to such circuity to form a functioning memory device.
Regarding claim 18, figure 2B of Kang discloses a second shortest distance between adjacent pairs of bond pads of the second bond pad row of the microelectronic device is greater than a greatest width of each one of the lands, as measured in the direction parallel to the first shortest distance.
Conclusion
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/YU-HSI D SUN/ Primary Examiner, Art Unit 2817
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