Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 8-9, 11-13, 15, and 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wei et al. (US 20220139911 A1; hereinafter Wei).
Regarding Claim 1. Wei (Figs.1-4E) discloses a semiconductor device, comprising:
a source/drain feature (366; Fig.3I; [0089]) adjacent to a semiconductor layer stack (357, Fig.3B; [0063]) disposed over a substrate (350, Fig.3A, [0058]), the source/drain feature (366) and the semiconductor layer stack (357; Fig.3C) disposed along a first plane that extends in a first direction in a top down view;
a dielectric layer (364; Fig.3O; [0106]) adjacent to each of the source/drain feature (366) and the semiconductor layer stack (357) in a second direction in the top down view (Fig.3O), the second direction perpendicular to the first direction; and a source/drain contact (378, Fig.3P; [0108]) disposed between the source/drain feature (366) and the dielectric layer (364).
Regarding Claim 2. The semiconductor device of claim 1, Wei (364; Fig.3O; [0084]) discloses wherein the dielectric layer includes a low-K material, a high-K material, or a combination thereof.
Regarding Claim 3. The semiconductor device of claim 1, further comprising: Wei discloses a gate stack (371, Fig.3K; [0095]) disposed over the semiconductor layer stack (357) and over at least one dummy fin (the fin under dummy gate 361-1-, 361-2,
361-3, Fig.3C, [0068]) adjacent to the semiconductor layer stack (357), wherein the at least one dummy fin is disposed along a second plane in the top
down view, the second plane parallel to the first plane and extending in the first direction (Fig.3C).
Regarding Claim 4. The semiconductor device of claim 3, Wei (Fig.3C) discloses wherein the dummy fin (the fin under dummy gate 361-1-, 361-2, 361-3, Fig.3C, [0068]) interposes the source/drain feature (366 on left) disposed along the first
plane and another source/drain feature (366 on right) disposed along a third plane in the top down view, the third plane parallel to the first and second planes (Fig.3C).
Regarding Claim 5. The semiconductor device of claim 1, further comprising: a portion of a shallow trench isolation layer (362/352; Fig.3G; [0069]) in contact with a sidewall of the dielectric layer (364).
Regarding Claim 6. The semiconductor device of claim 3, further comprising: a cladding layer (362) interposing the at least one dummy fin (the fin under dummy gate 361-1-, 361-2, 361-3, Fig.3C) and the semiconductor layer stack.
Regarding Claim 8. The semiconductor device of claim 1, further comprising: Wei discloses a backside power rail (382, Fig.3S, [0111]) disposed beneath and in contact with the source/drain contact (378).
Regarding Claim 9. The semiconductor device of claim 8, Wei ([0111], [0046]) discloses wherein the backside power rail (382) includes a barrier layer and a metal fill layer.
Regarding Claim 11. Wei (Fig.3) discloses a semiconductor device, comprising:
a source/drain feature (366; Fig.3I) in contact with a plurality of semiconductor channel layers (357) along a first side of the source/drain feature (366), the first side of the
source/drain feature (366) facing a first direction in a top down view;
a dielectric layer (364; Fig.3O) adjacent to and the source/drain feature (366) along a second side of the source/drain feature (left side), the second side of the source/drain
feature facing a second direction perpendicular to the first direction in the top down view; and
a source/drain contact (378, Fig.3P) adjacent to the source/drain feature (366) along the second side of the source/drain feature (left side), the source/drain contact (378)
interposing the dielectric layer (364) and the source/drain feature (366), and the source/drain contact (378) electrically connected to the source/drain feature (366).
Regarding Claim 12. The semiconductor device of claim 11, Wei (Fig.3) discloses a backside power rail (382, Fig.3S) disposed beneath and in contact with the source/drain contact (378).
Regarding Claim 13. The semiconductor device of claim 12, Wei (Fig.3) discloses wherein the backside power rail (382) includes a barrier layer and a metal fill layer ([0111], [0046]).
Regarding Claim 15. Wei (Fig.3) discloses a semiconductor device, comprising: a source/drain feature (366, Fig,3I) disposed over a substrate (350, Fig.3A);
a dielectric layer (364, Fig.3O) disposed over the substrate (350) and adjacent to the source/drain feature (366);
a metal contact (378; Fig.3O) disposed over the substrate (350) and interposing the source/drain feature (366) and the dielectric layer (364); and
a power rail (382, Fig.3S) disposed within the substrate (350) and below the metal contact (378), wherein the power rail (382) physically contacts the metal contact (378).
Regarding Claim 17. The semiconductor device of claim 15, Wei (Fig.3) discloses a shallow trench isolation (362/352; Fig.3G) feature disposed below the source/drain feature (366) and adjacent the dielectric layer (364).
Regarding Claim 18. The semiconductor device of claim 15, Wei (Fig.3) discloses wherein the dielectric layer (364; [0083]) includes silicon.
Regarding Claim 19. The semiconductor device of claim 15, Wei (Fig.3) discloses wherein the metal contact (378; [0108]) is a source/drain contact.
Regarding Claim 20. The semiconductor device of claim 15, Wei (Fig.3) discloses wherein the backside power rail (382) includes a barrier layer and a metal fill layer ([0111], [0046]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Wei in view of Krishnan et al. (US 2018/0286982 A1; hereinafter Krishnan).
Regarding Claim 7. The semiconductor device of claim 6, Wei does not particularly disclose wherein the cladding layer includes silicon germanium.
Krishnan ([0032]) discloses in a related art a cladding layer including SiGe.
Therefore, it would have been obvious in the art before the effective filing of the application to use SiGe as a cladding layer to prevent ions likes boron to diffuse from outgassing from the doped fin structure into the spacer material ([0032]).
Claim(s) 10, 14, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Wei in view of Lilak et al. (US 2020/0294998 A1, hereinafter Lilak).
Regarding Claim 10. The semiconductor device of claim 1, Wei does not particularly disclose a silicide layer disposed between the source/drain feature and the source/drain contact.
Lilak (Fig.8A-B; [0056]) in a related art discloses forming a silicide layer over the source/drain features and forming the source/drain contact over the silicide layer.
Therefore, it would have been obvious in the art before the effective filing of the application to form a silicide layer over the exposed sidewall surface of the source/drain feature and depositing the source/drain contact over the silicide layer to make a better connection quality.
Regarding Claim 14. The semiconductor device of claim 11, Wei does not particularly disclose a silicide layer disposed between the source/drain feature and the source/drain contact.
Lilak (Fig.8A-B; [0056]) in a related art discloses forming a silicide layer over the source/drain features and forming the source/drain contact over the silicide layer.
Therefore, it would have been obvious in the art before the effective filing of the application to form a silicide layer over the exposed sidewall surface of the source/drain feature and depositing the source/drain contact over the silicide layer to make a better connection quality.
Regarding Claim 16. The semiconductor device of claim 15, Wei does not particularly disclose a silicide layer disposed along a sidewall of the source/drain feature, physically contacting the source/drain feature, wherein the silicide layer extends from the source/drain feature to the metal contact.
Lilak (Fig.8A-B; [0056]) in a related art discloses forming a silicide layer disposed along a sidewall of the source/drain feature, physically contacting the source/drain feature, wherein the silicide layer extends from the source/drain feature to the metal contact.
Therefore, it would have been obvious in the art before the effective filing of the application to form a silicide layer over the exposed sidewall surface of the source/drain feature and depositing the source/drain contact over the silicide layer to make a better connection quality.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAJAR KOLAHDOUZAN whose telephone number is (571)270-5842.
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/HAJAR KOLAHDOUZAN/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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