DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 2 in the reply filed on 7/15/26 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 12-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Cheng et al (US 2023/0026676).
12. A method comprising:
forming a first set of devices (Fig.2 (228) and [0034]) of a first integrated circuit (Fig.2 (108) and [0034]);
forming a first set of internal connections (Fig.2 (206d) and [0034]) of the first integrated circuit (Fig.2 (108) and [0034]) that are coupled to the first set of devices (Fig.2 (228) and [0034]) of the first integrated circuit (Fig.2 (108) and [0034]);
selecting a first set of masks from a library of sets of masks based at least in part on a first set of external connections (Fig.2 (210d pad and bump) and [0034]/see also[0102-0104-note solder masks sizing based upon bump size];
forming a first set of metal wiring layers (Fig.2 (214d/210d pad) and [100]) of the first integrated circuit (Fig.2 (108) and [0034]) using the first set of masks (Fig.2 (210d pad and bump) and [0034]/see also [0102-0104-note solder masks sizing based upon bump size];
forming a second set of devices (Fig.2 (218) and [0032]) of a second integrated circuit (Fig.2 (104) and [0032]), wherein the second set of devices (Fig.2 (218) and [0032]) is in a same configuration (Fig.2 (218/228) as a configuration of the first set of devices (Fig.2 (228) and [0034]);
forming a second set of internal connections (Fig.2 (206b) and [0032]) of the second integrated circuit (Fig.2 (104) and [0032]) that are coupled to the second set of devices (Fig.2 (218) and [0032]) of the second integrated circuit (Fig.2 (104) and [0032]);
selecting a second set of masks from the library of sets of masks based at least in part on a second set of external connections (Fig.2 (210b pad and bump) and [0032]/see also[0102-0104-note solder masks sizing based upon bump size], wherein the second set of masks is different than the first set of masks [0102-0104-note solder masks sizing based upon bump size] and the second set of external connections (Fig.2 (210b pad and bump) and [0032]) has a different configuration than a configuration of the first set of external connections (Fig.2 (210d pad and bump) and [0034]); and
forming a second set of metal wiring layers (Fig.2 (214b) and [0032]) of the second integrated circuit (Fig.2 (104) and [0032]) using the second set of masks [0102-0104-note solder masks sizing based upon bump size], wherein the second integrated circuit (Fig.2 (104) and [0032]) has a configuration that is different than a configuration of the first set of metal wiring layers (Fig.2 (214d/210d pad) and [100]).
13. The method of claim 12, further comprising: coupling the first set of external connections (Fig.2 (210d pad and bump) and [0034] ) of the first integrated circuit (Fig.2 (108) and [0034]) to the first set of internal connections (Fig.2 (206d) and [0034]) via the first set of metal wiring layers (Fig.2 (214d/210d pad) and [100]); and coupling the second set of external connections (Fig.2 (210b pad and bump) and [0032]) of the second integrated circuit (Fig.2 (104) and [0032]) to the second set of internal connections (Fig.2 (206b) and [0032])via the second set of metal wiring layers (Fig.2 (214b) and [0032]).
14. The method of claim 13, wherein forming the first set of metal wiring layers (Fig.2 (214d/210d pad) and [100]) comprises leaving a subset of the first set of internal connections (Fig.2 (206d) and [0034]) uncoupled from the first set of external connections (Fig.2 (210d pad and bump) and [0034] ) in a first metal wiring configuration (Fig.2 (214d/210d pad) and [100]).
15. The method of claim 14, wherein forming the second set of metal wiring layers (Fig.2 (214b) and [0032]) comprises leaving a subset of the second set of internal connections (Fig.2 (206b) and [0032]) uncoupled from the second set of external connections (Fig.2 (210b pad and bump) and [0032]) in a second metal wiring configuration (Fig.2 (214b) and [0032]), a quantity of the subset of the first set of internal connections (Fig.2 (206d) and [0034]) uncoupled from the first set of external connections (Fig.2 (210d pad and bump) and [0034] ) being different than a quantity of the subset of the second set of internal connections (Fig.2 (206b) and [0032]) uncoupled from the second set of external connections (Fig.2 (210b pad and bump) and [0032]).
16. The method of claim 12, wherein: the first set of external connections (Fig.2 (210d pad and bump) and [0034] ) is associated with a first package (Fig.1 (108)); and the second set of external connections (Fig.2 (210b pad and bump) and [0032]) is associated with a second package (Fig.1 (104)).
17. The method of claim 16, wherein: the first package (Fig.1 (108)) is different than the second package (Fig.1 (104)).
18. The method of claim 12, wherein: the first set of external connections (Fig.2 (210d pad and bump) and [0034] ) are one of solder balls, bumps, pillars, leads; and the second set of external connections (Fig.2 (210b pad and bump) and [0032]) are one of solder balls, bumps, pillars, leads.
19. The method of claim 12, wherein: the first (Fig.2 (108) and [0034]) and second integrated circuits (Fig.2 (104) and [0032- chiplets]) are chiplets; and the first and second sets of devices (Fig.2 (228/218) and [0034/0032- transistors]) are transistors.
20. The method of claim 12, wherein: the first set of internal connections (Fig.2 (206d) and [0034]) are associated with a first pitch(Fig.2 (206d) and [0034]), the second set of internal connections (Fig.2 (206b) and [0032]) are associated with a second pitch (Fig.2 (206b) and [0032]), the first set of external connections (Fig.2 (210d pad and bump) and [0034]) are associated with a third pitch, and the second set of external connections (Fig.2 (210b pad and bump) and [0032]) are associated with a fourth pitch (Fig.2 (210b pad and bump) and [0032]); the first pitch (Fig.2 (206d) and [0034]) is different than the third pitch (Fig.2 (210d pad and bump) and [0034]); the second pitch (Fig.2 (206b) and [0032]) is different than the fourth pitch (Fig.2 (210b pad and bump) and [0032]); and the third pitch (Fig.2 (210d pad and bump) and [0034]) is different than the fourth pitch (Fig.2 (210b pad and bump) and [0032]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Wang et al (US 9099999); Chen et al (US 20070145367) and Martorelli et al (US 11233002) teach similar IC package structures having devices with internal and external directions.
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/LAURA M MENZ/Primary Examiner, Art Unit 2813
7/25/26
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