DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) filed on July 23, 2024 has been considered by the examiner.
Claim Objections
Claims 7, 9 and 11 are objected to because of the following informalities:
Claims 7 and 9, appear to recite what the Examiner assumes is a typographical error. In claims 7 and 9, the phrase “the first image having a positon of the conductive pad” should read “the first image having a position of the conductive pad”.
Claim 11, appears to recite what the Examiner assumes is a typographical error. In claim 11, the phrase “the semiconductor die is shifted form a first position over” should read “the semiconductor die is shifted from a first position over”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-5, 8, 10-15, and 17-20, are rejected under 35 U.S.C. 103 as being unpatentable over Scanlan (US 20160086825 A1), hereinafter Scanlan825, in view of Scanlan (US 20190139901 A1), hereinafter Scanlan901.
Claim 1, Scanlan825 discloses a shift control method in manufacture of semiconductor device (Fan-Out-Wafer-Level-Package FOWLP 428, [0159], Fig. 19), comprising:
conductive connector (copper pillar 348, hereinafter conductive connector 348, Fig. 19) of a semiconductor die (semiconductor die 334, Fig. 19) and a conductive pad (contact pad 342, hereinafter conductive pad 342, Fig. 19) of the semiconductor die 334;
placing the semiconductor die 334 over a carrier (semiconductor die 334 mounted face down/up to carrier 360, [0129/0132], Fig. 13A/13B); and
forming a lithographic pattern on the conductive connector 348 of the semiconductor die 334 (adaptive patterning is performed with a lithography machine on interconnects 356, [0139]; conductive connector 348, may be formed directly on conductive pad 342, instead of on conductive layer 354 and interconnects 356, [0159]).
Scanlan825 does not explicitly disclose a shift control method in manufacture of semiconductor device 428, comprising:
calculating a difference of a relative position between a conductive connector 348 of a semiconductor die 334, and a conductive pad 342 of the semiconductor die 334 relative to a reference mark on the semiconductor die 334; and
the difference being compensated when placing the semiconductor die 334 over the carrier 360.
However, Scanlan901 teaches a shift control method in manufacture a semiconductor device, comprising:
calculating a difference of a relative position (radial shift Rm, [0078], Fig. 4A) between a conductive connector of a semiconductor die (via 288 of semiconductor die 334, [0092], Fig. 3K), and a conductive pad of the semiconductor die (electrical interconnect 356 of semiconductor die 334, [0092], Fig. 3K) relative to a reference mark (limiting feature 420, hereinafter reference mark 420, [0077], Fig. 4A) on the semiconductor die (total radial shift is calculated between layers a and b which contain the electrical interconnect 356 and the via 288 respectively, [0081], Fig. 5A); and
the difference being compensated when placing the semiconductor die 334 over the carrier 360. (compensation or arrangement can be made for misalignment of multiple semiconductor die 334, [0090]).
As taught in Scanlan901 in [0060], the total radial shift of individual semiconductor die may be distributed over multiple layers of an interconnect structure to reduce the number of misalignment-related defects such as faulty and missing electrical connections. Therefore, compensating at least a portion of that radial shift by applying it when the semiconductor die are being placed on the carrier would reduce the number of potential defects and layers needed to distribute the total radial shift and compensate for the remaining misalignment.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by Scanlan825 by compensating at least a portion of that radial shift by applying it when the semiconductor die are being placed on the carrier to reduce the number of potential defects and layers needed to distribute the total radial shift and compensate for the remaining misalignment.
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Figure 19 from Scanlan825
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Figure 13A from Scanlan825
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Figure 13B from Scanlan825
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Figure 4A from Scanlan901
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Figure 3K from Scanlan901
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Figure 5A from Scanlan901
Claim 2, the combination of Scanlan825 and Scanlan901 teaches the shift control method of claim 1.
Scanlan825 further discloses the shift control method of claim 1, further comprising:
forming an insulating encapsulation (encapsulant 366, hereinafter insulating encapsulation 366, [0131], Fig. 13A) on the carrier 360 to cover the semiconductor die 334 (insulating encapsulation 366 is injected into cavity 374 and over semiconductor die 334 and carrier 360, [0131], Fig. 13A), wherein the semiconductor die 334 is shifted after forming the insulating encapsulation 366 (movement of semiconductor die 334 also results from shifts in the position of the semiconductor die, which occur during encapsulation, [0138]); and
measuring a shift of the semiconductor die 334 (the measured position of semiconductor die 334 includes an x-y position that accounts for a shift of the semiconductor die 334, [0137]).
Claim 3, the combination of Scanlan825 and Scanlan901 teaches the shift control method of claim 2.
Scanlan825 further discloses the shift control method of claim 2, further comprising:
performing a shifting feedback correction in response to the shift of the semiconductor die 334 when forming the lithographic pattern (position data for semiconductor die 334 and interconnects 356 are imported into an adaptive pattern auto-router, which accounts for the true or measured positions of semiconductor die 334 and produces a new design that adjusts or selects new locations for at least a portion of the fan-out build-up interconnect structure, to connect to interconnects 356 of semiconductor die 334, [0139]; conductive connector 348, may be formed directly on conductive pad 342, instead of on conductive layer 354 and interconnects 356, [0159]).
Claim 4, the combination of Scanlan825 and Scanlan901 teaches the shift control method of claim 2.
Scanlan825 further discloses the shift control method of claim 2, wherein measuring the shift of the semiconductor die 334 comprises:
setting a reference point over the carrier 360 (fiducial alignment marks 364 are positioned over carrier 360, [0128], Fig. 13A/13B); and
determining a relative displacement between the semiconductor die 334 relative to the reference point (semiconductor die 334 are positioned with respect to fiducial 364 according to a nominal or predetermined position, [0129]).
Claim 5, the combination of Scanlan825 and Scanlan901 teaches the shift control method of claim 2.
Scanlan825 further discloses the shift control method of claim 2, further comprising:
releasing the carrier 360 (carrier 360 is removed, [0136]); and
performing a singulation process to cut through the insulating encapsulation 366 (a singulation process is performed with a cutting tool 398 to obtain individual FOWLPs and therefore cut through insulating encapsulation 366, [0153], Fig. 13H).
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Figure 13H from Scanlan825
Claim 8, Scanlan825 discloses a shift control method in manufacture of semiconductor device (Fan-Out-Wafer-Level-Package FOWLP 428, [0159], Fig. 19), comprising:
conductive connector (copper pillar 348, hereinafter conductive connector 348, Fig. 19) of a semiconductor die (semiconductor die 334, Fig. 19) and a conductive pad (contact pad 342, hereinafter conductive pad 342, Fig. 19) of the semiconductor die 334;
placing the semiconductor die 334 over a carrier (semiconductor die 334 mounted face down/up to carrier 360, [0129/0132], Fig. 13A/13B);
forming an insulating encapsulation (encapsulant 366, hereinafter insulating encapsulation 366, [0131], Fig. 13A) on the carrier 360 to cover the semiconductor die 334 (insulating encapsulation 366 is injected into cavity 374 and over semiconductor die 334 and carrier 360, [0131], Fig. 13A); and
forming a redistribution structure (RDL 390, hereinafter redistribution structure 390, [0143], Fig. 13E) on the insulating encapsulation 366 and the semiconductor die 334 (redistribution structure 390 is patterned and deposited over insulating layer 388 and therefore over insulating encapsulation 366, [0143], Fig. 13E).
Scanlan825 does not explicitly disclose a shift control method in manufacture of semiconductor device 428, comprising:
measuring a degree of offset between a conductive connector 348 of a semiconductor die 334 and a conductive pad 342 of the semiconductor die 334 in a dimensional direction; and
placing the semiconductor die 334 over a carrier 360 at a position to compensate for the degree of offset.
However, Scanlan901 teaches a shift control method in manufacture of a semiconductor device comprising:
measuring a degree of offset (radial shift Rm, [0078], Fig. 4A) between a conductive connector 348 of a semiconductor die 334 (via 288 of semiconductor die 334, [0092], Fig. 3K) and a conductive pad 342 of the semiconductor die 334 (electrical interconnect 356 of semiconductor die 334, [0092], Fig. 3K) in a dimensional direction (dimensional directions x and y comprising Rm are labeled in Fig. 4A; Rm can be measured, [0078]); and
compensating for the degree of offset of semiconductor die 334 over a carrier 360 (compensation or arrangement can be made for misalignment of multiple semiconductor die 334, [0090]).
As taught in Scanlan901 in [0060], the total radial shift of individual semiconductor die may be distributed over multiple layers of an interconnect structure to reduce the number of misalignment-related defects such as faulty and missing electrical connections. Therefore, compensating at least a portion of that radial shift by applying it when the semiconductor die are being placed on the carrier would reduce the number of potential defects and layers needed to distribute the total radial shift and compensate for the remaining misalignment.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by Scanlan825 by compensating at least a portion of that radial shift by applying it when the semiconductor die are being placed on the carrier to reduce the number of potential defects and layers needed to distribute the total radial shift and compensate for the remaining misalignment.
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Figure 13E from Scanlan825
Claim 10, the combination of Scanlan825 and Scanlan901 teaches the shift control method of claim 8.
Scanlan825 further discloses the shift control method of claim 8, wherein forming the insulating encapsulation 366 on the carrier 360 comprises:
forming an insulating material (insulating encapsulation 366) on the carrier 360 to embed the semiconductor die 334 therein (semiconductor die 334 are embedded together in insulating encapsulation 366 which is non-conductive, [0131]);
curing the insulating material (insulating encapsulation 366, which can be a polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler, is evenly dispersed and uniformly distributed under an elevated temperature, [0131]);
performing a planarization process on the insulating material until the conductive connector 348 of the semiconductor die 334 is exposed (a chemical etch can also be used to remove and planarize a portion of encapsulant 366 and therefore expose a surface of interconnects 356, [0134], Fig. 13C; conductive connector 348, may be formed directly on conductive pad 342, instead of on conductive layer 354 and interconnects 356, [0159]).
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Figure 13C from Scanlan825
Claim 11, the combination of Scanlan825 and Scanlan901 teaches the shift control method of claim 10.
Scanlan825 further discloses the shift control method of claim 10, wherein after curing the insulating material, the semiconductor die 334 is shifted form a first position over the carrier 360 to a second position over the carrier 360 (movement of semiconductor die 334 also results from shifts in the position of the semiconductor die, which occur during encapsulation, [0138]; curing occurs while the semiconductor die 334 is on the carrier 360, [0131], Fig. 13A).
Claim 12, the combination of Scanlan825 and Scanlan901 teaches the shift control method of claim 11.
Scanlan825 further discloses the shift control method of claim 11, further comprising:
measuring a shift between the first position and the second position to result in a measuring result before forming the redistribution structure 390. (the measured position of semiconductor die 334 includes an x-y position that accounts for a shift of the semiconductor die 334, [0137]).
Claim 13, the combination of Scanlan825 and Scanlan901 teaches the shift control method of claim 11.
Scanlan825 further discloses the shift control method of claim 11, wherein forming the redistribution structure 390 on the insulating encapsulation 366 and the semiconductor die 334 comprises:
compensating for a shift of the semiconductor die 334 by adjusting a lithographic tool (position data for semiconductor die 334 and interconnects 356 are imported into an adaptive pattern auto-router, which accounts for the true or measured positions of semiconductor die 334 and produces a new design that adjusts or selects new locations for at least a portion of the fan-out build-up interconnect structure, to connect to interconnects 356 of semiconductor die 334, [0139]; a lithography machine is used for adaptive patterning, [0139]; conductive connector 348, may be formed directly on conductive pad 342, instead of on conductive layer 354 and interconnects 356, [0159]).
Claim 14, the combination of Scanlan825 and Scanlan901 teaches the shift control method of claim 8.
Scanlan825 further discloses the shift control method of claim 8, further comprising:
performing a singulation process to dice the redistribution structure 390 and the insulating encapsulation 366 (a singulation process is performed to obtain individual FOWLPs, [0153]).
Claim 15, Scanlan825 discloses a shift control method in manufacture of semiconductor device (Fan-Out-Wafer-Level-Package FOWLP 428, [0159], Fig. 19), comprising:
providing a semiconductor wafer (semiconductor wafer 330, [0123], Annotated Fig. 12B), wherein the semiconductor wafer 330 comprises die regions (die regions in Annotated Fig. 12B), and each of the die regions comprises a conductive pad (conductive layer 342, hereinafter conductive pad 342, is comprised of conductive pads, [0124], Annotated Fig. 12B) and a conductive connector (copper pillars 348, hereinafter conductive connector 348, Annotated Fig. 12B) on the conductive pad 342 (conductive connector 348 on conductive pad 342, [0124], Annotated Fig. 12B);
performing a singulation process to dice the die regions after measuring the offset to form semiconductor dies 334 (a singulation process is performed with a cutting tool 398 to obtain individual FOWLPs and therefore cut through insulating encapsulation 366, [0153], Fig. 13H);
placing the semiconductor dies 334 over a carrier (semiconductor die 334 mounted face down/up to carrier 360, [0129/0132], Fig. 13A/13B); and
forming a redistribution structure (RDL 390, hereinafter redistribution structure 390, [0143], Fig. 13E) over the semiconductor die 334 (redistribution structure 390 is patterned and deposited over insulating layer 388 and therefore over semiconductor die 334, [0143], Fig. 13E).
Scanlan825 does not explicitly disclose a shift control method in manufacture of semiconductor device 428, comprising:
measuring an offset between the conductive connector 348 and the conductive pad 342; and
placing the semiconductor dies 334 over a carrier 360 to compensate the offset.
However, Scanlan901 teaches a shift control method in manufacture of a semiconductor device, comprising:
measuring an offset (radial shift Rm, [0078], Fig. 4A) between a conductive connector 348 (via 288 of semiconductor die 334, [0092], Fig. 3K) and a conductive pad 342 (electrical interconnect 356 of semiconductor die 334, [0092], Fig. 3K; Rm can be measured, [0078]);
compensating for the degree of offset of semiconductor die 334 over a carrier 360 (compensation or arrangement can be made for misalignment of multiple semiconductor die 334, [0090]).
As taught in Scanlan901 in [0060], the total radial shift of individual semiconductor die may be distributed over multiple layers of an interconnect structure to reduce the number of misalignment-related defects such as faulty and missing electrical connections. Therefore, compensating at least a portion of that radial shift by applying it when the semiconductor die are being placed on the carrier would reduce the number of potential defects and layers needed to distribute the total radial shift and compensate for the remaining misalignment.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention disclosed by Scanlan825 by compensating at least a portion of that radial shift by applying it when the semiconductor die are being placed on the carrier to reduce the number of potential defects and layers needed to distribute the total radial shift and compensate for the remaining misalignment.
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Annotated Figure 12B from Scanlan825
Claim 17, the combination of Scanlan825 and Scanlan901 teaches the shift control method of claim 15.
Scanlan825 further discloses the shift control method of claim 15, further comprising:
forming an insulating encapsulation (encapsulant 366, hereinafter insulating encapsulation 366, [0131], Fig. 13A) on the carrier 360 to cover the semiconductor dies 334 before forming the redistribution structure 390 (insulating encapsulation 366 is injected into cavity 374 and over semiconductor die 334 and carrier 360, [0131], Fig. 13A).
Claim 18, the combination of Scanlan825 and Scanlan901 teaches the shift control method of claim 17.
Scanlan825 further discloses the shift control method of claim 17, wherein at least a portion of the semiconductor dies 334 is shifted after forming the insulating encapsulation 366 (movement of semiconductor die 334 also results from shifts in the position of the semiconductor die, which occur during encapsulation, [0138]).
Claim 19, the combination of Scanlan825 and Scanlan901 teaches the shift control method of claim 18.
Scanlan825 further discloses the shift control method of claim 18, further comprising:
setting one of the semiconductor dies 334 as a reference point (point of reference R6, [0129], Fig. 13A); and
determining a relative displacement of the semiconductor dies 334 relative to the reference point (semiconductor die 334 are separated by a space or gap represented by the displacement between R6 and R7 when mounted over carrier 360 and therefore have a displacement that was determined to be between them, [0129], Fig. 13A).
Claim 20, the combination of Scanlan825 and Scanlan901 teaches the shift control method of claim 18.
Scanlan825 further discloses the shift control method of claim 18, wherein forming the redistribution structure 390 comprises:
compensating shifts of the portion of the semiconductor dies 334 when forming the redistribution structure 390 (position data for semiconductor die 334 and interconnects 356 are imported into an adaptive pattern auto-router, which accounts for the true or measured positions of semiconductor die 334 and produces a new design that adjusts or selects new locations for at least a portion of the fan-out build-up interconnect structure, to connect to interconnects 356 of semiconductor die 334, [0139]; conductive connector 348, may be formed directly on conductive pad 342, instead of on conductive layer 354 and interconnects 356, [0159]).
Claims 6-7, 9, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Scanlan825 in view of Scanlan901 further in view of Raaijmakers (US 20030231950 A1).
Claim 6, the combination of Scanlan825 and Scanlan901 teaches the shift control method of claim 1, further comprising:
providing a semiconductor wafer (Scanlan825, semiconductor wafer 330, [0123], Annotated Fig. 12B), wherein the semiconductor wafer 330 comprises a die region (Scanlan825, die regions in Annotated Fig. 12B) comprising the conductive pad 342 and the conductive connector 348 (Scanlan825, each of the die regions comprise of a conductive pad 342 and a conductive connector 348, Annotated Fig. 12B); and
performing a singulation process on the semiconductor wafer 330 to form the semiconductor die 334 (Scanlan825, semiconductor wafer 330 is singulated into individual semiconductor die 334, [0125]).
The combination of Scanlan825 and Scanlan901 does not explicitly teach the shift control method of claim 1, further comprising:
scanning the semiconductor wafer 330 to obtain the relative position between the conductive pad 342 and the conductive connector 348.
However, Raaijmakers teaches a shift control method comprising:
scanning a wafer (obtaining a first image [0052] and a second image [0053] of wafer 210) to obtain the relative position between the nominal position and the shifted position of the wafer in order to properly position the wafer during robotic transfer ([0014]).
As taught in Raaijmakers, obtaining the relative position with this method only requires a minimal number of independent variables which are all easy to measure accurately and therefore produce a more accurate relative position, and does not require complicated calibration ([0093]). In addition, this methodology can be directly applied to overlapping features such as the conductive connector and the conductive pad since that would only involve substituting substrate features with semiconductor die features while applying this same imaging methodology to obtain the relative position. Therefore, the method disclosed can be used to obtain the relative position between the conductive pad 342 (nominal position) and the conductive connector 348 (shifted position).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention taught by the combination of Scanlan825 and Scanlan901 by obtaining the relative position between the conductive pad and conductive connector using the imaging methodology taught by Raaijmakers to arrive at the claimed invention.
Claim 7, the combination of Scanlan825, Scanlan901, and Raaijmakers teaches the shift control method of claim 6, wherein after scanning the semiconductor wafer 330 (Scanlan825, semiconductor wafer 330, [0123], Annotated Fig. 12B; Raaijmakers, wafer 210, [0052]), a first image (Raaijmakers, first image of wafer 210 is obtained, [0052], Fig. 6A) and a second image (Raaijmakers, second image of wafer 210 is obtained, [0053], Fig. 6B) of the semiconductor wafer 330 are obtained, and calculating the difference of the relative position (Raaijmakers, the difference of the relative position between the centered wafer in Fig. 6A and the off-centered wafer in Fig. 6B, [0061]) between the conductive pad 342 (Scanlan825, conductive pad 342, Fig. 19; Raaijmakers, centered wafer, [0061], Fig. 6A) and the conductive connector 348 (Scanlan825, conductive connector 348, Fig. 19; Raaijmakers, off-centered wafer, [0061], Fig. 6B) comprises:
comparing the first image having a position of the conductive pad 342 (Raaijmakers , first image having the centered wafer position, Fig. 6A) and the second image having a position of the conductive connector 348, (Raaijmakers , second image having the off-centered wafer position, Fig. 6B) wherein the first image and the second image are aligned (Raaijmakers, the wafer center is at the intersection of these two circles [0064] depicted in figures 6A and 6B [0062] wherein each figure contains the reference point (0,0) and are therefore aligned) by using the reference mark 420 (Scanlan901, limiting feature 420, hereinafter reference mark 420, [0077], Fig. 4A; Raaijmakers, each image contains reference point (0,0), [0061], Figs. 6A/6B).
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Figure 6A from Raaijmakers
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Figure 6B from Raaijmakers
Claim 9, the combination of Scanlan825 and Scanlan901 teaches the shift control method of claim 8.
The combination of Scanlan825 and Scanlan901 does not explicitly teach the shift control method of claim 8, wherein measuring the degree of offset between the conductive connector 348 and the conductive pad 342 comprises:
scanning the semiconductor die 334 to obtain a first image of the semiconductor die 334 and a second image of the semiconductor die 334; and
comparing the first image having a position of the conductive pad 342 and the second image having a position of the conductive connector 348, wherein the first image and the second image are aligned by using a reference mark of the semiconductor die 334.
However, Raaijmakers teaches a shift control method, wherein measuring a degree of offset between a shifted position and a nominal position comprises:
scanning a wafer (wafer 210, [0061]) to obtain a first image of the wafer (first image of wafer 210 is obtained, [0052], Fig. 6A) and a second image of the wafer (second image of wafer 210 is obtained, [0053], Fig. 6B); and
comparing the first image having a position of the nominal position (first image having the centered wafer position, Fig. 6A) and the second image having a position of the shifted position (second image having the off-centered wafer position, Fig. 6B), wherein the first image and the second image are aligned by using a reference mark of the wafer (the wafer center is at the intersection of these two circles [0064] depicted in figures 6A and 6B [0062] wherein each figure contains the reference point (0,0) and are therefore aligned).
As taught in Raaijmakers, obtaining the relative position with this method only requires a minimal number of independent variables which are all easy to measure accurately and therefore produce a more accurate relative position, and does not require complicated calibration ([0093]). In addition, this methodology can be directly applied to overlapping features such as the conductive connector and the conductive pad since that would only involve substituting substrate features with semiconductor die features while applying this same imaging methodology to obtain the relative position. Therefore, the method disclosed can be used to obtain the relative position between the conductive pad 342 (nominal position) and the conductive connector 348 (shifted position).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention taught by the combination of Scanlan825 and Scanlan901 by obtaining the relative position between the conductive pad and conductive connector using the imaging methodology taught by Raaijmakers to arrive at the claimed invention.
Claim 16, the combination of Scanlan825 and Scanlan901 teaches the shift control method of claim 15.
The combination of Scanlan825 and Scanlan901 does not explicitly teach the shift control method of claim 15 wherein measuring the offset between the conductive connector 348 and the conductive pad 342 comprises:
capturing a first image of the semiconductor die 334 having a position of the conductive connector 348 and a second image of the semiconductor die 334 having a position of the conductive pad 342;
aligning the first image with the second image; and
calculating a difference of a relative position between the conductive connector 348 and the conductive pad 342.
However, Raaijmakers teaches a shift control method wherein measuring an offset between a shifted position and a nominal position comprises:
capturing a first image of a wafer (wafer 210, [0061]) having a position of the shifted position (first image having the centered wafer position, Fig. 6A) and a second image of the wafer having a position of the nominal position (second image having the off-centered wafer position, Fig. 6B);
aligning the first image with the second image (the wafer center is at the intersection of these two circles [0064] depicted in figures 6A and 6B [0062] wherein each figure contains the reference point (0,0) and are therefore aligned); and
calculating a difference of a relative position between the shifted position and the nominal position (the difference of the relative position between the centered wafer in Fig. 6A and the off-centered wafer in Fig. 6B, [0061]).
As taught in Raaijmakers, obtaining the relative position with this method only requires a minimal number of independent variables which are all easy to measure accurately and therefore produce a more accurate relative position, and does not require complicated calibration ([0093]). In addition, this methodology can be directly applied to overlapping features such as the conductive connector and the conductive pad since that would only involve substituting substrate features with semiconductor die features while applying this same imaging methodology to obtain the relative position. Therefore, the method disclosed can be used to obtain the relative position between the conductive pad 342 (nominal position) and the conductive connector 348 (shifted position).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention taught by the combination of Scanlan825 and Scanlan901 by obtaining the relative position between the conductive pad and conductive connector using the imaging methodology taught by Raaijmakers to arrive at the claimed invention.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Coots (US 20200301404 A1) discloses a method for picking and placing semiconductor dies on a wafer that compensates for stochastic shifts during a placement process by collecting and storing shift measurements from prior die placements and using that data to fit mathematical models that predict future shift values to reduce misalignment and defect rates in integrated circuit packaging.
Scanlan (US 20130280826 A1) and Bishop (US 20180082911 A1) both disclose methods for compensating for shifts that occur during die placement by distributing total translational and radial shift across multiple interconnect layers formed with adaptive patterning methods.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL M VANYO whose telephone number is (571)270-3088. The examiner can normally be reached 9am-12pm, 1pm-4pm EST Monday-Friday.
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/MICHAEL M VANYO/Examiner, Art Unit 2812
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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