DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Allowable Subject Matter
Claims 2-3, 13-14, and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 2, 13, and 18, prior art fails to teach or suggest an intermediate contact pattern below the gate structure laterally adjoining the S/D contacts to the channel layer wherein the intermediate contact pattern comprises a different 2D material than the 2D material of the channel layer. Emphasis on the underlined portion.
References used in the rejection below include 2D material layers underlying either the gate or the S/D contacts, or both, however, none teach or suggest using two different 2D materials on the same layer where the channel is one 2D material and the intermediate contact pattern laterally surrounding the channel is a different 2D material.
One reference found in the search, Pritchard (US 20210057558 A1), cited below, discloses using several layers under the gate in Fig 8, and several under the S/D contacts in Fig 14. Pritchard teaches various combinations of these two embodiments wherein 2D layers could reside under the S/D contacts, or could extend from source to drain fully under the gate (spanning across the entire active region (Pritchard, [0024]). However, these 2D layers are above the channel layer. In fact, Pritchard teaches away from including the 2D materials as the channel layer, reciting, "the channel region is free of any 2D materials." (Pritchard, [0042]).
As such, Pritchard cannot be combined in the rejection to meet the limitations of claims 2, 13, and 18. No other prior art teaches or suggests an intermediate contact pattern that laterally surrounds the channel and is comprised of a second, different, 2D material than that of the channel.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4, 10-12, 15, 17, and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yeh (US 20180012962 A1).
Regarding claim 1, Yeh teaches a transistor (400B, Fig 6B), comprising:
a gate structure (410);
a spacer (606) laterally surrounding (shown surrounding) the gate structure (410);
a channel layer (404) underlying (shown under) the gate structure (410) and comprising a two-dimensional (2D) material (2D material, [0024]); and
a source/drain (S/D) contact (412) laterally separated (shown laterally separated) from the gate structure (410) by the spacer (606) and laterally coupled (shown laterally coupled) to the channel layer (404).
Regarding claim 4, Yeh teaches the transistor of claim 1 and goes on to teach wherein the channel layer (404, Fig 6B) comprises a first portion (404A: portion of 404 directly under gate 410 corresponding to thickness t1) and a second portion (404B: portion of 404 between gate 410 and S/D contact 412 corresponding to thickness t2) connected (shown connected) to the first portion (404A), and
the first portion (404A) underlying (shown under) the gate structure (410) has a first thickness (t1) less (shown less) than a second thickness (t2) of the second portion (404B) below (shown below) the spacer (606).
Regarding claim 10, Yeh teaches a semiconductor structure (MOSFET, [0001]), comprising:
a semiconductor substrate (402, Fig 6B);
a transistor (400B) disposed over (shown over) the semiconductor substrate (402) and comprising:
a gate structure (410);
a channel layer (404) underlying (shown under) the gate structure (410) and comprising a first 2D material (2D material, [0024]);
a S/D contact (412) laterally coupled (shown laterally coupled) to the channel layer (404); and
a bottom dielectric layer (616) overlying (shown over) the semiconductor substrate (402) and separating (shown separating) the channel layer (404) from the semiconductor substrate (402).
Regarding claim 11, Yeh teaches the structure of claim 10 and goes on to teach wherein a bottom surface (602B: bottom of 602, Fig 6B) of the gate structure (410) is substantially planar (shown substantially planar) and is in direct contact (shown in direct contact) with the channel layer (404).
Regarding claim 12, Yeh teaches the structure of claim 10 and goes on to teach an interconnect structure (IC: layers 502 and 614, Fig 6B) disposed over (shown over) the semiconductor substrate (402),
a dielectric layer (614) of the interconnect structure (IC) covering (shown covering) the transistor (400B), and
a metallization pattern (502) of the interconnect structure (IC) being electrically coupled (shown electrically coupled) to the transistor (400B).
Regarding claim 15, Yeh teaches the structure of claim 10 and goes on to teach wherein the channel layer (404, Fig 6B) is connected (shown connected) to a bottom surface (602B: bottom of 602) of the gate structure (410) and laterally surrounds (shown laterally surrounding) a lower sidewall (602W: outer sidewall of 602) of the gate structure (410) connected (shown connected) to the bottom surface (602B).
Regarding claim 17, Yeh teaches A semiconductor device (MOSFET, [0001]), comprising:
a gate structure (410, Fig 6B);
a S/D contact (412) laterally spaced apart (shown laterally spaced apart) from the gate structure (410);
a channel layer (404A: portion of 404 directly under gate electrode 604) underlying (shown under) an inner portion (604) of the gate structure (410); and
an intermediate contact pattern (404B: portion of 404 outside of 404A) underlying (shown under) an outer portion (602) of the gate structure (410) and laterally encircling (shown encircling) the channel layer (404A),
wherein the intermediate contact pattern (404B) is laterally connected (shown laterally connected) to the S/D contact (412) and comprises a first 2D material (2D material, [0024]).
Regarding claim 19, Yeh teaches the device of claim 17 and goes on to teach wherein a maximum lateral dimension (as defined above, the channel layer 404A is the portion of 404 directly under the gate electrode 604, while the maximum width of the gate structure includes 602, making the gate width greater than the channel) of the gate structure (410, Fig 6B) is greater (shown greater) than that of the channel layer (404A).
Regarding claim 20, Yeh teaches the device of claim 17 and goes on to teach wherein the outer portion (602, Fig 6B) of the gate structure (410) is in direct contact (shown in direct contact) with the intermediate contact pattern (404B).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-9, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Yeh (US 20180012962 A1) as applied to claims 1, 4, 10-12, 15, 17, and 19-20 above, and further in view of Lin (US 10872973 B2).
Regarding claim 5, Yeh teaches the transistor of claim 1 and the S/D contact (412, Fig 6B).
Yeh fails to explicitly teach wherein the S/D contact comprises a first contact material layer laterally adjoining the channel layer and a second contact material layer disposed on the first contact material layer, wherein the first contact material layer comprises semi-metallic 2D material.
However, Lin teaches the S/D contact comprises a first contact material layer (222, Fig 2H) laterally adjoining (shown laterally adjoining the channel which would be directly under gate electrode 254) the channel layer (404) and a second contact material layer (270) disposed on (shown on) the first contact material layer (222),
wherein the first contact material layer (222) comprises semi-metallic 2D material (MoS2, [Col 1, Ln 48]).
Yeh and Lin are considered analogous to the claimed invention because both are from the same field of endeavor of semiconductor transistor devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Yeh with the features of Lin to create a transistor wherein the S/D contact comprises a first contact material layer laterally adjoining the channel layer and a second contact material layer disposed on the first contact material layer, wherein the first contact material layer comprises semi-metallic 2D material which can greatly save critical dimension allowance in newer technology nodes, e.g., sub-7 nm technologies (Lin, [Col 2, Ln 1-2]) and with the 2-D-2-D interface between the first 2-D material as the body region and the second 2-D material as the source/drain terminal contact, the contact resistance between the source/ drain terminal and the body region is substantially reduced, and an Ohmic contact is effectively achieved (Lin, [Col 4, Ln 27-31]).
Regarding claim 6, the combination of Yeh and Lin discloses the transistor of claim 5. Lin goes on to teach wherein the first contact material layer (222, Fig 2H) comprises a maximum width (222W: width of 222 directly under 230) greater (shown greater) than a maximum width (270W: width of 270 in horizontal direction of Fig 2H) of the second contact material layer (270).
Regarding claim 7, the combination of Yeh and Lin discloses the transistor of claim 5. Yeh teaches the S/D contact (412, Fig 6B).
Lin goes on to teach the S/D contact further comprises a third contact material layer (230, Fig 2H) interposed between (shown between) the first contact material layer (222) and the second contact material layer (270), and
a material (antimonene, [Col 1, Ln 46]) of the third contact material layer (230) is different (different) from that of the first contact material layer (222, comprised of MoS2, [Col 1, Ln 48]) and the second contact material layer (270, comprised of copper, [Col 10, Ln 1-2]).
Regarding claim 8, the combination of Yeh and Lin discloses the transistor of claim 5. Yeh teaches the S/D contact (412, Fig 6B).
Lin goes on to teach a contact etch stop layer (252, Fig 2H) laterally surrounding (shown laterally surrounding) the second contact material layer (270, Fig 2H) of the S/D contact and landing on (shown landing on) the first contact material layer (222) of the S/D contact.
Regarding claim 9, the combination of Yeh and Lin discloses the transistor of claim 5. Yeh goes on to teach that (404T: thickness of 404 shown as 3 monolayers) of the channel layer (404, Fig 6B).
Lin goes on to teach wherein a thickness (222T: thickness of 222; 6 monolayers, [Col 6, Ln 14]) of the first contact material layer (222) is greater (shown greater) than that of the channel layer.
Regarding claim 16, Yeh teaches the structure of claim 10, the S/D contact (412, Fig 6B), and the channel layer (404).
Yeh fails to explicitly teach wherein the S/D contact comprises a first contact material layer laterally coupled to the channel layer and a second contact material layer overlying the first contact material layer, and the first contact material layer is wider than the second contact material layer.
However, Lin teaches the S/D contact comprises a first contact material layer (222, Fig 2H) laterally coupled (shown laterally coupled) to the channel layer and a second contact material layer (270) overlying (shown over) the first contact material layer (222), and
the first contact material layer (222) is wider (shown wider) than the second contact material layer (270).
Yeh and Lin are considered analogous to the claimed invention because both are from the same field of endeavor of semiconductor transistor devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Yeh with the features of Lin to create a transistor wherein the S/D contact comprises a first contact material layer laterally coupled to the channel layer and a second contact material layer overlying the first contact material layer, and the first contact material layer is wider than the second contact material layer which can greatly save critical dimension allowance in newer technology nodes, e.g., sub-7 nm technologies (Lin, [Col 2, Ln 1-2]) and with the 2-D-2-D interface between the first 2-D material as the body region and the second 2-D material as the source/drain terminal contact, the contact resistance between the source/ drain terminal and the body region is substantially reduced, and an Ohmic contact is effectively achieved (Lin, [Col 4, Ln 27-31]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Pritchard (US 20210057558 A1) -2D layers in gate and/or S/D regions.
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/JEREMY DANIEL WATTS/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897