Prosecution Insights
Last updated: October 02, 2026
Application No. 18/782,187

SEMICONDUCTOR PACKAGE

Non-Final OA §102§103
Filed
Jul 24, 2024
Priority
Dec 20, 2023 — RE 10-2023-0187581 +1 more
Examiner
KIM, TONG-HO
Art Unit
Tech Center
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
95%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 95% — above average
95%
Career Allowance Rate
1040 granted / 1092 resolved
+35.2% vs TC avg
Minimal +1% lift
Without
With
+0.7%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 8m
Avg Prosecution
53 currently pending
Career history
1103
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
46.2%
+6.2% vs TC avg
§102
30.9%
-9.1% vs TC avg
§112
8.7%
-31.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1092 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) submitted on 7/24/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-2 and 10-12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Son (KR 20080071431 A). Regarding claim 1, Son discloses, in at least figures 4-5 and related text (translated text), a semiconductor package comprising: a package substrate (110, page 3) including a substrate pad (116, page 3); a semiconductor chip (120, page 3) on the package substrate (110, page 3), the semiconductor chip (120, page 3) including a chip pad (122, page 3); a bonding wire (124, page 3) that connects the substrate pad (116, page 3) to the chip pad (122, page 3); an adhesive member (118, page 3) between the package substrate (110, page 3) and the semiconductor chip (110, page 3); and a dam (131, page 3) extending along a side surface of the adhesive member (118, page 3) and surrounding at least some of side surfaces of the adhesive member (118, page 3), wherein a height of the dam (131, page 3) is greater than or equal to a height of the adhesive member (118, page 3). Regarding claim 2, Son discloses the semiconductor package of claim 1 as described above. Son further discloses, in at least figures 4-5 and related text (translated text), the dam (131, page 3) surrounds all the side surfaces of the adhesive member (118, page 3) and is in contact with the side surfaces of the adhesive member (118, page 3). Regarding claim 10, Son discloses the semiconductor package of claim 1 as described above. Son further discloses, in at least figures 4-5 and related text (translated text), the adhesive member (118, page 3) includes a first side surface and a second side surface opposite to the first side surface, and the dam (131, page 3) includes a first portion extending along the first side surface of the adhesive member (118, page 3) and a second portion extending along the second side surface of the adhesive member (118, page 3) (figures). Regarding claim 11, Son discloses the semiconductor package of claim 1 as described above. Son further discloses, in at least figures 4-5 and related text (translated text), the adhesive member (118, page 3) includes a first side surface extending in a first direction (horizontal direction, figure 4) and a second side surface extending in a second direction (vertical direction, figure 4) that crosses the first direction (horizontal direction, figure 4), and the dam (131, page 3) includes a first portion extending along the first side surface of the adhesive member (118, page 3) and a second portion extending along the second side surface of the adhesive member (118, page 3). Regarding claim 12, Son discloses the semiconductor package of claim 11 as described above. Son further discloses, in at least figures 4-5 and related text (translated text), the adhesive member (118, page 3) includes a third side surface opposite to the second side surface in the first direction (horizontal direction, figure 4), and the dam (131, page 3) further includes a third portion extending along the third side surface of the adhesive member (118, page 3). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Son (KR 20080071431 A) in view of Lin (US 2018/0342466). Regarding claim 7, Son discloses the semiconductor package of claim 1 as described above. Son does not explicitly disclose the dam is spaced apart from the adhesive member. Lin teaches, in at least figures 3A-3B and related text, the device comprising the dam (40, [22]) is spaced apart from the adhesive member (26, [21]), for the purpose of providing heat dissipation for the semiconductor chip ([22]). Son and Lin are analogous art because they are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Son with the specified features of Lin because they are from the same field of endeavor. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Son to have the dam being spaced apart from the adhesive member, as taught by Lin, for the purpose of providing heat dissipation for the semiconductor chip ([22], Lin). Regarding claim 8, Son in view of Lin discloses the semiconductor package of claim 7 as described above. Son in view of Lin does not explicitly disclose a distance between the dam and the adhesive member is about 20 µm to 30 µm. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the distance between the dam and the adhesive member as claimed in claim 8 in order to optimize the performance of the device in .. It is noted that the selection dimension of the distance between the dam and the adhesive member as being no more than use of known technique to improve similar devices in the same way. See MPEP 2143 I. C. It is noted that if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond that person's skill. KSR International Co. v. Teleflex Inc., 550 US 398, 82 USPQ2d 1385, 1389 (2007). In Gardnerv.TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. The specification contains no disclosure of either the critical nature of the claimed arrangement (i.e.- a distance between the dam and the adhesive member is about 20 µm to 30 µm) or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen limitations or upon another variable recited in a claim, the applicant must show that the chosen limitations are critical. In re Woodruff, 919 F.2d 1575, 1578 (FED. Cir. 1990). Claim(s) 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Son (KR 20080071431 A) in view of Song (US 2015/0102506). Regarding claim 13, Son discloses, in at least figures 4-5 and related text (translated text), a semiconductor package comprising: a package substrate (110, page 3) including a substrate pad (116, page 3); a first semiconductor chip (120, page 3) on the package substrate (110, page 3), the first semiconductor chip (120, page 3) including a first chip pad (122, page 3); a first adhesive member (118, page 3) between the first semiconductor chip (120, page 3) and the package substrate (110, page 3); a first bonding wire (124, page 3) connecting the substrate pad (116, page 3) to the first chip pad (122, page 3); and a dam (131/130, page 3) bordering at least one of side surfaces of the first adhesive member (118, page 3) and side surfaces of the second adhesive member. Son does not explicitly disclose a second semiconductor chip including a second chip pad, the second semiconductor chip being on the first semiconductor chip; a second adhesive member between the first semiconductor chip and the second semiconductor chip; a second bonding wire connecting the first chip pad to the second chip pad. Song teaches, in at least figure 1A and related text, the device comprising a second semiconductor chip (200, [23]) including a second chip pad (240, [41]), the second semiconductor chip (200, [23]) being on the first semiconductor chip (100, [23]); a second adhesive member (290, [32]) between the first semiconductor chip (100, [23]) and the second semiconductor chip (200, [23]); a second bonding wire (810, [27]) connecting the first chip pad (140, [41]) to the second chip pad (240, [41]), for the purpose of providing high capacity semiconductor package capable of minimizing a volume ([171]). Son and Song are analogous art because they are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Son with the specified features of Song because they are from the same field of endeavor. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Son to have the second semiconductor chip including a second chip pad, the second semiconductor chip being on the first semiconductor chip; the second adhesive member between the first semiconductor chip and the second semiconductor chip; the second bonding wire connecting the first chip pad to the second chip pad, as taught by Song, for the purpose of providing high capacity semiconductor package capable of minimizing a volume ([171], Song). Regarding claim 14, Son in view of Song discloses the semiconductor package of claim 13 as described above. Son further discloses, in at least figures 4-5 and related text (translated text), the dam (131/130, page 3) includes a first portion on the package substrate (110, page 3) and bordering at least one of the side surfaces of the first adhesive member (118, page 3). Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Son (KR 20080071431 A) in view of Song (US 2015/0102506), and further in view of Park (US 2023/0060115). Regarding claim 19, Son in view of Song discloses the semiconductor package of claim 13 as described above. Son in view of Song does not explicitly disclose the dam includes at least one of a metal material, a moisture absorbent, an epoxy resin, silicon, polyurethane, polycarbonate, polypropylene, and polyethylene. Park teaches, in at least figure 1A and related text, the device comprising the dam (502, [38]) includes at least one of a metal material ([38]), a moisture absorbent, an epoxy resin, silicon, polyurethane, polycarbonate, polypropylene, and polyethylene, for the purpose of improving reliability of the semiconductor package ([21]). Son, Song, and Park are analogous art because they are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Son in view of Song with the specified features of Park because they are from the same field of endeavor. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Son in view of Song to have the dam including at least one of a metal material, a moisture absorbent, an epoxy resin, silicon, polyurethane, polycarbonate, polypropylene, and polyethylene, as taught by Park, for the purpose of improving reliability of the semiconductor package ([21], Park). Allowable Subject Matter Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1, 2, and 3 that recite "the dam is in contact with at least some of side surfaces of the semiconductor chip" in combination with other elements of the base claims 1, 2, and 3. Claims 4-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1, 2, and 4 that recite "the second side surface includes a curved surface" in combination with other elements of the base claims 1, 2, and 4. Claim 9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1, 7, and 9 that recite "the dam includes a moisture absorbent" in combination with other elements of the base claims 1, 7, and 9. Claims 15-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 13, 14, and 15 that recite "a second portion on an upper surface of the first semiconductor chip, the second portion bordering at least one of the side surfaces of the second adhesive member" in combination with other elements of the base claims 13, 14, and 15. Claim 18 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 13 and 18 that recite "the dam is only on an upper surface of the first semiconductor chip and borders at least one of the side surfaces of the second adhesive member" in combination with other elements of the base claims 13 and 18. Claim 20 is allowed because the prior art of record neither anticipates nor render obvious the limitations of the base claims 20 that recite "a side surface of the dam includes a curved surface" in combination with other elements of the base claims 20. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONG-HO KIM whose telephone number is (571)270-0276. The examiner can normally be reached Monday thru Friday; 8:30 AM to 5PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TONG-HO KIM/ Primary Examiner, Art Unit 2811
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Prosecution Timeline

Jul 24, 2024
Application Filed
Sep 16, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
95%
Grant Probability
96%
With Interview (+0.7%)
1y 8m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1092 resolved cases by this examiner. Grant probability derived from career allowance rate.

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