Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on July 24, 2024 was in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 6, 9 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Eid (Pub. No.: US 2021/0057354 A1).
Regarding Claim 1, Eid discloses a semiconductor package, comprising: a package substrate (Par. 0175; Fig. 24 – package substrate 2401); a first semiconductor device on the package substrate (Par. 0175; Fig. 24 – first semiconductor device 2406); a second semiconductor device on the package substrate and spaced laterally from the first semiconductor device (Par. 0175; Fig. 24 – second semiconductor device 2405); and
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a package encapsulant including a first encapsulant and a second encapsulant, wherein the first encapsulant is on the package substrate, in contact with side surfaces of the first semiconductor device and at least partially encloses the side surfaces of the first semiconductor device, and the second encapsulant is on the package substrate and laterally spaced apart from some side surfaces of the second semiconductor device (Par. 0175; Fig. 24 – molding layer 2402 on the right side of the second semiconductor device 2405 could be considered as the first encapsulant; molding layer 2402 on the left side of the second semiconductor device 2405 could be considered as the second encapsulant), wherein the first encapsulant and the second encapsulant are integrally provided, and some side surfaces of the package encapsulant are coplanar with an outer edge of the package substrate Par. 0175; Fig. 24).
Regarding Claim 6, Eid, as applied to claim 1, discloses the semiconductor package, wherein the first encapsulant extends around side surfaces of the first semiconductor device and a top surface of the first semiconductor device (Fig. 24).
Regarding Claim 9, Eid, as applied to claim 1, discloses the semiconductor package, wherein the second encapsulant faces at least one side surface of the second semiconductor device (Fig. 24).
Regarding Claim 15, Eid, as applied to claim 1, discloses the semiconductor package, wherein the first semiconductor device includes an application processor, and the second semiconductor device includes at least one memory chip (Par. 0042, 0188).
Allowable Subject Matter
Claims 16-20 are allowed. The following is an examiner's statement of reasons for allowance:
Regarding Claim 16: The prior art of record to the examiner’s knowledge does not teach or render obvious the instant invention, particularly characterized by a semiconductor package, comprising: a package substrate having a plurality of upper connection pads on a top surface thereof; a first semiconductor device on the package substrate and electrically connected to a first subset of the plurality of upper connection pads; and a package encapsulant including a first encapsulant and a second encapsulant, wherein the first encapsulant is on the package substrate and is in contact with at least some side surfaces of the first semiconductor device at a perimeter of the first semiconductor device, and the second encapsulant is on the package substrate and laterally spaced from a second subset of the plurality of upper connection pads, and at least partially encloses the second subset of the plurality of upper connection pads, wherein the first encapsulant and the second encapsulant are integrally provided, and a first height, which is a vertical level of the first encapsulant relative to the top surface of the package substrate, is greater than a second height, which is a vertical level of the second encapsulant relative to the top surface of the package substrate, the first height is equal to or greater than a third height, which is a vertical level of a top surface of the first semiconductor device relative to the top surface of the package substrate, and some side surfaces of the package encapsulant are coplanar with an outer edge of the package substrate.
The most relevant prior art reference due to Eid (Pub. No.: US 2021/0057354 A1) substantially discloses a semiconductor package, comprising: a package substrate having a plurality of upper connection pads on a top surface thereof (Par. 0175; Fig. 24 (in light of Figs. 20-23) – package substrate 2401); a first semiconductor device on the package substrate and electrically connected to a first subset of the plurality of upper connection pads (Par. 0175; Fig. 24 (in light of Figs. 20-23) – package substrate 2401; first semiconductor device 2406); and
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a package encapsulant including a first encapsulant and a second encapsulant, wherein the first encapsulant is on the package substrate and is in contact with at least some side surfaces of the first semiconductor device at a perimeter of the first semiconductor device, and the second encapsulant is on the package substrate and laterally spaced from a second subset of the plurality of upper connection pads, and at least partially encloses the second subset of the plurality of upper connection pads, wherein (Par. 0175; Fig. 24 (in light of Figs. 20-23) – molding layer 2402 on the right side of a second semiconductor device 2405 could be considered as the first encapsulant; molding layer 2402 on the left side of the second semiconductor device 2405 could be considered as the second encapsulant), wherein the first encapsulant and the second encapsulant are integrally provided (Par. 0175; Fig. 24 (in light of Figs. 20-23)), and the first height is equal to or greater than a third height, which is a vertical level of a top surface of the first semiconductor device relative to the top surface of the package substrate (Fig. 24), and some side surfaces of the package encapsulant are coplanar with an outer edge of the package substrate (Fig. 24).
This prior art, however, does not disclose a semiconductor package, comprising: a first height, which is a vertical level of the first encapsulant relative to the top surface of the package substrate, is greater than a second height, which is a vertical level of the second encapsulant relative to the top surface of the package substrate.
Additionally, the prior arts made of record and not relied upon are considered pertinent to applicant's disclosure. See form PTO-892.
However, none of these prior art references indicated above or the prior arts made of record in form PTO-892, disclose all the limitations of claim 16 (the individual limitations may be found in a plurality of prior arts but there is no motivation to combine). Because no reference alone teaches all the limitations, nor is there any motivation to combine the prior arts to construct all the limitations of this independent claim, claim 16 is deemed patentable over the prior arts.
Regarding Claims 17-18: these claims are allowed because of their dependency status from claim 16.
Regarding Claim 19: The prior art of record to the examiner’s knowledge does not teach or render obvious the instant invention, particularly characterized by a semiconductor package, comprising: a package substrate having a plurality of upper connection pads on a top surface thereof; a first semiconductor device on the package substrate and electrically connected to a first subset of the plurality of upper connection pads; and a package encapsulant including a first encapsulant and a second encapsulant, wherein the first encapsulant is on the package substrate and in contact with at least some side surfaces of the first semiconductor device at a perimeter of the first semiconductor device, and the second encapsulant is on the package substrate and laterally spaced from a second subset of the plurality of upper connection pads, and at least partially encloses the second subset of the plurality of upper connection pads, wherein the first encapsulant and the second encapsulant are integrally provided, and a first height, which is a vertical level of the first encapsulant relative to the top surface of the package substrate, is greater than a second height, which is a vertical level of the second encapsulant relative to the top surface of the package substrate, the second height is less than or equal to half the first height, the first height is equal to or greater than a third height, which is a vertical level of a top surface of the first semiconductor device relative to the top surface of the package substrate, and some side surfaces of the package encapsulant are coplanar with an outer edge of the package substrate.
The most relevant prior art reference due to Eid (Pub. No.: US 2021/0057354 A1) substantially discloses a semiconductor package, comprising: a package substrate having a plurality of upper connection pads on a top surface thereof (Par. 0175; Fig. 24 (in light of Figs. 20-23) – package substrate 2401); a first semiconductor device on the package substrate and electrically connected to a first subset of the plurality of upper connection pads (Par. 0175; Fig. 24 (in light of Figs. 20-23) – package substrate 2401; first semiconductor device 2406); and
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a package encapsulant including a first encapsulant and a second encapsulant, wherein the first encapsulant is on the package substrate and in contact with at least some side surfaces of the first semiconductor device at a perimeter of the first semiconductor device, and the second encapsulant is on the package substrate and laterally spaced from a second subset of the plurality of upper connection pads, and at least partially encloses the second subset of the plurality of upper connection pads (Par. 0175; Fig. 24 (in light of Figs. 20-23) – molding layer 2402 on the right side of a second semiconductor device 2405 could be considered as the first encapsulant; molding layer 2402 on the left side of the second semiconductor device 2405 could be considered as the second encapsulant), wherein the first encapsulant and the second encapsulant are integrally provided (Par. 0175; Fig. 24 (in light of Figs. 20-23)), and
Fig. 24), and some side surfaces of the package encapsulant are coplanar with an outer edge of the package substrate (Fig. 24).
This prior art, however, does not disclose a semiconductor package, comprising: a first height, which is a vertical level of the first encapsulant relative to the top surface of the package substrate, is greater than a second height, which is a vertical level of the second encapsulant relative to the top surface of the package substrate, the second height is less than or equal to half the first height
Additionally, the prior arts made of record and not relied upon are considered pertinent to applicant's disclosure. See form PTO-892.
However, none of these prior art references indicated above or the prior arts made of record in form PTO-892, disclose all the limitations of claim 19 (the individual limitations may be found in a plurality of prior arts but there is no motivation to combine). Because no reference alone teaches all the limitations, nor is there any motivation to combine the prior arts to construct all the limitations of this independent claim, claim 19 is deemed patentable over the prior arts.
Regarding Claims 20: this claim is allowed because of its dependency status from claim 19.
Allowable Subject Matter
Claims 2-5, 7-8 and 10-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Mehta et al. (Pub. No.: US 2021/0035859 A1) – This prior art teaches a semiconductor package, comprising: a package substrate (130); a first semiconductor device (120A)on the package substrate; a second semiconductor device (120B) on the package substrate and spaced laterally from the first semiconductor device; and a package encapsulant including a first encapsulant (128 – left of 120A and right of 120B) and a second encapsulant (128 – between 120A and 120B), wherein the first encapsulant is on the package substrate, in contact with side surfaces of the first semiconductor device and at least partially encloses the side surfaces of the first semiconductor device , and the second encapsulant is on the package substrate and laterally spaced apart from some side surfaces of the second semiconductor device, wherein the first encapsulant and the second encapsulant are integrally provided, and some side surfaces of the package encapsulant are coplanar with an outer edge of the package substrate (Figs. 1A-1D).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SYED I GHEYAS whose telephone number is (571)272-0592. The examiner can normally be reached on Monday-Friday from 8:30 AM - 5:30 PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley, can be reached at telephone number (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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09/22/2026
/SYED I GHEYAS/Primary Examiner, Art Unit 2893
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