DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claim 3-4, 8-9, 12-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 5-7, 10-11 and 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhou et al. (PGPUB 20240061583), hereinafter as Zhou, in view of Papagianni et al. (PGPUB 20240071514), hereinafter as Papagianni.
Regarding claim 1, Zhou teaches a semiconductor memory device comprising: a memory cell array including a plurality of memory blocks (Fig 1, memory device 130, 140); and
a control logic (Fig 1, controller 115) configured to control an operation of the memory cell array, wherein the control logic sets a target level (Fig 6, parameter used in step 640) of a program verify operation ([0020] program verify operation), based on
but not expressly an offset information based on physical information of the group,
Papagianni teaches an offset information based on physical information of the group ([0043] read offset voltages …due to physical locations… word line groups).
Since Zhou and Papagianni are both from the same field of semiconductor memory device, the purpose disclosed by Papagianni would have been recognized in the pertinent art of Zhou.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to find offset values of read voltages based on physical features of a cell group as in Papagianni into the device of Zhou for the purpose of managing memory device operations.
Regarding claim 2, Zhou teaches divide world lines into groups ([0021]), Papagianni teaches store offset information ([0043]); except expressly multiple offsets info for a group of word lines. It has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
Regarding claim 5, Zhou and Papagianni teach a device as in rejection of claim 2, except expressly store offset info in a system block or a CAM block. It has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Regarding claim 6, Zhou teaches a semiconductor memory device comprising: a memory cell array including a plurality of memory blocks (Fig 1); a peripheral circuit (Fig 1, controller) configured to perform a program operation on a selected memory block among the plurality of memory blocks ([0027]);
a group information storage unit configured to store group information; and a control logic configured to control the peripheral circuit to perform the program operation, wherein the control logic sets a target level of a program verify operation during the program operation, based on the group information (Fig 6, step 630-640).
Regarding claim 7, argument used in rejection of claim 2 applies.
Regarding claim 10, argument used in rejection of claim 5 applies.
Regarding claim 11, Zhou teaches a method of operating a semiconductor memory device, the method comprising:
receiving a program command, an address, and program data with the semiconductor memory device ([0027] write data, it is obvious address info is associated with a write process);
setting a target level of each of program states of a selected page of a selected memory block including memory cells to be programmed by checking group information corresponding to the address among group information stored in a group information storage unit (Fig 6, 630-640);
performing a program voltage apply operation on the selected page (Fig 6, step 640); and
performing a program verify operation on the selected page, using the target level ([0020]).
Regarding claim 14, the examiner takes note that it is well known that a program verify operation as a program pass when memory cells included in the selected page are programmed to the set target level or higher in the program verify operation.
Regarding claim 15, the examiner takes note that it is well known that selecting a next page of the selected page and re-performing the operations from the program voltage apply operation when the program verify operation is determined as the program pass
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIN HUANG whose telephone number is (571)270-5798. The examiner can normally be reached M-F 9-6.
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/MIN HUANG/ Primary Examiner, Art Unit 2827