DETAILED ACTION
Examiner’s Note
The examiner has cited particular passages including column and line numbers, paragraphs as designated numerically and/or figures as designated numerically in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claims, other passages, paragraphs and figures of any and all cited prior art references may apply as well. It is respectfully requested from the applicant, in preparing an eventual response, to fully consider the context of the passages, paragraphs and figures as taught by the prior art and/or cited by the examiner while including in such consideration the cited prior art references in their entirety as potentially teaching all or part of the claimed invention. MPEP 2141.02 VI: “PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS." MPEP 2123 (I): “PATENTS ARE RELEVANT AS PRIOR ART FOR ALL THEY CONTAIN.”
Additionally, in an effort to provide a timely Office response to amendments the Applicant may file in response to this Office Action, it is respectfully requested that, on accompanying remarks/arguments papers, every effort be made to provide specific (page No., paragraph No., FIG. No., etc.) Specification/Drawings support for such amendments, particularly claim amendments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claim(s) 1-11 are allowed.
The following is an examiner’s statement of reasons for allowance: the pertinent prior art of record, such as US 20160125939, US 20160148668, and in light of such record as a whole under MPEP 1302.14 guidance, and further guidance under MPEP 2103, in brief and saliently: “the claim as a whole must be considered,” does not teach or suggest the combination of claim limitations making the whole of the claim(s) of the claimed invention, particularly as set forth in representative claim(s) 1; expressing the claim(s) and highlighting subject matter, in brief and saliently: while the pertinent prior art may include teachings, generally, of memory readout circuit that may include a comparator that compares a memory cell charge with a reference potential to identify the memory cell state, and while a sensing capacitance may be involved in such readout circuit, said prior art is silent on such teachings further including, in combination with the rest of the claim limitations, in whole, under MPEP 2103 as set forth above: a level detector that is set up to provide a digital output signal and to switch a state of the digital output signal when a potential of the readout node crosses a switching threshold; and a control circuit that is configured to set the switching threshold and/or a switching speed of the level detector depending on the cell current.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 12-19 are rejected under 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph, as based on a disclosure which is not enabling. The disclosure does not enable one of ordinary skill in the art to practice the invention without a critical element as found in at least in the Abstract, [0004], [0022], [0025], [0044], etc., and at least FIGS. 2, 4, 6, 7: Capacitor 608 in FIG. 6, which is/are critical or essential to the practice of the invention but not included in the claim(s). See In re Mayhew, 527 F.2d 1229, 188 USPQ 356 (CCPA 1976). As disclosed in at least the Abstract: “The memory readout circuit includes a readout node having a capacitance that is discharged by the memory cell to read out a memory cell by means of a cell current.” And as found in at least [0043]: “The memory readout circuit 600 is an example of a circuit in which the cell current is measured at the integration capacitance (based on the discharge current of the integration capacitance in the readout phase).” That is, without the capacitor 608 in FIG. 6, the cell current could not be measured, it would lack a capacitor to do just that. Claim 12 requires, in brief and saliently: “a third transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the third transistor being coupled to the first input of the comparator.” While claim 13, further defines this third transistor: “wherein the second terminal of the third transistor is coupled to a ground terminal and the control terminal of the third transistor is coupled to a constant voltage bias terminal.” It seems only transistor 605 in FIG. 6 could be this claimed third transistor. However, and this is the important part, the first terminal of 605 is not coupled to the first input of the comparator 602. It is coupled to capacitor 608, which in turn is coupled to the first input of comparator 602. Once more, without capacitor 608, the present invention falls; 608 is critical to the functioning of the invention.
Claim(s) 12-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential elements, such omission amounting to a gap between the elements. See MPEP § 2172.01. The omitted elements are: integration capacitor 208, 405, 608, 708, or 1001/1002 in FIGS. 2, 4, 6, 7 and 10, respectively. For analysis on the criticality of these capacitors to the present invention, refer to analysis above under claim rejection based on 35 USC 112(a) based on the disclosure of the present Application.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO N HIDALGO whose telephone number is (571)270-3306. The examiner can normally be reached M-F 9:00-7:30 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 5712721852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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FERNANDO N. HIDALGO
Primary Examiner
Art Unit 2827
/Fernando Hidalgo/Primary Examiner, Art Unit 2827