DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4-5, 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tomioka et al. (US 2022/0058365 A1 hereinafter referred to as “Tomioka”).
With respect to claim 1, Tomioka discloses, in Figs.1-21, a detection device comprising: a substrate (21); and a plurality of photodiodes (PD) arranged on the substrate (21), wherein each of the photodiodes (PD) includes a lower electrode (35), a lower buffer layer (32c), an active layer (32a), an upper buffer layer (32b), and an upper electrode (34) that are stacked on the substrate (21) in the order as listed, and a plurality of the lower electrodes (34) are each provided with a plurality of openings (H3) (see Par.[0036]-[0038] wherein a control board 201 is electrically coupled to the insulating substrate 21 through a flexible printed circuit board 71; see Par.[0040] wherein the sensor 10 is an optical sensor including the light-receiving elements PD each serving as a photoelectric conversion element; each of the light-receiving elements PD is the photoelectric conversion element, more specifically, a photodiode, and outputs an electrical signal corresponding to the received light as a detection signal Vdet to the signal line selection circuit 16; see Par.[0094] wherein the lower electrode 35 is electrically coupled to the third conductive layer 67 through the contact hole H3 provided in the first organic insulating layer 23a; see Par.[0074] wherein as illustrated in FIG. 8, the light-receiving element PD is configured such that the lower electrode 35, the third semiconductor 31, and the upper electrode 34 are stacked in the order of the lower electrode 35, the third semiconductor 31, and the upper electrode 34 on a first organic insulating layer 23a of a backplane 2; see Par.[0075] wherein the semiconductor 32a is formed of a bulk heterojunction of a p-type semiconductor and an n-type semiconductor, and the semiconductor 32b and the semiconductor 32c are each formed of a charge transport layer or a charge blocking layer of electrons and holes, respectively).
With respect to claim 2, Tomioka discloses, in Figs.1-21, the detection device, wherein the lower buffer layer (32c) includes either a hole transport layer or an electron transport layer, and the upper buffer (32b) layer includes the other of the hole transport layer and the electron transport layer (see Par.[0075] wherein the semiconductor 32a is formed of a bulk heterojunction of a p-type semiconductor and an n-type semiconductor, and the semiconductor 32b and the semiconductor 32c are each formed of a charge transport layer or a charge blocking layer of electrons and holes, respectively).
With respect to claim 4, Tomioka discloses, in Figs.1-21, the detection device, wherein the openings of the lower electrode are arranged in a first direction and are each formed in a slit shape extending in a second direction intersecting the first direction (see Figs.4, 7-8).
With respect to claim 5, Tomioka discloses, in Figs.1-21, the detection device, wherein the openings of the lower electrode are arranged in a matrix having a row-column configuration (see Par.[0050] wherein As illustrated in FIG. 4, the sensor 10 has a plurality of partial detection areas PAA arranged in a matrix having a row-column configuration).
With respect to claim 7, Tomioka discloses, in Figs.1-21, the detection device, comprising power supply wiring line coupled to the lower electrode, wherein the openings radially extend from a contact between the power supply wiring line and the lower electrode (see Par.[0051] wherein the cathode of the light-receiving element PD is supplied with the power supply signal SVS from the power supply circuit 203; see Par.[0056] wherein the gate line drive circuit 15 supplies the gate drive signals VGCL to the first switching elements Tr through the selected gate lines GCL).
Claims 1, 4-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Watanabe et al. (US 2014/0339431 A1 hereinafter referred to as “Watanabe”).
With respect to claim 1, Watanabe discloses, in Figs.1A-15, a detection device comprising: a substrate (100); and a plurality of photodiodes (12) arranged on the substrate (100), wherein each of the photodiodes (12) includes a lower electrode (122), a lower buffer layer (121, 123), an active layer (124), an upper buffer layer (125-126), and an upper electrode (128) that are stacked on the substrate (100) in the order as listed, and a plurality of the lower electrodes (122) are each provided with a plurality of openings (see Par.[0035] wherein each pixel 11 includes a converting element 12 to convert radiation or light into charge and a thin film transistor (TFT) 13, serving as a switching element, to output an electrical signal depending on the charge in the converting element 12; the converting element 12 is disposed over the TFT 13 disposed on the insulating substrate 100, such as a glass substrate, such that an interlayer insulating layer 120 formed of an organic material is disposed between the converting element 12 and the TFT 13; see Par.[0038] wherein the converting element 12 includes on the interlayer insulating layer 120 a metal layer 122, serving as the pixel electrode, a first conductivity type impurity semiconductor layer 123, a semiconductor layer 124, a second conductivity type impurity semiconductor layer 125, and a counter electrode 126 arranged in that order from the interlayer insulating layer (or the substrate) side; the covering members 121 formed of the inorganic material, specifically, the covering member 121 is disposed between the interlayer insulating layer 120 and the first conductivity type impurity semiconductor layer 123 in each of the gaps 122' of the metal layer 122 and in each area between the pixel electrodes of the adjacent pixels 11; see Par.[0052] wherein a conductive layer 128 having a lower resistivity than the impurity semiconductor layer 123 is disposed between the metal layer 122 and the interlayer insulating layer 120 and the pixel electrode includes the metal layer 122 and the conductive layer 128; see Fig.1C wherein a plurality of the lower electrodes (122) are each provided with a plurality of openings).
With respect to claim 4, Watanabe discloses, in Figs.1A-15, the detection device, wherein the openings of the lower electrode are arranged in a first direction and are each formed in a slit shape extending in a second direction intersecting the first direction (see Fig.1C wherein a plurality of the lower electrodes (122) are each provided with a plurality of openings).
With respect to claim 5, Watanabe discloses, in Figs.1A-15, the detection device, wherein the openings of the lower electrode are arranged in a matrix having a row-column configuration (see Fig.3, wherein photodiodes 12 are arranged in matrix formation; see Par.[0042] wherein a schematic equivalent circuit of the detecting apparatus according to the first embodiment will be described below with reference to FIG. 3. Although FIG. 3 illustrates the equivalent circuit of 3 rows by 3 columns for the convenience of description, the disclosure is not limited to this illustration).
With respect to claim 6, Watanabe discloses, in Figs.1A-15, the detection device, wherein the openings of the lower electrode are each formed in a slit shape and extend at a predetermined angle with respect to an arrangement direction of the photodiodes (see Fig.1C wherein a plurality of the lower electrodes (122) are each provided with a plurality of openings).
With respect to claim 7, Watanabe discloses, in Figs.1A-15, the detection device, comprising power supply wiring line (15) coupled to the lower electrode, wherein the openings radially extend from a contact between the power supply wiring line and the lower electrode (see Par.[0042]-[0043] wherein a power supply circuit 9 supplies a reference potential Vref to a noninverting input terminal of each integrating amplifier 5. The power supply circuit 9 is electrically connected to the electrode lines 14 arranged in the row direction, and supplies a bias potential Vs to the counter electrode 126 of each converting element 12).
Claims 1, 3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamazaki et al. (US 2014/0209899 A1 hereinafter referred to as “Yamazaki”).
With respect to claim 1, Yamazaki discloses, in Figs.1A-30C, a detection device comprising: a substrate (601); and a plurality of photodiodes (602) arranged on the substrate (601), wherein each of the photodiodes (602) includes a lower electrode (641), a lower buffer layer (606a), an active layer (606b), an upper buffer layer (606c), and an upper electrode (642) that are stacked on the substrate (601) in the order as listed, and a plurality of the lower electrodes (601) are each provided with a plurality of openings/(opened spaced without lower electrode 641 between photodiodes) (see Par.[0434]-[0445] wherein FIG. 18A illustrates an example of a semiconductor device having an image sensor function; in the photodiode 602, a first semiconductor film 606a, a second semiconductor film 606b, and a third semiconductor film 606c are sequentially stacked from the interlayer insulating film 633 side, between an electrode 641 formed over the interlayer insulating film 633 and an electrode 642 formed over the interlayer insulating film 634; a pin photodiode in which a semiconductor film having p-type conductivity as the first semiconductor film 606a, a high-resistance semiconductor film (i-type semiconductor film) as the second semiconductor film 606b, and a semiconductor film having n-type conductivity as the third semiconductor film 606c are stacked is illustrated as an example; see Par.[0058]-[0060] wherein in the doped semiconductor of device (transistor and photodiode) has sheet resistance it is greater than or equal to 50 M.OMEGA./sq., preferably greater than or equal to 1 G.OMEGA./sq).
With respect to claim 3, Yamazaki discloses, in Figs.1A-30C, the detection device, wherein the lower buffer layer has sheet resistance of equal to or larger than 1×1010 Ω/sq. and not larger than 1×1013 Ω/sq (see Par.[0434]-[0445] wherein FIG. 18A illustrates an example of a semiconductor device having an image sensor function; in the photodiode 602, a first semiconductor film 606a, a second semiconductor film 606b, and a third semiconductor film 606c are sequentially stacked from the interlayer insulating film 633 side, between an electrode 641 formed over the interlayer insulating film 633 and an electrode 642 formed over the interlayer insulating film 634; a pin photodiode in which a semiconductor film having p-type conductivity as the first semiconductor film 606a, a high-resistance semiconductor film (i-type semiconductor film) as the second semiconductor film 606b, and a semiconductor film having n-type conductivity as the third semiconductor film 606c are stacked is illustrated as an example; see Par.[0058]-[0060] wherein in the doped semiconductor of device (transistor and photodiode) has sheet resistance it is greater than or equal to 50 M.OMEGA./sq., preferably greater than or equal to 1 G.OMEGA./sq).
Citation of Pertinent Prior Art
The prior art made of record (e.g.; see PTO-892) and not relied upon is considered pertinent to applicant's disclosure.
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOULOUCOULAYE INOUSSA whose telephone number is (571)272-0596. The examiner can normally be reached Monday-Friday (10-18).
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/Mouloucoulaye Inoussa/ Primary Examiner, Art Unit 2818
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