Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. (see MPEP § 606.01).
This may result in slightly longer titles, but the loss in brevity of title will be more than offset by the gain in its informative value in indexing, classifying, searching, etc.
The following title is suggested:
“
because the application is directed to a lead-frame power module having at least one control chip positioned over and electrically connected to a first die pad, together with power chips mounted on second die pads. Applicant is required to amend the title to more accurately reflect the nature of the disclosed invention.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-8 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Regarding claim 1, the phrase "the respective second die pads" renders the scope of the claim unclear. The term "respective" ordinarily denotes a one-to-one correspondence between the plurality of power chips and the plurality of second die pads. However, the specification discloses an embodiment in which multiple power chips are mounted on the same second die pad. Therefore, it is unclear whether claim 1 requires a one-to-one correspondence between the plurality of power chips and the plurality of second die pads. Applicant is required to amend the claim to clarify the intended relationship.
Suggestion: Applicant may overcome this rejection by amending the limitation from:
"...a plurality of power chips mounted to the respective second die pads..."
to:
"...a plurality of power chips mounted to the second die pads..."
Deletion of the term "respective" removes the implication of a one-to-one correspondence between the plurality of power chips and the plurality of second die pads, thereby clarifying the scope of the claim. Such an amendment is supported by the specification, which discloses an embodiment in which multiple power chips are mounted on the same second die pad (e.g., second die pad 4c).
Further regarding claim 1, the phrase "the respective circuit patterns" renders the scope of the claim unclear. The term "respective" ordinarily denotes a one-to-one correspondence between the plurality of control chips and the plurality of circuit patterns. However, the claim does not clearly define such a correspondence. Therefore, it is unclear whether claim 1 requires each control chip to be electrically connected to a different circuit pattern. Applicant is required to amend the claim to clarify the intended relationship.
Suggested amendment, similarly, the applicant could simply delete "respective":
from:
"...electrically connected to the respective circuit patterns..."
to:
"...electrically connected to the circuit patterns..."
This removes the implication of a one-to-one correspondence while preserving the intended structural relationship.
Regarding claims 2-8, because of their dependency on claim 1, these claims are also objected for the reasons set forth above with respect to claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Ishimatsu et al. (US 20210217741) in view of Muto et al. (US 20190035745).
Regarding claim 1. Fig 4 of Ishimatsu discloses A semiconductor device comprising:
a first die pad (first base portion 55; Figs. 4 and 5);
at least one control chip (control chip 4G) provided on a top side of the first die pad and at a position overlapping the first die pad in plan view (Figs. 4 and 5);
a plurality of control-side terminals (2I-2O) configured to supply signals to the control chip (Fig. 4);
a plurality of second die pads (second base portions 56; Figs. 4 and 5);
a plurality of power chips (4D-4F) mounted on the second die pads and controlled by the control chip (Fig. 4);
a plurality of power-side terminals (12B-12D) connected to the second die pads (Fig. 4);
a plurality of conductive circuit patterns (conductive section 5 including wirings 50A-50P, first base portion 55, second base portion 56, and connecting portion 57) electrically connected to the plurality of control-side terminals (Figs. 4 and 5);
a plurality of wire pads (wire-bond pads 21P and 21C of conductive section 5) electrically connected to the conductive circuit patterns (Figs. 4 and 5);
a plurality of first control wires (bonding wires extending between control chip 4G and wire-bond pads 21P and 21C) electrically connecting the plurality of wire pads and the control chip (Figs. 4 and 5);
a plurality of second control wires (bonding wires extending between control chip 4G and power chips 4D-4F) electrically connecting the control chip and first connection regions of the plurality of power chips (Fig. 4);
a molding resin (7) encapsulating the control chip, the plurality of power chips, the plurality of first control wires, and the plurality of second control wires (Figs. 4 and 5); and
wherein the first die pad, the plurality of second die pads, the plurality of control-side terminals, and the plurality of power-side terminals are formed from a lead frame (Fig. 4).
Although Ishimatsu further discloses that conductive bonding material 84 used to mount control chips 4G and 4H to first base portion 55 may instead comprise an insulative bonding material (¶ [0470]), thereby teaching an electrically insulating material disposed on the top surface of the first die pad, Ishimatsu does not expressly disclose:
an insulating substrate provided on the top surface of the first die pad;
conductive circuit patterns arranged on the insulating substrate; and
wire pads arranged on the top surface of the insulating substrate and electrically connected to the conductive circuit patterns.
However, Muto discloses wiring substrate PCB comprising a base material made of an insulating material and a plurality of conductive wires BW formed in the base material (¶ [0115]; Fig. 14). Muto further discloses that wiring substrate PCB is mounted over chip mounting portion DPC through bonding material BD (¶¶ [0115]-[0117]; Figs. 12 and 14).
Muto further discloses that the end portions of conductive wires BW are connected to bonding pads BPD exposed at upper surface PCBt of wiring substrate PCB. Conductive wires BW are covered by an insulating film while bonding pads BPD are exposed through openings in the insulating film for wire bonding (¶ [0116]; Fig. 14).
Accordingly, regarding the limitation:
"an insulating substrate provided on the top surface of the first die pad," Muto teaches wiring substrate PCB mounted over chip mounting portion DPC corresponding to the claimed first die pad (¶¶ [0115]-[0117]; Figs. 12 and 14).
"a plurality of conductive circuit patterns arranged on the insulating substrate," Muto teaches conductive wires BW formed in the insulating base material and terminating at bonding pads BPD exposed at upper surface PCBt of wiring substrate PCB (¶¶ [0115]-[0116]; Fig. 14).
"a plurality of wire pads arranged on the top surface of the insulating substrate and electrically connected to the conductive circuit patterns," Muto teaches bonding pads BPD exposed at upper surface PCBt and electrically connected to conductive wires BW (¶ [0116]; Fig. 14).
Muto further discloses that semiconductor chip SCC is electrically connected to bonding pads BPD through bond wires WR/WGH (¶¶ [0115], [0116], [0171]; Figs. 12-14).
Muto additionally discloses that wiring substrate PCB is disposed between semiconductor chip SCC and the high-side power semiconductor chips such that routing electrical signals through the wiring substrate reduces bond-wire length, reduces wire deformation, and improves package reliability (¶ [0118]; Figs. 12 and 14).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the electrically insulating structure recognized by Ishimatsu in paragraph [0470] in the form of Muto's wiring substrate PCB.
Ishimatsu expressly recognizes the desirability of electrically insulating the control chip from the first die pad by providing an insulating material therebetween. Muto teaches a known implementation of such an electrically insulating structure as an insulating wiring substrate carrying conductive circuit patterns and bonding pads for routing electrical signals. Muto further teaches that employing the wiring substrate reduces bond-wire length, reduces wire deformation, and improves package reliability (¶ [0118]). Therefore, one of ordinary skill in the art would have been motivated to incorporate Muto's wiring substrate PCB into the semiconductor package of Ishimatsu in order to implement the electrically insulating structure suggested by Ishimatsu while obtaining the known benefits of improved signal routing and package reliability.
The proposed modification merely changes the structure by which control signals are routed above the first die pad and does not alter the fundamental operation of Ishimatsu's semiconductor package. The modification would have involved using Muto's known insulating wiring substrate according to its established function and would have yielded the predictable result of providing electrically insulated signal routing while improving package reliability. Accordingly, claim 1 would have been obvious over Ishimatsu in view of Muto.
Regarding claim 2. Ishimatsu in view of Muto discloses the semiconductor device according to claim 1, Muto does not expressly disclose that the distance between the plurality of wire pads and the control chip is shorter than the distance between the control chip and the plurality of power chips. However, Figure 12 illustrates control chip SCC disposed adjacent the left lateral side of wiring substrate PCB, with bonding pads BPD positioned between control chip SCC and terminal LD. The bond wires extending between control chip SCC and bonding pads BPD follow a relatively direct routing path toward the adjacent left side of wiring substrate PCB. In contrast, the bond wires extending between control chip SCC and power semiconductor chip SCL1 traverse across the routing region occupied by the bond wires connected to bonding pads BPD before reaching the more remotely positioned power semiconductor chip SCL1. Accordingly, the routing path between control chip SCC and power semiconductor chip SCL1 is necessarily longer than the routing path between control chip SCC and bonding pads BPD.
Therefore, it would have been obvious to one of ordinary skill in the art that the bonding pads BPD would be positioned closer to control chip SCC than the power semiconductor chip SCL1, such that the distance between the plurality of wire pads and the control chip is shorter than the distance between the control chip and the plurality of power chips, as recited in claim 2. Such an arrangement represents a predictable optimization of the semiconductor package layout that minimizes the length of the control-wire connections while maintaining the required electrical connections to the more remotely located power semiconductor chips.
Regarding claim 3. Ishimatsu in view of Muto discloses the semiconductor device according to claim 1, Muto discloses that the bond wires extending between control chip SCC and power semiconductor chips SCL1 and SCL2 extend generally in a first direction from control chip SCC toward the power semiconductor chips (Fig. 12). Muto further discloses that wiring substrate PCB extends beyond chip mounting portion DPC toward the power semiconductor chips such that the end of wiring substrate PCB protrudes beyond the corresponding end of chip mounting portion DPC in the direction of the first connection regions of the power semiconductor chips (Figs. 12 and 14).
Regarding claim 6. Ishimatsu in view of Muto discloses the semiconductor device according to claim 1, Muto discloses that power semiconductor chips SCL1 and SCL2 are arranged below wiring substrate PCB and partially overlap wiring substrate PCB in plan view (Fig. 12). Figure 12 further illustrates that the first connection regions of power semiconductor chips SCL1 and SCL2 are exposed beyond the edge of wiring substrate PCB and therefore do not overlap the wiring substrate in plan view.
Regarding claim 7. Ishimatsu in view of Muto discloses the semiconductor device according to claim 1, Muto discloses that the encapsulating molding resin MR comprises an epoxy resin (¶ [0124]). Muto further discloses that wiring substrate PCB comprises an insulating base material (¶ [0115]). Therefore, it would have been obvious to one of ordinary skill in the art that the insulating substrate would be formed of a material capable of withstanding the molding process used to encapsulate the semiconductor package, including the curing of the epoxy molding resin, without degradation or loss of structural integrity. Selecting an insulating substrate material having an appropriate heat resistance for compatibility with the epoxy molding process would have been a routine design consideration and would have yielded predictable results.
Regarding claim 8. Ishimatsu in view of Muto discloses the semiconductor device according to claim 1, Ishimatsu expressly discloses that semiconductor chips 4A-4F are metal-oxide-semiconductor field-effect transistors (MOSFETs) and that the semiconductor material of the semiconductor chips may comprise a wide bandgap semiconductor, such as gallium nitride (GaN) (¶ [0436]).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Ishimatsu et al. (US 20210217741) in view of Muto et al. (US 20190035745), and further in view of Kim et al. (US 20210111105).
Regarding claim 4. Ishimatsu in view of Muto discloses the semiconductor device according to claim 1. But Ishimatsu in view of Muto does not expressly disclose the at least one control chip is mounted to the top surface of the insulating substrate and is electrically connected to the first die pad via a through hole provided in the insulating substrate.
However, Kim expressly discloses a control die 16 mounted on the top surface 61 of flexible circuit 60, which comprises an insulating substrate (¶¶ [0032]-[0034]; Figs. 1A and 3C). Kim further discloses that flexible circuit 60 includes through holes (conductive vias) 68 extending through the insulating substrate to electrically interconnect conductive circuit layers 64 and 65 (¶ [0034]). As shown in Figures 1A and 3G, the electrical connection from control die 16 extends through conductive via 68 provided in flexible circuit 60, through conductive pin terminal 38, and to conductive pad 24 on substrate 20, thereby teaching a control chip mounted on the top surface of an insulating substrate and electrically connected through a through hole provided in the insulating substrate.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Ishimatsu, as modified by Muto, by mounting the control chip on the top surface of Muto's insulating substrate using Kim's through-via interconnection structure. Kim teaches that conductive vias formed through the insulating substrate electrically interconnect the control die with underlying conductive structures while permitting the control die to remain mounted on the upper surface of the insulating substrate. Applying Kim's known through-via interconnection technique to the combined Ishimatsu/Muto device would have predictably provided compact three-dimensional electrical routing while maintaining reliable electrical connection between the control chip and the first die pad through the conductive circuitry.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Ishimatsu et al. (US 20210217741) in view of Muto et al. (US 20190035745), and further in view of Kessler et al. (US 20220093573).
Regarding claim 5. Ishimatsu in view of Muto discloses The semiconductor device according to claim 1. But Ishimatsu in view of Muto does not expressly disclose wherein the at least one control chip is mounted to a top surface of the first die pad in an opening provided in the insulating substrate.
However, Kessler discloses control chip 14 embedded within electrically insulating core layer 20, such that the lateral sides of control chip 14 are surrounded by core layer 20 (¶ [0047]; Figs. 2A and 2B). Figures 2A and 2B further illustrate that control chip 14 is received within an opening defined by insulating core layer 20 and interfaces with first redistribution layer 23, thereby teaching a control chip disposed within an opening provided in an insulating substrate.
Although Kessler does not expressly disclose mounting control chip 14 directly on a first die pad, Ishimatsu teaches mounting control chip 4G directly on first base portion 55, corresponding to the claimed first die pad. It would have been obvious to one of ordinary skill in the art to modify the semiconductor package of Ishimatsu, as modified by Muto, by forming the insulating substrate with the chip-receiving opening taught by Kessler while retaining Ishimatsu's direct mounting of the control chip on the first die pad. The resulting structure would position the control chip on the top surface of the first die pad within the opening of the insulating substrate, as recited in claim 5.
A person of ordinary skill in the art would have been motivated to make this modification because Kessler teaches embedding the control chip within an insulating substrate to provide a compact semiconductor package while enabling redistribution routing around the control chip. Incorporating Kessler's chip-embedding configuration into the Ishimatsu/Muto semiconductor package would have predictably reduced package size, improved layout flexibility for the conductive routing patterns, and preserved the direct mounting of the control chip on the first die pad. Therefore, the modification would have been no more than the predictable application of a known chip-embedding technique to obtain its recognized advantages. Accordingly, claim 5 would have been obvious over Ishimatsu in view of Muto and Kessler.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Changhyun Yi whose telephone number is (571)270-7799. The examiner can normally be reached Monday-Friday: 10A-3P.
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/Changhyun Yi/Primary Examiner, Art Unit 2812
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