DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 11,502,053 to Bhushan et al. (hereinafter Bhushan) in view of Lee et al. (US 2023/0139378, hereinafter Lee) and Muroga (US 2022/0130746).
With respect to claims 1 and 14, Bhushan discloses a semiconductor package (Bhushan, Figs. 3A-3B, Col. 1, lines 5-8; Col. 3, lines 66-67; Col. 4, lines 1-67; Col. 5, lines 1-4) comprising:
a substrate (310) (Bhushan, Figs. 3A-3B, Col. 4, lines 30-41) having a first side (e.g., a left top side) and a second side (e.g., a right top side) opposing each other;
a plurality of pads (e.g., bond pads 332 of the contact section 330) (Bhushan, Figs. 3A-3B, Col. 4, lines 19-41) disposed on the substrate (310),
wherein the plurality of pads (332) include first bonding pads arranged adjacent to the first side (e.g., the left side in Fig. 3B), second bonding pads arranged adjacent to the second side (the right side in Fig. 3B);
an insulation layer (350) (Bhushan, Figs. 3A-3B, Col. 4, lines 38-41) disposed on the substrate (310);
wherein the insulation layer (350) exposes the first bonding pads (332, on the left side in Fig. 3B) and the second bonding pads (332, on the right side in Fig. 3B);
a first chip structure (e.g., a first stack 205a) (Bhushan, Figs. 3A-3B, Col. 4, lines 1-18) disposed on the insulation layer (350) adjacent to the first side and electrically connected to the first bonding pads (332, on the left side in Fig. 3B);
a second chip structure (e.g., a first stack 205b) (Bhushan, Figs. 3A-3B, Col. 4, lines 1-18) disposed on the insulation layer (350) adjacent to the second side and electrically connected to the second bonding pads (332, on the right side in Fig. 3B);
a controller (340) (Bhushan, Figs. 3A-3B, Col. 4, lines 32-38) disposed on the substrate (310) between the first chip structure (205a) and the second chip structure (205b), the controller (340) includes a plurality of connection pads in a lower portion of the controller.
Further, Bhushan does not specifically disclose (1) upper pads disposed between the first bonding pads and the second bonding pads; (2) a passivation layer disposed on the substrate, a solder resist layer disposed on the passivation layer of the substrate; a first chip structure disposed on the solder resist layer; a second chip structure disposed on the solder resist layer; a controller disposed on the solder resist layer; and a connection structure penetrating the passivation layer and the solder resist layer, and electrically connecting the controller and the upper pads, wherein at least a portion of the connection structure has a horizontal width decreasing as a distance from the controller increases within the passivation layer and the solder resist layer (as claimed in claim 1); wherein the solder resist layer includes a photosensitive resin composition (as claimed in claim 14).
Regarding (1), Lee teaches a semiconductor package (Lee, Fig. 2A, ¶0031-¶0039, ¶0052) comprising a controller chip (210) (Lee, Fig. 2A, ¶0033-¶0034) between the first chip stack (230A) and the second chip stack (230B) on a substrate (200) including upper substrate pads, wherein the controller chip (210) is connected to the substrate through various interconnects and including connections electrodes (212) disposed between the first bonding pad (202A) and the second bonding pad (202B), to provide improved package integrating different types of memories and controller and having reduced area and thickness (Lee, ¶0052).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor package Bhushan by forming upper substrate pads connected to the first chip stack and the second chip stack, and the controller chip disposed between the first chip stack and the second chip stack as taught by Lee to have the semiconductor package, comprising: upper pads disposed between the first bonding pads and the second bonding pads, in order to provide improved package integrating different types of memories and controller and having reduced area and thickness (Lee, ¶0033-¶0034, ¶0052).
Regarding (2), Muroga teaches forming a wiring substrate (Muroga, Figs. 1A-1B, 2, 7, 10, ¶0004-¶0005, ¶0018-¶0081, ¶0084-¶0090, ¶0096-¶0108) to mount a semiconductor element on the wiring substrate, wherein the wiring substrate (20) (Muroga, Figs. 1A-1B, 2, 7, 10, ¶0019-¶0020) comprises a passivation layer (40) (Muroga, Figs. 1A-1B, 2, 7, 10, ¶0026-¶0028) disposed on the substrate (20), a solder resist layer (60) (Muroga, Figs. 1A-1B, 2, 7, 10, ¶0030-¶0031) comprised of a photosensitive resin (e.g., epoxy resin) and disposed on the passivation layer (40) of the substrate (20); a chip structure (81) (Muroga, Figs. 1A-1B, 2, ¶0057-¶0058) including a combination of multiple memory chips and logic chip disposed on the solder resist layer (60), wherein the chip structure (81) including the logic chip disposed on the solder resist layer (60); and a connection structure (e.g., via 51/71) (Muroga, Figs. 1A-1B, 2, ¶0046-¶0047) penetrating the passivation layer (40) and the solder resist layer (60), and electrically connecting the logic chip (81) and the upper pads (31) of the substrate (20), wherein at least a portion of the connection structure (via 71/51) has a horizontal width decreasing as a distance from the logic chip (81) increases within the passivation layer (40) and the solder resist layer (60), to provide improved connection structure with improved reliability and effectively limited separation of vis wiring from the wiring substrate (Muroga, ¶0078-¶0080).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor package Bhushan by forming a wiring substrate including a connection structure as taught by Muroga to have the semiconductor package, comprising: a passivation layer disposed on the substrate, a solder resist layer disposed on the passivation layer of the substrate; a first chip structure disposed on the solder resist layer; a second chip structure disposed on the solder resist layer; a controller disposed on the solder resist layer; and a connection structure penetrating the passivation layer and the solder resist layer, and electrically connecting the controller and the upper pads, wherein at least a portion of the connection structure has a horizontal width decreasing as a distance from the controller increases within the passivation layer and the solder resist layer (as claimed in claim 1); wherein the solder resist layer includes a photosensitive resin composition (as claimed in claim 14), in order to provide a semiconductor element on the wiring substrate including improved connection structure with improved reliability and effectively limited separation of via wiring from the wiring substrate (Muroga, ¶0004-¶0005, ¶0078-¶0080).
Regarding claims 2-4, Bhushan in view of Lee and Muroga discloses the semiconductor package of claim 1. Further, Bhushan does not specifically disclose the semiconductor package, wherein a lower surface of the controller is in contact with an upper surface of the solder resist layer (as claimed in claim 2); wherein the solder resist layer has a protrusion protruding from the upper surface of the solder resist layer and contacting at least a portion of a side surface of the controller (as claimed in claim 3); wherein a lower surface of the controller is spaced apart from an upper surface of the solder resist layer (as claimed in claim 4).
However, Muroga teaches forming the wiring substrate, wherein a lower surface of the logic chip (81) is in contact with an upper surface of the solder resist layer (60), wand herein the solder resist layer (60) has a protrusion (e.g., a portion of the epoxy resin 85 is interpreted as a protrusion of the solder resist ayer 60 also including epoxy resin) (Muroga, Figs. 1A-1B, 2, ¶0030, ¶0061) protruding from the upper surface of the solder resist layer (60) and contacting at least a portion of a side surface of the logic chip (81), and wherein a lower surface of the logic chip (81) is spaced apart from an upper surface of the solder resist layer (60) and filled with epoxy resin material (85).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor package Bhushan/Lee/Muroga by forming the solder resist layer comprised of specific material, such as epoxy resin surrounding low portions of the chip as taught by Muroga to have the semiconductor package, wherein the semiconductor package, wherein a lower surface of the controller is in contact with an upper surface of the solder resist layer (as claimed in claim 2); wherein the solder resist layer has a protrusion protruding from the upper surface of the solder resist layer and contacting at least a portion of a side surface of the controller (as claimed in claim 3); wherein a lower surface of the controller is spaced apart from an upper surface of the solder resist layer (as claimed in claim 4), in order to provide a semiconductor element on the wiring substrate including improved connection structure with improved reliability and effectively limited separation of via wiring from the wiring substrate (Muroga, ¶0004-¶0005, ¶0078-¶0080).
Regarding claim 5, Bhushan in view of Lee and Muroga discloses the semiconductor package of claim 1. Further, Bhushan does not specifically disclose the semiconductor package, wherein the connection structure includes, a first structure convex in a first direction between a lower surface of the controller and an upper surface of the solder resist layer; and a second structure extending from a lower surface of the first structure in a second direction perpendicular to the first direction, wherein a width of the second structure in the first direction decreases as a distance from the lower surface of the first structure increases.
However, Muroga teaches the connection structure (70/50) (Muroga, Figs. 1A-1B, 2, ¶0051-¶0053) including, a first structure (e.g., post 75 on the via 71) as a rod-shaped connection portion in a first direction (horizontal direction) between a lower surface of the logic chip (81) and an upper surface of the solder resist layer (60); and a second structure (71/51) extending from a lower surface of the first structure (75) in a second direction (e.g., a vertical direction) perpendicular to the first direction, wherein a width of the second structure (71) in the first direction decreases as a distance from the lower surface of the first structure (75) increases.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor package Bhushan/Lee/Muroga by forming the connection structure including a post structure on the via as taught by Muroga to have the semiconductor package, wherein the connection structure includes, a first structure convex in a first direction between a lower surface of the controller and an upper surface of the solder resist layer; and a second structure extending from a lower surface of the first structure in a second direction perpendicular to the first direction, wherein a width of the second structure in the first direction decreases as a distance from the lower surface of the first structure increases, in order to provide improved connection structure with improved reliability and effectively limited separation of via wiring from the wiring substrate (Muroga, ¶0030, ¶0061, ¶0078-¶0080).
Regarding claim 6, Bhushan in view of Lee and Muroga discloses the semiconductor package of claim 1. Further, Bhushan does not specifically disclose the semiconductor package, wherein the solder resist layer includes a first portion interposed between the passivation layer and the controller, and a second portion disposed between the passivation layer and the first chip structure and between the passivation layer and the second chip structure, and an upper surface of the second portion is at substantially a same level as an upper surface of the first portion or is at a higher level than the upper surface of the first portion.
However, Muroga teaches forming a wiring substrate (Muroga, Figs. 1A-1B, 2, 7, 10, ¶0004-¶0005, ¶0018-¶0081, ¶0084-¶0090, ¶0096-¶0108) to mount a semiconductor element on the wiring substrate, wherein the chip structure (81) (Muroga, Figs. 1A-1B, 2, ¶0057-¶0058) includes a combination of multiple memory chips and logic chip disposed on the solder resist layer (60), and the solder resist layer (60) includes a first portion interposed between the passivation layer (40) and the logic chip (81), and a second portion disposed on the passivation layer (40) on the left side of the logic chip (81) and on the right side of the logic chip (81), and an upper surface of the second portion is at substantially a same level as an upper surface of the first portion.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor package Bhushan/Lee/Muroga by forming the chip structure including a combination of multiple memory chips and logic chip disposed on the solder resist layer as taught by Muroga to have the semiconductor package, wherein the solder resist layer includes a first portion interposed between the passivation layer and the controller, and a second portion disposed between the passivation layer and the first chip structure and between the passivation layer and the second chip structure, and an upper surface of the second portion is at substantially a same level as an upper surface of the first portion or is at a higher level than the upper surface of the first portion, in order to provide improved connection structure with improved reliability and effectively limited separation of via wiring from the wiring substrate (Muroga, ¶0030, ¶0061, ¶0078-¶0080).
Regarding claim 7, Bhushan in view of Lee and Muroga discloses the semiconductor package of claim 1. Further, Bhushan discloses the semiconductor package, wherein the first chip structure (e.g., a first stack 205a) (Bhushan, Figs. 3A-3B, Col. 4, lines 1-18) includes a plurality of first semiconductor chips (200) with first pads (e.g., bond pads 232, of the first bond section 230) disposed on each upper surface, and the second chip structure (205b) includes a plurality of second semiconductor chips (200) with second pads (e.g., bond pads 232, of the second bond section 230) disposed on each upper surface, wherein the plurality of first semiconductor chips (200) are stacked and sequentially offset (e.g., staircase-type configuration) (Bhushan, Figs. 3A-3B, Col. 4, lines 2-41) in a first direction (e.g., offset direction 315a) and the first pads are adjacent to the first side, and the plurality of second semiconductor chips (200) are stacked and sequentially offset (e.g., offset direction 315b) opposite to the first direction (315a) and the second pads are adjacent to the second side.
Regarding claim 8, Bhushan in view of Lee and Muroga discloses the semiconductor package of claim 7. Further, Bhushan discloses the semiconductor package, further comprising a first bonding wire structure (e.g., 234, on the left side) (Bhushan, Figs. 3A-3B, Col. 4, lines 19-41) connecting the first pads (232) and the first bonding pads (332), and a second bonding wire structure (234, on the right side) connecting the second pads (232) and the second bonding pads (332).
Regarding claim 9, Bhushan in view of Lee and Muroga discloses the semiconductor package of claim 1. Further, Bhushan discloses the semiconductor package, wherein the first chip structure (e.g., a first stack 205a) (Bhushan, Figs. 3A-3B, Col. 4, lines 1-18) includes a plurality of first semiconductor chips (200) stacked and sequentially offset (e.g., staircase-type configuration) (Bhushan, Figs. 3A-3B, Col. 4, lines 2-41) from the first side in a first direction (e.g., offset direction 315a), and the second chip structure (205b) includes a plurality of second semiconductor chips (200) stacked and sequentially offset from the second side (e.g., offset direction 315b) opposite to the first direction (315a), and a lowest first semiconductor chip among the plurality of first semiconductor chips (e.g., first chip 200 of the first stack 205a) and a lowest second semiconductor chip (e.g., first chip 200 of the second stack 205b) among the plurality of second semiconductor chips are spaced apart from a side surface of the controller (340) by a first distance in the first direction (e.g., horizontal direction).
Regarding claims 10 and 11, Bhushan in view of Lee and Muroga discloses the semiconductor package of claim 9. Further, Bhushan discloses the semiconductor package, wherein a first semiconductor chip (e.g., a second chip 200 from the top of the first stack 205a) (Bhushan, Figs. 3A-3B, Col. 4, lines 1-18) stacked on an upper surface of the lowest first semiconductor chip (200) and a second semiconductor chip(e.g., a second chip 200 from the top of the second stack 205b) stacked on an upper surface of the lowest second semiconductor chip overlap at least a portion of an upper surface of the controller (340) in a second direction (e.g., vertical direction) perpendicular to the first direction, and are spaced from the upper surface of the controller (340) by a second distance, but does not specifically disclose that a second distance greater than the first distance in the second direction (as claimed in claim 10); wherein the first distance is about 50um to 100um or less, and the second distance is about 100um to 150um or less (as claimed in claim 11).
However, Bhushan teaches that an arrangement of the bond pads (Bhushan, Figs. 3A-3B, Col. 3, lines 2-22; Col. 4, lines 42-67; Col. 5, lines 1-4) and the slits of the semiconductor dies (200) of the first and second stacks (205a /205b) and the thickness of the semiconductor dies (200) define the position of the controller, and thus the first distance and the second distance between the side surface and the upper surface of the controller and the respective semiconductor dies (200) of the first and second stacks (205a/205b). Specifically, the thickness of the semiconductor dies (200) is less than 50 um to have more dies in the stacks and reduced memory device package size while preventing failure of the semiconductor dies due to the stress.
Thus, Bhushan recognizes that the arrangement of the bond pads and the slits, and the thickness of the semiconductor dies impact the first distance and the second distance between the side surface and the upper surface of the controller and the respective semiconductor dies, and size of the memory device package, and the reliability of the package. Thus, the arrangement of the bond pads and the slits, and the thickness of the semiconductor dies are result-effective variables.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, the arrangement of the bond pads and the slits, and the thickness of the semiconductor dies as Bhushan has identified the arrangement of the bond pads and the slits, and the thickness of the semiconductor dies as result-effective variables. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at specific arrangement of the bond pads and the slits, and the thickness of the semiconductor dies, such that a second distance greater than the first distance in the second direction (as claimed in claim 10); wherein the first distance is about 50um to 100um or less, and the second distance is about 100um to 150um or less (as claimed in claim 11), in order to provide more dies in the stacks and reduced memory device package size while preventing failure of the semiconductor dies due to the stress as taught by Bhushan (Col. 3, lines 2-22; Col. 4, lines 58-67; Col. 5, lines 1-4) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor package Bhushan/Lee/Muroga by optimizing the arrangement of the bond pads and the slits, and the thickness of the semiconductor dies as taught by Bhushan to have the semiconductor package, wherein a second distance greater than the first distance in the second direction (as claimed in claim 10); wherein the first distance is about 50um to 100um or less, and the second distance is about 100um to 150um or less (as claimed in claim 11), in order to provide more dies in the stacks and reduced memory device package size while preventing failure of the semiconductor dies due to the stress (Bhushan, Col. 3, lines 2-22; Col. 4, lines 58-67; Col. 5, lines 1-4).
Regarding claim 12, Bhushan in view of Lee and Muroga discloses the semiconductor package of claim 1. Further, Bhushan discloses the semiconductor package, wherein the first chip structure (e.g., a first stack 205a) (Bhushan, Figs. 3A-3B, Col. 4, lines 1-18) includes a plurality of first semiconductor chips (200) stacked and sequentially offset (e.g., staircase-type configuration) (Bhushan, Figs. 3A-3B, Col. 4, lines 2-41) from the first side in a first direction (e.g., a horizontal direction in Fig. 3B), and the second chip structure (205b) includes a plurality of second semiconductor chips (200) stacked and sequentially offset from the second side opposite to the first direction, and a distance between a lowest first semiconductor chip (200) among the plurality of first semiconductor chips (of the first stack 205a) and a lowest second semiconductor chip (200) among the plurality of second semiconductor chips (of the second stack 205b) in the first direction is less than a horizontal width of the controller (340).
Regarding claim 13, Bhushan in view of Lee and Muroga discloses the semiconductor package of claim 12. Further, Bhushan discloses the semiconductor package, wherein a highest first semiconductor chip (200) among the plurality of first semiconductor chips (of the first stack 205a) and a highest second semiconductor chip (200) among the plurality of second semiconductor chips (of the second stack 205b) are spaced apart from each other by a distance, but does not specifically disclose that a distance is of about 100um to 200um or less in the first direction.
However, Bhushan teaches that an arrangement of the bond pads (Bhushan, Figs. 3A-3B, Col. 3, lines 2-22; Col. 4, lines 42-67; Col. 5, lines 1-4) and the slits of the semiconductor dies (200) of the first and second stacks (205a /205b) and the thickness of the semiconductor dies (200) define the position of the controller, and thus a distance between the respective semiconductor dies (200) of the first and second stacks (205a/205b). Specifically, the thickness of the semiconductor dies (200) is less than 50 um to have more dies in the stacks and reduced memory device package size while preventing failure of the semiconductor dies due to the stress.
Thus, Bhushan recognizes that the arrangement of the bond pads and the slits, and the thickness of the semiconductor dies impact a distance between the respective semiconductor dies, and the reliability of the package. Thus, the arrangement of the bond pads and the slits, and the thickness of the semiconductor dies are result-effective variables.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, the arrangement of the bond pads and the slits, and the thickness of the semiconductor dies as Bhushan has identified the arrangement of the bond pads and the slits, and the thickness of the semiconductor dies as result-effective variables. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at specific arrangement of the bond pads and the slits, and the thickness of the semiconductor dies, such that a distance is of about 100um to 200um or less in the first direction, in order to provide more dies in the stacks and reduced memory device package size while preventing failure of the semiconductor dies due to the stress as taught by Bhushan (Col. 3, lines 2-22; Col. 4, lines 58-67; Col. 5, lines 1-4) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor package Bhushan/Lee/Muroga by optimizing the arrangement of the bond pads and the slits, and the thickness of the semiconductor dies as taught by Bhushan to have the semiconductor package, wherein a distance is of about 100um to 200um or less in the first direction, in order to provide more dies in the stacks and reduced memory device package size while preventing failure of the semiconductor dies due to the stress (Bhushan, Col. 3, lines 2-22; Col. 4, lines 58-67; Col. 5, lines 1-4).
With respect to claim 15, Bhushan discloses a semiconductor package (Bhushan, Figs. 3A-3B, Col. 1, lines 5-8; Col. 3, lines 66-67; Col. 4, lines 1-67; Col. 5, lines 1-4) comprising:
a substrate (310) (Bhushan, Figs. 3A-3B, Col. 4, lines 30-41) including edge pads (e.g., bond pads 332 of the contact section 330) (Bhushan, Figs. 3A-3B, Col. 4, lines 19-41), and an insulation layer (350) (Bhushan, Figs. 3A-3B, Col. 4, lines 38-41) having openings exposing the edge pads (332);
at least one controller (340) (Bhushan, Figs. 3A-3B, Col. 4, lines 32-38); and
at least one pair of chip structures (e.g., stacks 205a/205b each including a plurality of semiconductor dies 200) disposed on the insulation layer (350) and spaced apart from each other with the at least one controller (340) disposed between the at least one pair of chip structures (205a/205b),
wherein the at least one pair of chip structures (e.g., stacks 205a/205b) 9Bhushan, Figs. 3A-3B, Col. 4, lines 19-41) includes upper surface pads (232) electrically connected to the edge pads (332).
Further, Bhushan does not specifically disclose (1) upper pads; (2) a passivation layer having openings; a solder resist layer disposed on the passivation layer of the substrate and including open regions exposing the openings, the open regions of the solder resist layer have a width greater than a width of the openings of the passivation layer; at least one controller having an active surface with connection pads disposed thereon and a non-active surface opposite to the active surface, the active surface facing an upper surface of the solder resist layer; a plurality of connection structures disposed between the at least one controller and the upper pads of the substrate and electrically connecting the connection pads of the at least one controller and the upper pads of the substrate; and at least one pair of chip structures disposed on the solder resist layer.
Regarding (1), Lee teaches a semiconductor package (Lee, Fig. 2A, ¶0031-¶0039, ¶0052) comprising a controller chip (210) (Lee, Fig. 2A, ¶0033-¶0034) between the first chip stack (230A) and the second chip stack (230B) on a substrate (200) including upper substrate pads, wherein the controller chip (210) is connected to the substrate through various interconnects and including connections electrodes (212) disposed between the first bonding pad (202A) and the second bonding pad (202B), to provide improved package integrating different types of memories and controller and having reduced area and thickness (Lee, ¶0052).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor package Bhushan by forming upper substrate pads connected to the first chip stack and the second chip stack, and the controller chip disposed between the first chip stack and the second chip stack as taught by Lee to have the semiconductor package, comprising: a substrate including upper pads, in order to provide improved package integrating different types of memories and controller and having reduced area and thickness (Lee, ¶0033-¶0034, ¶0052).
Regarding (2), Muroga teaches forming a wiring substrate (Muroga, Figs. 1A-1B, 2, 7, 10, ¶0004-¶0005, ¶0018-¶0081, ¶0084-¶0090, ¶0096-¶0108) to mount a semiconductor element on the wiring substrate, wherein the wiring substrate (20) (Muroga, Figs. 1A-1B, 2, 7, 10, ¶0019-¶0020) comprises a passivation layer (40) (Muroga, Figs. 1A-1B, 2, 7, 10, ¶0026-¶0028) disposed on the substrate (20) and having openings exposing edge pads (e.g., 31), a solder resist layer (60) (Muroga, Figs. 1A-1B, 2, 7, 10, ¶0030-¶0031) comprised of a photosensitive resin (e.g., epoxy resin) and disposed on the passivation layer (40) of the substrate (20); a chip structure (81) (Muroga, Figs. 1A-1B, 2, ¶0057-¶0058) including a combination of multiple memory chips and logic chip disposed on the solder resist layer (60), wherein the solder resist layer (60) includes open regions (62) Muroga, Figs. 1A-1B, 2, ¶0032-¶0033) exposing the openings (41) of the passivation layer (40), the open regions (62) of the solder resist layer (60) have a width greater than a width of the openings (41) of the passivation layer (40); at least one logic chip (81) (Muroga, Figs. 1A-1B, 2, ¶0057-¶0058) having an active surface (e.g., a lower surface) with connection pads (82) disposed thereon and a non-active surface (e.g., top surface) opposite to the active surface, the active surface facing an upper surface of the solder resist layer (60); a plurality of connection structures (e.g., via 51/71) (Muroga, Figs. 1A-1B, 2, ¶0046-¶0047) disposed between the at least one logic chip (81) and the upper pads (31) of the substrate (20) and electrically connecting the connection pads (82) of the at least one logic chip (81) and the upper pads (31) of the substrate (20); wherein multiple memory chips and logic chip (Muroga, Figs. 1A-1B, 2, ¶0058) are disposed on the solder resist layer (60), to provide improved connection structure with improved reliability and effectively limited separation of vis wiring from the wiring substrate (Muroga, ¶0078-¶0080).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor package Bhushan by forming a wiring substrate including a plurality of connection structures as taught by Muroga to have the semiconductor package, comprising: a passivation layer having openings; a solder resist layer disposed on the passivation layer of the substrate and including open regions exposing the openings, the open regions of the solder resist layer have a width greater than a width of the openings of the passivation layer; at least one controller having an active surface with connection pads disposed thereon and a non-active surface opposite to the active surface, the active surface facing an upper surface of the solder resist layer; a plurality of connection structures disposed between the at least one controller and the upper pads of the substrate and electrically connecting the connection pads of the at least one controller and the upper pads of the substrate; and at least one pair of chip structures disposed on the solder resist layer, in order to provide a semiconductor element on the wiring substrate including improved connection structure with improved reliability and effectively limited separation of via wiring from the wiring substrate (Muroga, ¶0004-¶0005, ¶0078-¶0080).
Regarding claim 16, Bhushan in view of Lee and Muroga discloses the semiconductor package of claim 15. Further, Bhushan discloses the semiconductor package, further comprising a bonding wire structure (e.g., 234, on the left side) (Bhushan, Figs. 3A-3B, Col. 4, lines 19-41) connecting the edge pads (332) of the substrate and the upper surface pads (232) of the at least one pair of chip structures (205a/205b).
Regarding claim 17, Bhushan in view of Lee and Muroga discloses the semiconductor package of claim 15. Further, Bhushan does not specifically disclose that the solder resist layer and the passivation layer further include first open portions penetrating through the solder resist layer and the passivation layer to expose the upper pads of the substrate, and the plurality of connection structures are disposed within the first open portions.
However, Muroga teaches the wiring substrate (10), wherein the solder resist layer (60) and the passivation layer (40) further include first open portions (62/41) (Muroga, Figs. 1A-1B, 2, 7, 10, ¶0032-¶0033,¶0047-¶0053) penetrating through the solder resist layer (60) and the passivation layer (40) to expose the upper pads (31) of the substrate (20), and the plurality of connection structures (e.g., vias 51/71) are disposed within the first open portions (62/41).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor package Bhushan/Lee/Muroga by forming the connection structure including the vias as taught by Muroga to have the semiconductor package, wherein the solder resist layer and the passivation layer further include first open portions penetrating through the solder resist layer and the passivation layer to expose the upper pads of the substrate, and the plurality of connection structures are disposed within the first open portions, in order to provide a semiconductor element on the wiring substrate including improved connection structure with improved reliability and effectively limited separation of via wiring from the wiring substrate (Muroga, ¶0004-¶0005, ¶0078-¶0080).
Regarding claim 18, Bhushan in view of Lee and Muroga discloses the semiconductor package of claim 15. Further, Bhushan does not specifically disclose that the solder resist layer and the passivation layer include first open portions penetrating the solder resist layer and the passivation layer to expose the upper pads of the substrate, the solder resist layer includes a second open portion on the first open portions and having a horizontal width greater than a horizontal width of the first open portions, the at least one controller is disposed in the second open portion, and the plurality of connection structures are disposed within the first open portions.
However, Muroga teaches the wiring substrate (10), wherein the solder resist layer (60) and the passivation layer (40) include first open portions (62/41) (Muroga, Figs. 1A-1B, 2, 7, 10, ¶0032-¶0033,¶0047-¶0053) penetrating the solder resist layer (60) and the passivation layer (40) to expose the upper pads (31) of the substrate (20), the solder resist layer (60) includes a second open portion (e.g., the recess in the epoxy resin 85 is interpreted as a second open portion of the solder resist layer comprised the same epoxy resin material) (Muroga, Figs. 1A-1B, 2, 7, 10, ¶0030,¶0061) on the first open portions (62) and having a horizontal width greater than a horizontal width of the first open portions (62), the at least one logic chip (81) is disposed in the second open portion (e.g., the recess in the resin 85), and the plurality of connection structures (e.g., via 51/71) (Muroga, Figs. 1A-1B, 2, 7, 10, ¶0047-¶0053) are disposed within the first open portions (62/41).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor package Bhushan/Lee/Muroga by forming the solder resist layer comprises of portions of epoxy resin material surrounding the logic chip as taught by Muroga to have the semiconductor package, wherein the solder resist layer and the passivation layer include first open portions penetrating the solder resist layer and the passivation layer to expose the upper pads of the substrate, the solder resist layer includes a second open portion on the first open portions and having a horizontal width greater than a horizontal width of the first open portions, the at least one controller is disposed in the second open portion, and the plurality of connection structures are disposed within the first open portions, in order to provide a semiconductor element on the wiring substrate with improved reliability (Muroga, ¶0030, ¶0061, ¶0078-¶0080).
With respect to claim 19, Bhushan discloses a semiconductor package (Bhushan, Figs. 3A-3B, Col. 1, lines 5-8; Col. 3, lines 66-67; Col. 4, lines 1-67; Col. 5, lines 1-4) comprising:
a substrate (310) (Bhushan, Figs. 3A-3B, Col. 4, lines 30-41) including edge pads (e.g., bond pads 332 of the contact section 330) (Bhushan, Figs. 3A-3B, Col. 4, lines 19-41) on an upper portion;
an insulation layer (350) (Bhushan, Figs. 3A-3B, Col. 4, lines 38-41) disposed on the substrate (310) and exposing the edge pads (332);
at least one controller (340) (Bhushan, Figs. 3A-3B, Col. 4, lines 32-38); and
at least one pair of chip structures (e.g., stacks 205a/205b each including a plurality of semiconductor dies 200) disposed on the insulation layer (350), spaced apart from each other with the at least one controller (340) disposed between the at least one pair of chip structures (205a/205b), the at least one pair of chip structures (e.g., stacks 205a/205b) (Bhushan, Figs. 3A-3B, Col. 4, lines 19-41) includes upper surface pads (232) disposed on each upper surface; and
a bonding wire structure (234) (Bhushan, Figs. 3A-3B, Col. 4, lines 19-41) electrically connecting the upper surface pads (232) of the at least one pair of respective chip structures (205a/205b) and the edge pads (332) of the substrate (310).
Further, Bhushan does not specifically disclose (1) upper pads; (2) a first solder resist layer disposed on the substrate and exposing the edge pads; a second solder resist layer disposed on the first solder resist layer and having a step from the first solder resist layer; at least one controller disposed on the second solder resist layer and including a plurality of connection pads disposed in a lower portion of the at least one controller; at least one pair of chip structures disposed on the second solder resist layer; a connection structure penetrating the first solder resist layer and the second solder resist layer and electrically connecting the plurality of connection pads of the at least one controller and the upper pads of the substrate.
Regarding (1), Lee teaches a semiconductor package (Lee, Fig. 2A, ¶0031-¶0039, ¶0052) comprising a controller chip (210) (Lee, Fig. 2A, ¶0033-¶0034) between the first chip stack (230A) and the second chip stack (230B) on a substrate (200) including upper substrate pads, wherein the controller chip (210) is connected to the substrate through various interconnects and including connections electrodes (212) disposed between the first bonding pad (202A) and the second bonding pad (202B), to provide improved package integrating different types of memories and controller and having reduced area and thickness (Lee, ¶0052).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor package Bhushan by forming upper substrate pads connected to the first chip stack and the second chip stack, and the controller chip disposed between the first chip stack and the second chip stack as taught by Lee to have the semiconductor package, comprising: a substrate including upper pads, in order to provide improved package integrating different types of memories and controller and having reduced area and thickness (Lee, ¶0033-¶0034, ¶0052).
Regarding (2), Muroga teaches forming a wiring substrate (Muroga, Figs. 1A-1B, 2, 7, 10, ¶0004-¶0005, ¶0018-¶0081, ¶0084-¶0090, ¶0096-¶0108) to mount a semiconductor element on the wiring substrate, wherein the wiring substrate (20) (Muroga, Figs. 1A-1B, 2, 7, 10, ¶0019-¶0020) comprises a first solder resist layer (60) disposed on the substrate (20) and exposing the edge pads (e.g., 31), a second solder resist layer (e.g. resin layer 85 including the same epoxy resin material as a solder resist layer 60 is interpreted as a second solder resist layer) (Muroga, Figs. 1A-1B, 2, 7, 10, ¶0030, ¶0061) disposed on the first solder resist layer (60) and having a step from the first solder resist layer; at least one chip structure (81) (Muroga, Figs. 1A-1B, 2, ¶0057-¶0058) including a combination of multiple memory chips and logic chip disposed on the second solder resist layer (85) and including a plurality of connection pads (82) disposed in a lower portion of the at least one chip (81), a connection structure (e.g., via 51/71) (Muroga, Figs. 1A-1B, 2, ¶0046-¶0047) penetrating the first solder resist layer (60) and the second solder resist layer (85) and electrically connecting the plurality of connection pads (82) of the at least one chip (81) and the upper pads of the substrate, to provide improved connection structure with improved reliability and effectively limited separation of vis wiring from the wiring substrate (Muroga, ¶0078-¶0080).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor package Bhushan by forming a wiring substrate including a first solder resist layer and a second solder resist layer on the first solder resist layer as taught by Muroga to have the semiconductor package, comprising: a first solder resist layer disposed on the substrate and exposing the edge pads; a second solder resist layer disposed on the first solder resist layer and having a step from the first solder resist layer; at least one controller disposed on the second solder resist layer and including a plurality of connection pads disposed in a lower portion of the at least one controller; at least one pair of chip structures disposed on the second solder resist layer; a connection structure penetrating the first solder resist layer and the second solder resist layer and electrically connecting the plurality of connection pads of the at least one controller and the upper pads of the substrate, in order to provide a semiconductor element on the wiring substrate including improved connection structure with improved reliability and effectively limited separation of via wiring from the wiring substrate (Muroga, ¶0004-¶0005, ¶0078-¶0080).
Regarding claim 20, Bhushan in view of Lee and Muroga discloses the semiconductor package of claim 19. Further, Bhushan does not specifically disclose that the substrate further includes a wiring circuit electrically connecting the edge pads and the upper pads, and the at least one controller is electrically connected to the at least one pair of chip structures through the connection structure and the wiring circuit.
However, Lee teaches that the substrate (200) (Lee, Fig. 2, ¶0033-¶0035) further includes a wiring circuit (204a/204b) electrically connecting the edge pads (202a/202b) to the power electrodes (240), and the at least one controller (210) is electrically connected to the at least one pair of chip structures (230A/230B).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor package Bhushan/Lee/Muroga by forming connections between at least one controller chip and to the chip stacks through the wiring substrate including wiring structures extending in the vertical and horizontal direction as taught by Lee to have the semiconductor package, wherein the substrate further includes a wiring circuit electrically connecting the edge pads and the upper pads, and the at least one controller is electrically connected to the at least one pair of chip structures through the connection structure and the wiring circuit, in order to provide improved package integrating different types of memories and controller and having reduced area and thickness (Lee, ¶0033-¶0034, ¶0052).
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 11,502,053 to Bhushan in view of Lee (US 2023/0139378), Park et al. (US 2021/0384143, hereinafter Park), and Chen et al. (US 2025/0022810, hereinafter Chen).
With respect to claim 19, Bhushan discloses a semiconductor package (Bhushan, Figs. 3A-3B, Col. 1, lines 5-8; Col. 3, lines 66-67; Col. 4, lines 1-67; Col. 5, lines 1-4) comprising:
a substrate (310) (Bhushan, Figs. 3A-3B, Col. 4, lines 30-41) including edge pads (e.g., bond pads 332 of the contact section 330) (Bhushan, Figs. 3A-3B, Col. 4, lines 19-41) on an upper portion;
an insulation layer (350) (Bhushan, Figs. 3A-3B, Col. 4, lines 38-41) disposed on the substrate (310) and exposing the edge pads (332);
at least one controller (340) (Bhushan, Figs. 3A-3B, Col. 4, lines 32-38); and
at least one pair of chip structures (e.g., stacks 205a/205b each including a plurality of semiconductor dies 200) disposed on the insulation layer (350), spaced apart from each other with the at least one controller (340) disposed between the at least one pair of chip structures (205a/205b), the at least one pair of chip structures (e.g., stacks 205a/205b) (Bhushan, Figs. 3A-3B, Col. 4, lines 19-41) includes upper surface pads (232) disposed on each upper surface; and
a bonding wire structure (234) (Bhushan, Figs. 3A-3B, Col. 4, lines 19-41) electrically connecting the upper surface pads (232) of the at least one pair of respective chip structures (205a/205b) and the edge pads (332) of the substrate (310).
Further, Bhushan does not specifically disclose (1) upper pads; (2) a first solder resist layer disposed on the substrate and exposing the edge pads; a second solder resist layer disposed on the first solder resist layer and having a step from the first solder resist layer; at least one controller disposed on the second solder resist layer and including a plurality of connection pads disposed in a lower portion of the at least one controller; at least one pair of chip structures disposed on the second solder resist layer; a connection structure penetrating the first solder resist layer and the second solder resist layer and electrically connecting the plurality of connection pads of the at least one controller and the upper pads of the substrate.
Regarding (1), Lee teaches a semiconductor package (Lee, Fig. 2A, ¶0031-¶0039, ¶0052) comprising a controller chip (210) (Lee, Fig. 2A, ¶0033-¶0034) between the first chip stack (230A) and the second chip stack (230B) on a substrate (200) including upper substrate pads, wherein the controller chip (210) is connected to the substrate through various interconnects and including connections electrodes (212) disposed between the first bonding pad (202A) and the second bonding pad (202B), to provide improved package integrating different types of memories and controller and having reduced area and thickness (Lee, ¶0052).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor package Bhushan by forming upper substrate pads connected to the first chip stack and the second chip stack, and the controller chip disposed between the first chip stack and the second chip stack as taught by Lee to have the semiconductor package, comprising: a substrate including upper pads, in order to provide improved package integrating different types of memories and controller and having reduced area and thickness (Lee, ¶0033-¶0034, ¶0052).
Regarding (2), Park teaches forming a semiconductor package (Park, Fig. 3, ¶0005-¶0008, ¶0032-¶0090) including a wiring substrate (100/200) and at least one semiconductor chip (301-310) disposed on the wiring substrate (100/200), wherein the wiring substrate includes a first solder resist layer (130) (Park, Fig. 3, ¶0067-¶0068) disposed on the substrate (100) and including edge openings exposing the edge circuit patterns (e.g., 135) and a second passivation layer (e.g., 210/240) (Park, Fig. 3, ¶0076-¶0082) disposed on the first solder resist layer (130) and having a step from the first solder resist layer (130); at least one chip structure (301-310) including a controller (Park, Fig. 3, ¶0044) is disposed on the second passivation layer (210/240) and including a plurality of connection pads (e.g., 315/325) (Park, Fig. 3, ¶0083) disposed in a lower portion of the at least one chip (e.g., 301/302), a connection structure (e.g., solder 20/30) (Park, Fig. 3, ¶0078, ¶0085) penetrating the first solder resist layer (130) and the second passivation layer (210/240) and electrically connecting the plurality of connection pads (315/325) of the at least one chip (e.g., 301-302) and the upper pads (135) of the substrate (100), to provide reliable connection structure for the semiconductor package (Park, ¶0005-¶0006, ¶0090).
Further, Chen teaches a passivation layer (110) (Chen, Fig. 14, ¶0043-¶0044, ¶0052-¶0053) comprised of a solder resist material, to provide a protective coating for the package substrate and to inhibit solder material adhering to the outer surface of the package substrate during solder reflow process (Chen, ¶0052).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor package Bhushan by forming a wiring substrate including a first solder resist layer and a passivation layer on the first solder resist layer as taught by Park, wherein the passivation layer includes a solder resist material as taught by Chen such that the passivation layer functions as a second resist layer to have the semiconductor package, comprising: a first solder resist layer disposed on the substrate and exposing the edge pads; a second solder resist layer disposed on the first solder resist layer and having a step from the first solder resist layer; at least one controller disposed on the second solder resist layer and including a plurality of connection pads disposed in a lower portion of the at least one controller; at least one pair of chip structures disposed on the second solder resist layer; a connection structure penetrating the first solder resist layer and the second solder resist layer and electrically connecting the plurality of connection pads of the at least one controller and the upper pads of the substrate, in order to provide reliable connection structure for the semiconductor package; to provide a protective coating for the package substrate and to inhibit solder material adhering to the outer surface of the package substrate during solder reflow process (Park, ¶0005-¶0006, ¶0090; Chen, ¶0043-¶0044, ¶0052).
Regarding claim 20, Bhushan in view of Lee, Park, and Chen discloses the semiconductor package of claim 19. Further, Bhushan does not specifically disclose that the substrate further includes a wiring circuit electrically connecting the edge pads and the upper pads, and the at least one controller is electrically connected to the at least one pair of chip structures through the connection structure and the wiring circuit.
However, Lee teaches that the substrate (200) (Lee, Fig. 2, ¶0033-¶0035) further includes a wiring circuit (204a/204b) electrically connecting the edge pads (202a/202b) to the power electrodes (240), and the at least one controller (210) is electrically connected to the at least one pair of chip structures (230A/230B).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor package Bhushan/Lee/Muroga by forming connections between at least one controller chip and to the chip stacks through the wiring substrate including wiring structures extending in the vertical and horizontal direction as taught by Lee to have the semiconductor package, wherein the substrate further includes a wiring circuit electrically connecting the edge pads and the upper pads, and the at least one controller is electrically connected to the at least one pair of chip structures through the connection structure and the wiring circuit, in order to provide improved package integrating different types of memories and controller and having reduced area and thickness (Lee, ¶0033-¶0034, ¶0052).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 11,502,053 to Bhushan in view of Lee (US 2023/0139378), Park (US 2021/0384143), and Chen (US 2025/0022810) as applied to claim 19, and further in view of Tsai et al. (US 2021/0057346, hereinafter Tsai).
Regarding claim 20, Bhushan in view of Lee, Park, and Chen discloses the semiconductor package of claim 19. Further, Bhushan does not specifically disclose that the substrate further includes a wiring circuit electrically connecting the edge pads and the upper pads, and the at least one controller is electrically connected to the at least one pair of chip structures through the connection structure and the wiring circuit.
However, Lee teaches that the substrate (200) (Lee, Fig. 2, ¶0033-¶0035) further includes a wiring circuit (204a/204b) electrically connecting the edge pads (202a/202b) to the power electrodes (240), and the at least one controller (210) is electrically connected to the at least one pair of chip structures (230A/230B).
Further, Tsai teaches forming a package (Tsai, Fig. 1K, ¶0020-¶0033) comprising a substrate further includes a wiring circuit (e.g., redistribution structure including wiring pattern 324A) (Tsai, Fig. 1K, ¶0023, ¶0033) electrically connecting the pads of the chip stack (130) and the upper pads of the controller (100), and the controller (100) is electrically connected to the chip stack through the connection structure (136) and the wiring circuit (324A), to provide reliable semiconductor package including integrated multiple semiconductor devices having better electrical performance and reduced size (Tsai, ¶0001, ¶0015, ¶0020, ¶0023, ¶0033, ¶0041).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor package Bhushan/Lee/Muroga by forming connections between at least one controller chip and to the chip stacks through the wiring substrate including wiring structures extending in the vertical and horizontal direction as taught by Lee to have the semiconductor package, wherein the substrate further includes a wiring circuit electrically connecting the edge pads and the upper pads, and the at least one controller is electrically connected to the at least one pair of chip structures through the connection structure and the wiring circuit, in order to provide improved package integrating different types of memories and controller and having reduced area and thickness; to provide reliable semiconductor package including integrated multiple semiconductor devices having better electrical performance and reduced size (Lee, ¶0033-¶0034, ¶0052; Tsai, ¶0001, ¶0015, ¶0020, ¶0023, ¶0033, ¶0041).
Conclusion
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891
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