DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
1. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
2. The information disclosure statement (IDS) submitted on 7/24/2024 was filed prior to the mailing date of this action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
3. The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following features must be shown or the feature(s) canceled from the claim(s).
Claim 1, line 3, “first wafer having a chamfered portion”. Specifically, the drawings do not show a chamfered portion
No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
4. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-3 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, lines 2-3, the language recites “a first wafer having a chamfered portion”. However, it is not precisely clear what is required by this language. The specification refers to elements 20c and 10c in fig. 3b as chamfered portions. However, as seen in fig. 3b, these portions appear to be rounded and not “chamfered”. It is not precisely clear if the language is intended to require a rounded portion or a chamfered portion. As best understood by the examiner, in view of fig. 3b of the instant application, the language will be interpreted as requiring a rounded portion.
Regarding claim 1, lines 4-5, the language recites the phrase “by grinding and thinning the first wafer”. However, it is not precisely clear what this phrase is with respect to. Specifically, it is not clear what the phrase is intended to relate to as it appears the language is misplaced or there is a grammar issue that causes confusion. For purposes of examination, as best understood by the examiner, the language will be interpreted as requiring grinding of the first wafer.
Claims 2-3 are rejected for depending upon a rejected base claim.
Claim Rejections - 35 USC § 103
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Nakamura (US PGPUB 20210159080) in view of Sandoh (US PGPUB 20230066651) and further in view of Sakai (US PGPUB 20210069859).
Regarding claim 1, Nakamura teaches a processing method of a bonded wafer (fig. 1, bonded wafer W), the bonded wafer including a first wafer (fig. 1, wafer 20) having a chamfered portion formed on an outer periphery thereof (see above 35 USC 112(b) rejection for more details. chamfered part 20e, [0030]) and a second wafer (wafer 10) bonded with the first wafer (fig. 1), by grinding and thinning the first wafer (see above 35 USC 112(b) rejection for more details. in fig. 4a-b, the first wafer 20 is ground), the processing method comprising:
a chamfered-portion removing step of holding the bonded wafer on a chuck table of a processing machine (fig. 2a-2c, [0032-0033]) and removing the chamfered portion formed on the outer periphery of the first wafer (fig. 2a-2c, [0033]);
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a grinding step (fig. 4a-4b) of holding the bonded wafer on the side of the second wafer on a chuck table (see annotated fig. 4b above, chuck table 41 holds second wafer 10) of a grinding machine and grinding the first wafer (fig. 4a-4b).
Nakamura does not explicitly teach
a protective film arrangement step of arranging a protective film on a side of the second wafer;
a chamfered-portion removing step of holding the bonded wafer on a side of the protective film on a chuck table of a processing machine configured to remove the chamfered portion and removing the chamfered portion formed on the outer periphery of the first wafer;
a rinsing step of rinsing the bonded wafer from which the chamfered portion has been removed;
a peeling step of peeling off the protective film from the second wafer.
However, Sandoh teaches a method of manufacturing chips including applying a protective film 21 (fig. 3a), holding a wafer on a chuck table via the protective film (fig. 4b), processing an end chamfer of the wafer (fig. 4b), then peeling the protective film 21 after processing (fig. 7a, protective film 21 is removed). Overall, Sandoh teaches
a protective film arrangement step of arranging a protective film on a side of the wafer (fig. 3a, protective member 21);
a chamfered-portion removing step of holding the bonded wafer on a side of the protective film on a chuck table of a processing machine (fig. 4b) configured to remove the chamfered portion and removing the chamfered portion formed on the outer periphery of the first wafer (fig. 4b);
a peeling step of peeling off the protective film from the wafer (fig. 7a, [0089]).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Nakamura to incorporate the teachings of Sandoh to provide
a protective film arrangement step of arranging a protective film on a side of the second wafer;
a chamfered-portion removing step of holding the bonded wafer on a side of the protective film on a chuck table of a processing machine configured to remove the chamfered portion and removing the chamfered portion formed on the outer periphery of the first wafer;
a peeling step of peeling off the protective film from the second wafer.
Specifically, it would have been obvious to modify Nakamura to incorporate the teachings of Sandoh to provide applying a protective member to the wafer that is held on the chuck table during the processing of fig. 2b of Nakamura and then removing the protective member after the processing of fig. 2b. Doing so would promote quality of the workpiece and prevent damage to the workpiece. Additionally, doing so would protect the workpiece surface being held for later processing steps, which promotes consistent and uniform processing and quality of the workpiece.
Nakamura, as modified, does not explicitly teach
a rinsing step of rinsing the bonded wafer from which the chamfered portion has been removed.
However, Sakai teaches a wafer processing apparatus, wherein the wafer is subjected to grinding (fig. 1), wherein the wafer is also passed through a cleaning unit 70 that cleans the wafer after processing by a cleaning liquid such as purified water [0036]. Specifically, Sakai teaches the wafer for which the grinding processing and the polishing processing have been executed is conveyed from the chuck table to the cleaning unit by the conveying unit. Then, the wafer after the processing is cleaned by the cleaning unit [0050]. Overall, Sakai teaches a rinsing step of rinsing the bonded wafer (the wafer and protective component are rinsed via the cleaning liquid including purified water of the cleaning unit [0036 and 0050]) after the wafer has been subjected to grinding [0036 and 0050]).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have further modified Nakamura, as modified, to incorporate the teachings of Sakai to provide a rinsing step of rinsing the bonded wafer from which the chamfered portion has been removed. Specifically, it would have been obvious to provide a rinsing step of rinsing the bonded workpiece of Nakamura, as modified, after the chamfer removing operation. Doing so would promote cleanliness, promote quality for subsequent processing steps, and also prevent damage to the workpiece due to leftover debris.
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura (US PGPUB 20210159080) in view of Sandoh (US PGPUB 20230066651) and further in view of Sakai (US PGPUB 20210069859), as applied to claim 1 above, and further in view of Harada et al. (US PGPUB 20200343095), hereinafter Harada.
Regarding claim 2, Nakamura, as modified, teaches the claimed invention as rejected above in claim 1. Additionally, Nakamura teaches the second wafer contains any one of silicon (Nakamura teaches wafer 10 includes a silicon substrate [0029]), sapphire, quarts, or glass (The prior art is not required to teach these limitations because the language recites the term “or”).
Nakamura, as modified, does not explicitly teach wherein the first wafer contains any one of lithium tantalate or lithium niobate.
However, Harada teaches a stacked wafer processing method, wherein the stacked wafer can include a wafer formed of silicon or may be a generally known wafer such as a sapphire substrate, a glass substrate, and a lithium niobate substrate. Further, the stacked wafer is not limited to a stacked wafer formed by combining wafers of a same material and may be formed by combining wafers of different materials [0022].
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have further modified Nakamura, as modified, to incorporate the teachings of Harada to provide wherein the first wafer contains lithium niobate. Specifically, it would have been obvious to incorporate the teachings of Harada and provide wherein the stacked wafer of Nakamura, as modified, includes being formed by combining wafers of different materials including wherein the first wafer contains lithium niobate and the second wafer contains silicon. Doing so would have been a simple substitution (MPEP 2143) of one known wafer material for another known wafer material to obtain the predictable results of providing a stacked wafer having a known wafer material. Additionally, doing so would continue to allow the device to function as intended and perform as a stacked wafer.
Regarding claim 3, Nakamura, as modified, teaches the claimed invention as rejected above in claim 1. Nakamura, as modified, does not explicitly teach wherein, in the protective film arrangement step, the protective film is a thermocompression bonding film.
However, Harada teaches a stacked wafer processing method, wherein the stacked wafer is subjected to a protective member 20 (fig. 2a), wherein the protective member 20 is a thermocompression bonding sheet [0025].
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have further modified Nakamura, as modified, to incorporate the teachings of Harada to provide wherein, in the protective film arrangement step, the protective film is a thermocompression bonding film. Specifically, it would have been obvious to incorporate wherein the protective film of Nakamura, as modified, is a thermocompression bonding film. Doing so would have been a simple substitution (MPEP 2143) of one known protecting member configuration for another known protecting member configuration. Additionally, doing so would allow the device to function as intended and prevent the workpiece from damage.
Conclusion
6. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yamanaka (US PGPUB 20220072680) teaches a wafer grinding method of grinding a periphery of a workpiece similar to the claimed invention.
Priewasser (US PGPUB 20130115861) teaches a processing method for a wafer with periphery processing similar to the claimed invention
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL A GUMP whose telephone number is (571)272-2172. The examiner can normally be reached Monday- Friday 9:00-5:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, David Posigian can be reached at (313) 446-6546. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL A GUMP/Primary Examiner, Art Unit 3723
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