Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. (see MPEP § 606.01).
This may result in slightly longer titles, but the loss in brevity of title will be more than offset by the gain in its informative value in indexing, classifying, searching, etc.
The following title is suggested:
“Memory Device Package Having a Recessed or Cutout Substrate for Receiving a Stack of Memory Chips”
Because the disclosure and the independent claims are directed to a memory device package in which a substrate having a recess or cutout receives a stack of memory chips to reduce the overall package height. The suggested title more accurately identifies the statutory class of the invention and the principal inventive feature disclosed and claimed.
Specification
The disclosure is objected to because of the following informalities:
1. Paragraph [0005]
Issue: Typographical error
Current language:
"...the conductive wire is configure to couple the chip pad and one of the plurality of substrate pads electrically."
Objection:
The specification is objected to because paragraph [0005] contains a typographical error. Specifically, the phrase "is configure to couple" should be amended to "is configured to couple." Appropriate correction is required.
2. Paragraph [0008]
Issue: Typographical error
Current language:
"...the first conductive wire is attached to both the front surface and the stack of memory chip. The first conductive wire is attached..."
(The singular "memory chip" should be plural.)
Objection:
The specification is objected to because paragraph [0008] contains a grammatical error. Specifically, the phrase "stack of memory chip" should be amended to "stack of memory chips." Appropriate correction is required.
3. Paragraph [0009]
Current language:
"...The conductive wire is configure to couple..."
Objection:
The specification is objected to because paragraph [0009] contains a typographical error. Specifically, the phrase "is configure to couple" should be amended to "is configured to couple." Appropriate correction is required.
4. Paragraph [0010]
Current language:
"...receiving the stack of memory devices..."
The application consistently discusses a stack of memory chips, not memory devices.
Objection:
The specification is objected to because paragraph [0010] contains inconsistent terminology. Specifically, the phrase "receiving the stack of memory devices" appears inconsistent with the remainder of the disclosure, which consistently refers to a stack of memory chips. Appropriate correction is required for consistency.
5. Paragraph [0011]
Current language:
"...The conductive wire is configure to couple..."
Objection:
The specification is objected to because paragraph [0011] contains a typographical error. Specifically, the phrase "is configure to couple" should be amended to "is configured to couple." Appropriate correction is required.
6. Paragraph [0039]
Current language:
"...the conductive wire is configure to couple..."
Objection:
The specification is objected to because paragraph [0039] contains a typographical error. Specifically, the phrase "is configure to couple" should be amended to "is configured to couple." Appropriate correction is required.
7. Paragraph [0048]
Current language:
"...the stack of memory chips are partially disposed..."
Subject is singular.
Objection:
The specification is objected to because paragraph [0048] contains a grammatical error. Specifically, the phrase "the stack of memory chips are" should be amended to "the stack of memory chips is." Appropriate correction is required.
8. Paragraph [0059]
Current language:
"...The stack of memory chips is partially sits inside the recess..."
Objection:
The specification is objected to because paragraph [0059] contains a grammatical error. Specifically, the phrase "is partially sits" should be amended for proper grammatical construction, for example, to "partially sits" or "is partially disposed." Appropriate correction is required.
9. Paragraph [0065]
Current language:
"...The conductive wire is configure..."
Objection:
The specification is objected to because paragraph [0065] contains a typographical error. Specifically, the phrase "is configure" should be amended to "is configured." Appropriate correction is required.
10. Paragraph [0077]
Current language:
"...The conductive wire is configure..."
Objection:
The specification is objected to because paragraph [0077] contains a typographical error. Specifically, the phrase "is configure to couple" should be amended to "is configured to couple." Appropriate correction is required.
Appropriate correction is required.
Claim Objections
Claim 1 is objected to because it contains a typographical error. The phrase:
"...the conductive wire is configure to couple..."
should read:
"...the conductive wire is configured to couple..."
Claim 17 is objected to because it contains a grammatical error. The phrase:
"an NAND die"
should be amended to:
"a NAND die."
Claim 20 is objected to because the phrase "to partially fill the portion of the removed portion of the device substrate" contains redundant language and lacks clarity. Specifically, the recitation "the portion of the removed portion" should be revised for clarity.
One acceptable amendment would be:
"...receiving the stack of memory chips via the front opening of the front surface to partially fill the removed portion of the device substrate..."
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5-8, 11-12, 17 and 19-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Park et al. (US 20240047328).
Regarding claim 1. Park discloses a memory device comprising:
a stack of memory chips including a first memory chip, as shown by memory chip stack 200, including the lowermost memory chip 212 (Fig. 1B; ¶¶ [0033]-[0035]),
wherein the first memory chip further includes a chip pad formed on a first surface of the first memory chip, as shown by chip pad 220 formed on the upper (first) surface of memory chip 212 (Fig. 1B; ¶ [0035]),
a device substrate including a plurality of substrate pads, as shown by device substrate 100 including a plurality of upper connection pads 122P1a disposed on the upper/front surface of the substrate (Fig. 1B; ¶ [0046]),
wherein the plurality of substrate pads are formed on a front surface of the device substrate, as shown in Fig. 1B, where the upper connection pads 122P1a are disposed on the upper (front) surface of device substrate 100 (Fig. 1B; ¶ [0046]), and
the front surface has a front opening, as shown by opening 100R formed from the front (upper) surface of device substrate 100, the opening extending downward into the substrate to accommodate the memory chip stack (Fig. 1B; ¶ [0037]),
wherein the device substrate receives the stack of memory chips via the front opening of the front surface, as shown in Fig. 1B, where memory chip stack 200 is received within opening 100R formed in the front surface of device substrate 100, such that the stack is accommodated by the opening extending from the front surface into the substrate (Fig. 1B; ¶¶ [0037], [0046]), and
a conductive wire coupled to the front surface and the stack of memory chips, as shown by bonding wire 230 extending between the chip stack and the front surface of the device substrate (Fig. 1B; ¶ [0046]),
wherein the conductive wire is configured to electrically couple the chip pad and one of the plurality of substrate pads, as disclosed by bonding wire 230 electrically connecting chip pad 220 of memory chip 212 to one of the upper connection pads 122P1a disposed on the front surface of device substrate 100 (Fig. 1B; ¶ [0046]).
Regarding claim 2. Park discloses The memory device of claim 1, wherein the device substrate includes a recess, as shown by recess 100R formed in device substrate 100 to receive the stack of memory chips (Fig. 1B; ¶¶ [0037], [0046]), having a top edge defined by the front opening of the front surface, as shown in Fig. 1B, where recess 100R opens at the front (upper) surface of device substrate 100, thereby defining the top edge of the recess by the front opening (Fig. 1B; ¶ [0037]), and
the stack of memory chips is partially disposed in the recess, as shown in Fig. 1B, where memory chip stack 200 is received within recess 100R, with an upper portion of the stack projecting beyond the recess while a lower portion is accommodated therein, such that the stack is partially disposed in the recess (Fig. 1B; ¶¶ [0037], [0046]).
Regarding claim 3. Park discloses The memory device of claim 2, wherein the first memory chip sits on, and contacts, a bottom surface of the recess, as shown in Fig. 1B, where the lowermost memory chip 212 is disposed within recess 100R of device substrate 100. Figure 1B illustrates that the lower surface of the lowermost memory chip 212 directly rests on the bottom surface of recess 100R, with no intervening structure therebetween, thereby teaching that the first memory chip sits on and contacts the bottom surface of the recess (Fig. 1B; ¶¶ [0033], [0037]).
Regarding claim 5. Park discloses The memory device of claim 1, wherein the stack of memory chips includes a first set of memory chips, as shown by memory chip stack 200, including a plurality of stacked memory chips 210, wherein the lowermost memory chip 212 corresponds to the claimed first memory chip (Fig. 1B; ¶¶ [0033]-[0035]), and the first set of memory chips are spatially offset with one another along a first direction in a stair-like manner, as shown in Fig. 1B, where the memory chips 210 are arranged in a stacked configuration with each successive memory chip laterally offset relative to the adjacent memory chip in a common direction. This progressive lateral offset forms a stair-like arrangement that exposes portions of the respective memory chips, including chip pads 220, for electrical connection by bonding wires 230 (Fig. 1B; ¶¶ [0033]-[0035]).
Regarding claim 6. Park discloses The memory device of claim 5, wherein the stack of memory chips further includes a second set of memory chips attached to the first set of memory chips, as shown by memory chip stack 200 including a plurality of stacked memory chips 210 arranged in two opposing stair-step groups that together form the stack (Fig. 1B; ¶¶ [0033]-[0035]), and
the second set of memory chips are spatially offset with one another along a second direction in a stair-like manner, the second direction opposite to the first direction, as shown in Fig. 1B, where the memory chips of one stair-step group are progressively offset in a first lateral direction to expose chip pads 220 on one side of the stack, while the memory chips of the opposing stair-step group are progressively offset in the opposite lateral direction to expose chip pads 220 on the opposite side of the stack. Accordingly, the second set of memory chips is spatially offset with one another in a second direction opposite the first direction, as claimed (Fig. 1B; ¶¶ [0033]-[0035]).
Regarding claim 7. Park discloses The memory device of claim 6, wherein each of the first set of memory chips and the second set of memory chips includes at least one respective chip pad that is not covered by any memory chip, as shown in Fig. 1B, where the opposing stair-like arrangement of memory chips 210 exposes chip pads 220 on the respective memory chips. The exposed portions of chip pads 220 are not overlapped or covered by adjacent memory chips, thereby remaining accessible for electrical connection by bonding wires 230 (Fig. 1B; ¶¶ [0033]-[0035], [0046]), and
the at least one respective chip pad of the first set of memory chips and the at least one respective chip pad of the second set of memory chips are disposed in proximity to two opposite edges of the front opening of the front surface of the device substrate, respectively, as shown in Fig. 1B, where the exposed chip pads 220 of the first and second sets of memory chips are positioned adjacent opposite side edges of opening 100R formed in the front surface of device substrate 100. The exposed chip pads 220 are electrically connected to corresponding upper connection pads 122P1a on the front surface of device substrate 100 through bonding wires 230, demonstrating that the chip pads are disposed in proximity to the opposite edges of opening 100R (Fig. 1B; ¶ [0046]).
Regarding claim 8. Park discloses The memory device of claim 5, wherein one of the first set of memory chips includes at least one respective chip pad that is not covered by any memory chip, as shown in Fig. 1B, where the stair-like arrangement of memory chips 210 exposes chip pads 220 on the respective memory chips. The exposed chip pad 220 is not overlapped or covered by an adjacent memory chip, thereby remaining accessible for electrical connection (Fig. 1B; ¶¶ [0033]-[0035]), and
the at least one respective chip pad is coupled to at least one respective substrate pad on the front surface of the device substrate via at least one respective conductive wire, as shown in Fig. 1B, where bonding wire 230 electrically connects exposed chip pad 220 of the memory chip to upper connection pad 122P1a disposed on the front surface of device substrate 100 (Fig. 1B; ¶ [0046]). Accordingly, Park discloses one of the first set of memory chips having an exposed chip pad that is electrically coupled to a substrate pad on the front surface of the device substrate via a conductive wire, as recited in claim 8.
Regarding claim 11. Park discloses The memory device of claim 1, further comprising a molding component at least partially covering the front surface of the device substrate and a top surface of the stack of memory chips and conformally filling a space between the device substrate and the stack of memory chips, as shown by molding member 400, which encapsulates the memory chip stack 200, covers the front surface of device substrate 100, covers the top surface of the memory chip stack, and fills the spaces surrounding and between the device substrate and the memory chip stack (Fig. 1B; ¶ [0047]).
Regarding claim 12. Park discloses The memory device of claim 1, further comprising a support component attached to a rear surface of the device substrate, which is opposite to the front surface, and a bottom surface of the stack of memory chips, as shown in Figure 1B by bottom solder resist layer 134. Park discloses that bottom solder resist layer 134 covers the bottom surface of the lowermost base insulating layer 110 (¶ [0034]). As shown in Figure 1B, bottom solder resist layer 134 is attached to the rear surface of device substrate 100, opposite the front surface, and is attached to the bottom surface of the memory chip stack. Accordingly, bottom solder resist layer 134 corresponds to the claimed support component. Accordingly, Park discloses the support component attached to the rear surface of the device substrate and the bottom surface of the stack of memory chips, as recited in claim 12.
Regarding claim 17. Park discloses The memory device of claim 1, wherein the first memory chip includes a NAND die including a plurality of NAND memory cells, as taught by memory chip stack 200 including memory chips 210, which are NAND flash memory dies. Accordingly, the first memory chip is a NAND die including a plurality of NAND memory cells. (See, e.g., ¶ [0039] and related disclosure identifying the memory chip stack as NAND flash memory.)
Regarding claim 19. Park discloses The memory device of claim 1, wherein the front opening of the front surface includes three edges, and two of the three edges are connected to an edge of the device substrate, as shown in Figures 1A and 1B, wherein opening 100R is formed in the front surface of package base substrate 100 and is bounded by three edges, with two of the three edges connected to an outer edge of package base substrate 100, thereby forming an opening that opens to the edge of the substrate. Accordingly, Park discloses the front opening including three edges, with two of the three edges connected to an edge of the device substrate, as recited in claim 19.
Regarding claim 20. Park discloses A method [0015], [0141], comprising:
providing a device substrate including a plurality of substrate pads, wherein the plurality of substrate pads are formed on a front surface of the device substrate, and the front surface has a front opening, as taught by package base substrate 100 including upper connection pads 122P1a formed on the front surface of package base substrate 100, wherein the front surface includes recess (opening) 100R;
removing a portion of the device substrate to create one of a recess and a cutout opening, as evidenced by recess 100R formed in package base substrate 100, which necessarily results from removing a portion of the device substrate to create the recess;
providing a stack of chips including a first memory chip, wherein the first memory chip further includes a chip pad formed on a first surface of the first memory chip, as taught by memory chip stack 200 including lowermost memory chip 212 having chip pad 220 formed on a first surface of the lowermost memory chip;
receiving the stack of memory chips via the front opening of the front surface to partially fill the portion of the removed portion of the device substrate, as shown in Figures 1A and 1B, wherein memory chip stack 200 is received through opening 100R into recess 100R of package base substrate 100 such that the memory chip stack partially fills the recess; and
applying a conductive wire to couple the chip pad of the first memory chip and one of the plurality of substrate pads of the device substrate, as taught by bonding wire 230 electrically connecting chip pad 220 of lowermost memory chip 212 to upper connection pad 122P1a of package base substrate 100. Accordingly, Park discloses the method of claim 20.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20240047328) in view of Gibbons et al. (US 20190279964).
Regarding claim 4. Park discloses The memory device of claim 1. However, Park does not expressly disclose that the opening is a cutout opening extending through the entire thickness of the device substrate, as recited in claim 4.
Gibbons discloses wherein the device substrate includes a cutout opening that goes through an entire thickness of the device substrate, as shown by module substrate 102 including aperture 110 extending through substrate material 103 from first surface 106a to second surface 106b. Gibbons further teaches that aperture 110 extends to a depth D, wherein the depth D generally equals the thickness of module substrate 102, thereby teaching a cutout opening extending through the entire thickness of the device substrate, and has a top edge defined by the front opening of the front surface, as shown in Fig. 4, where aperture 110 opens at first surface 102a of module substrate 102, thereby defining the top edge of the cutout opening at the front surface of the substrate, and the stack of memory chips is disposed in the cutout opening, as shown in Fig. 4, where microelectronic package 404, including a plurality of stacked semiconductor dies 130, is disposed within aperture 110, substantially occupying the aperture, and surrounded by the device substrate, as shown in Fig. 4, where aperture 110 is bounded by substrate material 103 such that microelectronic package 404 is received within, and laterally surrounded by, module substrate 102.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Park by replacing Park's recess with the through-cutout opening taught by Gibbons so that the memory chip stack is received within a cutout extending through the entire thickness of the substrate. Such a modification would have predictably yielded the benefit expressly taught by Gibbons, namely, reducing the overall thickness of the semiconductor package by receiving the microelectronic package within the substrate while accommodating a larger number of stacked semiconductor dies.
Accordingly, it would have been obvious to modify Park to include the through-cutout opening of Gibbons, resulting in the claimed device substrate having a cutout opening extending through the entire thickness of the substrate, wherein the stack of memory chips is disposed within the cutout opening and surrounded by the device substrate.
Claims 9-10 are rejected under 35 U.S.C. §103 as being unpatentable over Park et al. (US 20240047328) in view of Hong et al. (US 20170170156).
Regarding claim 9. Park discloses The memory device of claim 5, However, Park does not expressly disclose the first set of memory chips being spatially offset with one another along a third direction in a stair-like manner, wherein the third direction is perpendicular to the first direction.
Hong teaches a memory chip structure including a plurality of stacked memory chips 110 and 130, wherein each upper memory chip is laterally shifted relative to an underlying memory chip to expose chip pads 117 and 137. Hong further teaches a lower group (LG) of memory chips 110 and an upper group (UG) of memory chips 130, each arranged in a stair-like configuration, with the upper group stacked on the lower group to form a multi-directional staggered memory chip structure.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park's stair-like memory chip arrangement to incorporate the additional staggered arrangement taught by Hong so that the memory chips are spatially offset in an additional direction, thereby exposing additional portions of the chip pads for wire bonding and improving routing flexibility and electrical interconnection in a high-density stacked memory package.
Accordingly, the combination of Park and Hong teaches or at least suggests the first set of memory chips being spatially offset with one another along a third direction in a stair-like manner, the third direction being perpendicular to the first direction, as recited in claim 9.
Regarding claim 10. Park in view of Hong discloses The memory device of claim 9, Hong further teaches: each of the first set of memory chips includes two chip pads that are disposed in proximity to two connected edges of the respective memory chip and not covered by any memory chip, as shown in Figure 4, where the lower group (LG) of memory chips includes exposed chip pads 117 that are uncovered by the overlying memory chips due to the stair-like arrangement of the memory chips. The chip pads are positioned adjacent the edges of the respective memory chips to facilitate wire bonding.
and the two chip pads are coupled to two substrate pads on the front surface of the device substrate via two conductive wires, respectively, as shown in Figure 4, where two bonding wires 125L electrically connect the exposed chip pads 117 of the lower group (LG) to two substrate pads 105 on the package substrate 100. Hong further teaches that the bonding wires provide chip-to-substrate electrical connections between the memory chips and the package substrate.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Park to incorporate Hong's multi-pad, multi-wire bonding arrangement in order to provide additional electrical interconnection paths, improve routing flexibility, and facilitate wire bonding in a high-density stacked memory package.
Claims 13-16 are rejected under 35 U.S.C. §103 as being unpatentable over Park et al. (US 20240047328) in view of Jensen et al. (US 20110180919).
Regarding claim 13. Park discloses The memory device of claim 12, However, Park does not expressly disclose a plurality of conductive vias, each conductive via extending throughout a thickness of the device substrate and a thickness of the support component, each conductive via being exposed from a rear surface of the support component.
Jensen teaches: a plurality of conductive vias, each conductive via extending throughout a thickness of the device substrate and a thickness of the support component, each conductive via being exposed from a rear surface of the support component, as shown in Figure 3A by electrically conductive vias 32 extending through package base 26, including tiers 27 and bottom layer 29, to electrical contacts 37 exposed on bottom surface 36. Jensen discloses that package base 26 includes a multi-tiered structure defined by a plurality of tiers 27, wherein each tier has a different elevation relative to bottom layer 29. Jensen further discloses that electrically conductive vias 32 define electrically conductive pathways extending through package base 26 to electrical contacts 37 positioned on bottom surface 36, thereby extending through both the device substrate and the support component and being exposed from the rear surface of the support component.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park by extending the conductive vias through the support component as taught by Jensen so that the conductive vias are exposed from the rear surface of the support component, thereby enabling electrical connection to external circuitry through the rear surface of the package while maintaining structural support for the memory device.
Regarding claim 14. Park discloses The memory device of claim 12, However, Park does not expressly disclose wherein the support component includes a rigid material.
Jensen teaches: the support component includes a rigid material, as shown in Figure 3A by bottom layer 29, which forms a platform onto which stacked integrated circuits may be placed. Jensen further discloses that package base 26, including tiers 27 and bottom layer 29, may comprise an electrically insulating substrate formed of ceramic materials, such as alumina ceramic, aluminum nitride (AlN), beryllium oxide (BeO), or silicon carbide (SiC), and may comprise multiple substrate layers. Accordingly, bottom layer 29 includes the rigid material of package base 26.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park by forming the support component to include a rigid material as taught by Jensen in order to improve the structural support and mechanical stability of the memory device.
Regarding claim 15. Park discloses The memory device of claim 1, However, Park does not expressly disclose a plurality of conductive vias, each conductive via extending throughout a thickness of the device substrate and from the front surface to a rear surface of the device substrate opposite the front surface.
Jensen teaches: a plurality of conductive vias, each conductive via extending throughout a thickness of the device substrate and from the front surface to a rear surface of the device substrate opposite the front surface, as shown in Figure 3A by electrically conductive vias 32 extending through package base 26 from the surfaces of tiers 27 to electrical contacts 37 exposed on bottom surface 36. Jensen discloses that package base 26 includes a multi-tiered structure defined by a plurality of tiers 27, and that electrically conductive vias 32 define electrically conductive pathways extending through package base 26 to electrical contacts 37 positioned on bottom surface 36.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park by incorporating the through-substrate conductive vias taught by Jensen to electrically route signals from the front surface to the rear surface of the device substrate, thereby facilitating electrical connection of the memory device to external circuitry.
Regarding claim 16. Park discloses The memory device of claim 1, However, Park does not expressly disclose a first via that extends throughout a thickness of the device substrate and from the front surface to a rear surface of the device substrate opposite the front surface, wherein the first via is electrically coupled to the chip pad and one of the plurality of substrate pads.
Jensen teaches: a first via that extends throughout a thickness of the device substrate and from the front surface to a rear surface of the device substrate opposite the front surface, as shown in Figure 5A by electrically conductive via 32A extending through package base 26 from electrical contact 28A disposed on the front surface of tier 27A to electrical contact 37A disposed on bottom surface 36. Figure 5A further shows wire bond 90A electrically connecting integrated circuit 86A to electrical contact 28A, whereby via 32A is electrically coupled to the front-surface electrical contact and extends through the thickness of package base 26 to the rear surface of the package base.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park by incorporating the through-substrate via arrangement taught by Jensen so that the conductive via electrically couples the chip pad and the substrate pad while extending from the front surface to the rear surface of the device substrate, thereby facilitating electrical signal routing and external electrical connection.
Claim 18 is rejected under 35 U.S.C. §103 as being unpatentable over Park et al. (US 20240047328) in view of Kumar et al. (US 20150228621).
Regarding claim 18. Park discloses The memory device of claim 1, However, Park does not expressly disclose a printed circuit board, a memory controller mounted on the printed circuit board, a plurality of planar wires on the printed circuit board electrically coupling the memory chip stack to the memory controller, wherein the memory device is a solid-state drive (SSD), and the memory controller controls the memory chip stack.
Kumar teaches a printed circuit board, as substrate 102 may comprise a printed circuit board (PCB). Kumar further teaches a memory controller, as controller die 24 mounted on substrate 26 in the conventional semiconductor package shown in Figure 1, and further teaches mounting a controller die on substrate 102 after the memory die stacks have been assembled. Kumar also teaches electrical traces 106 and contact pads 108 formed on substrate 102. As shown in Figures 9 and 10, each memory die stack 120 is electrically connected to contact pads 108 on substrate 102 by wire bonds 130, while the controller die is likewise mounted and electrically connected to the same substrate. Kumar further teaches that the finished semiconductor device may be an SSD card. Accordingly, Kumar teaches a printed circuit board having conductive traces and wire bonds electrically coupling the memory die stacks to the memory controller in a solid-state drive.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park by incorporating the printed circuit board and memory controller arrangement taught by Kumar so that the memory chip stack is electrically coupled to the memory controller, thereby enabling the memory package to function as a solid-state drive while allowing the memory controller to control operation of the memory chip stack.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Changhyun Yi whose telephone number is (571)270-7799. The examiner can normally be reached Monday-Friday: 10A-3P.
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/Changhyun Yi/Primary Examiner, Art Unit 2812
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