DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendments filed on 8/27/2024 have been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al’076 (US 2018/0138076) in view of Bao et al (US 2014/0167268), and in further view of Bielefeld et al (US 2008/0073748).
Regarding Claim 1, Yang et al’076 discloses a structure (shown in Fig 13) comprising:
a first conductive feature (via contacts (not shown) are in the substrate 101 [0014] Fig 1);
a metal conductive feature (conductive portions 131 and 132 [0020] Fig 9A) feature over the first conductive feature (via contacts);
a spacer layer (capping layer 138 [0026] Fig 12A) comprising sidewall portions on sidewalls of the metal conductive feature (131 and 132 Fig 12A);
a first dielectric layer (second dielectric layer 140 [0028] Fig 12A) over the spacer layer (138 Fig 12A);
an etch stop layer (etching stop layer 116 [0016] shown in annotated Fig 13) over (in the broadest reasonable interpretation of the word “over”, the etch stop layer 116 can be considered to meet this limitation by being above and does not need to be in contact with the first dielectric layer and the metal conductive feature vertically) the first dielectric layer (140 Fig 12A) and the metal conductive feature (131 and 132 Fig 13);
a second dielectric layer (dielectric layer 170 [0030] Fig 13) over the etch stop layer (116 shown in annotated Fig 13); and
a second conductive feature (conductive lines 161 and 162 [0030] Fig 13) penetrating through the second dielectric layer (170 Fig 13),
wherein the second conductive feature (161 and 162 Fig 13) is over the metal conductive feature (131 and 132 Fig 13).
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Yang et al’076 does not disclose
a graphite conductive feature over and electrically coupling to the first conductive feature;
a dielectric spacer layer comprising sidewall portions on sidewalls of the graphite conductive feature;
a first dielectric layer encircling the sidewall portions of the dielectric spacer layer;
an etch stop layer over the first dielectric layer and the graphite conductive feature; and
wherein the second conductive feature is over and electrically connected to the graphite conductive feature.
Bao et al, in the related art of semiconductor devices that include graphene and metal interconnect structures, discloses
a graphite conductive feature (graphene 30 [0036] Fig 6) over and electrically coupling to the first conductive feature (via 16 [0036] Fig 6);
an etch stop layer (etch stopping layer 25 and 44 [0031] Fig 6) over the first dielectric layer (substrate 12 which is an insulating material [0030] Fig 6) and the graphite conductive feature (30 Fig 6); and
wherein the second conductive feature (via 36 and barrier metal 38 [0032] Fig 6) is over and electrically connected to the graphite conductive feature (30 Fig 6).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Yang et al’076 to include a graphite conductive feature as taught Bao et al in order to have superior current capabilities and thermal conductivity [0003]. Further, a person of ordinary skill in the art would have recognized that having superior current capabilities and thermal conductivity would be advantageous in optimizing the electrical functioning capability of the device when the graphite is electrically connected to the second conductive feature (see MPEP 2143.I(D)). Additionally, a person of ordinary skill in the art would have recognized that having graphite for a conductive feature would be a simple substitution of one known element for another to achieve predictable results (see MPEP 2143.I(B)) (suitable alternate).
The combination of Yang et al’076 and Bao et al now discloses
a dielectric spacer layer (138 Fig 12A Yang et al’076) comprising sidewall portions on sidewalls of the graphite conductive feature (30 Fig 6 Bao et al); and
wherein the second conductive feature (36 and 38 Fig 6 Bao et al/161 and 162 Fig 13 Yang et al’076) is over and electrically connected to the graphite conductive feature (30 Fig 6 Bao et al).
The combination of Yang et al’076 and Bao et al does not disclose
a first dielectric layer encircling the sidewall portions of the dielectric spacer layer.
Bielefeld et al, in the related art of semiconductor devices that include dielectric spacers and metal interconnects, discloses
a first dielectric layer (gap 120 may be comprised of carbon-doped oxide [0023] Fig 1) encircling the sidewall portions of the dielectric spacer layer (dielectric spacer 108 [0024] Fig 1).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Yang et al’076 and Bao et al to include a first dielectric layer encircling the sidewall portions of the dielectric spacer layer as taught by Bielefeld et al in order to isolate the metal interconnects [0023]. Further, a person of ordinary skill in the art would have recognized that having a gap filled with carbon-doped oxide [0023] would be a simple substitution of one known element for another to obtain predictable results (see MPEP 2143.I(B)) (suitable alternate).
Regarding Claim 2, the combination of Yang et al’076, Bao et al, and Bielefeld et al discloses the limitations of claim 1 as explained above. The combination of Yang et al’076, Bao et al, and Bielefeld et al further discloses
wherein the graphite conductive feature (conductive portions 131 and 132 [0020] Fig 9A Yang et al’076/graphene 30 [0036] Fig 6 Bao et al) has a lateral dimension smaller than about 12 nm (the lower width of 131 and 132 is approximately the width of 135b shown in Fig 9B, and may be ranged from about 50 nm to about 3 nm [0034] Yang et al’076).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Yang et al’076, Bao et al, and Bielefeld et a, as applied to claim 1, to include a graphite conductive feature that has a lateral dimension smaller than about 12 nm as taught by Yang et al’076 in order to meet the nanometer technology higher density requirements [0001] and because it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (see MPEP 2144.05).
Regarding Claim 3, the combination of Yang et al’076, Bao et al, and Bielefeld et al discloses the limitations of claim 1 as explained above. The combination of Yang et al’076, Bao et al, and Bielefeld et al further discloses
wherein the dielectric spacer layer (dielectric spacer 108 [0024] Fig 1 Bielefeld et al) further comprises a horizontal portion overlapping the graphite conductive feature (conductive portions 131 and 132 [0020] Fig 9A Yang et al’076/graphene 30 [0036] Fig 6 Bao et al), and
wherein the second conductive feature (conductive lines 161 and 162 [0030] Fig 13 Yang et al’076/via 36 and barrier metal 38 [0032] Fig 6 Bao et al) further penetrates through the horizontal portion (shown in the combination of annotated Fig 1 Bielefeld et al and annotated Fig 6 Bao et al) of the dielectric spacer layer (dielectric spacer 108 [0024] Fig 1 Bielefeld et al).
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Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Yang et al’076 (US 2018/0138076) in view of Bao et al (US 2014/0167268), and Bielefeld et al (US 2008/0073748), and in further view of Yang et al’913 (US 2018/0350913).
Regarding Claim 4, the combination of Yang et al’076, Bao et al, and Bielefeld et al discloses the limitations of claim 1 as explained above. The combination of Yang et al’076, Bao et al, and Bielefeld et al does not disclose
further comprising an amorphous carbon layer over and contacting the graphite conductive feature, wherein the second conductive feature is over and contacts a top surface of the amorphous carbon layer.
Yang et al’913, in the related art of semiconductor devices that include interconnect structures, discloses
further comprising an amorphous carbon layer (amorphous carbon layer 306 [0052] Fig 3) over and contacting the conductive line (103 [0030]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Yang et al’076, Bao et al, and Bielefeld et al to include an amorphous carbon layer and contacting the conductive line as taught by Yang et al’913 in order to improve the reliability of the graphite layer [0026]. Further, a person of ordinary skill in the art would have recognized that improving the reliability of the graphite layer would be advantageous in optimizing the electrical functioning capability of the device while improving the durability and reliability of the device (see MPEP 2143.I(D)).
The combination of Yang et al’076, Bao et al, Bielefeld et al, and Yang et al’913 now discloses
further comprising an amorphous carbon layer (306 Fig 3 Yang et al’913) over and contacting the graphite conductive feature (conductive portions 131 and 132 [0020] Fig 9A Yang et al’076/graphene 30 [0036] Fig 6 Bao et al), wherein the second conductive feature (conductive lines 161 and 162 [0030] Fig 13 Yang et al’076/via 36 and barrier metal 38 [0032] Fig 6 Bao et al) is over and contacts a top surface of the amorphous carbon layer (306 Fig 3 Yang et al’913).
Claims 7 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Elers et al (US 2005/0110145) in view of Bao et al (US 2014/0167268), and in further view of Bielefeld et al (US 2008/0073748).
Regarding Claim 7, Elers discloses a structure comprising:
an integrated circuit [0008];
a dual damascene structure ([0035]-[0041]) comprising:
a metal line (conductor 250 in trench 232 [0056] Fig 20) and a via (via 230 [0050] Fig 19), wherein the dual damascene structure comprises a barrier layer (diffusion barrier 252 [0056] Fig 20) and a copper region (region that contains electrical conductor 250 which may be copper [0057] Fig 20) over the barrier layer (252 Fig 20).
Elers et al does not disclose
a graphite line electrically coupled between the via and the integrated circuit; and
a dielectric spacer layer encircling the graphite line.
Bao et al, in the related art of semiconductor devices that include graphene and metal interconnect structures, discloses
a graphite conductive feature (graphene 30 [0036] Fig 6) over and electrically coupling to the first conductive feature (via 16 [0036] Fig 6).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Elers et al to include a graphite conductive feature as taught Bao et al in order to have superior current capabilities and thermal conductivity [0003]. Further, a person of ordinary skill in the art would have recognized that having superior current capabilities and thermal conductivity would be advantageous in optimizing the electrical functioning capability of the device when the graphite is electrically connected to the second conductive feature (see MPEP 2143.I(D)). Additionally, a person of ordinary skill in the art would have recognized that having graphite for a conductive feature would be a simple substitution of one known element for another to achieve predictable results (see MPEP 2143.I(B)) (suitable alternate).
The combination of Elers et al and Bao et al now discloses
a graphite line (graphene 30 [0036] Fig 6 Bao et al) electrically coupled between the via (via 16 Fig 6 Bao et al) and the integrated circuit (integrated circuit [0008] Elers et al).
The combination of Elers et al an d Bao et al does not disclose
a dielectric spacer layer encircling the graphite line.
Bielefeld et al, in the related art of semiconductor devices that include dielectric spacers and metal interconnects, discloses
a dielectric spacer (dielectric spacer 108 [0024] Fig 1) encircling a conductive feature (metal interconnects 102 and 104 [0018] Fig 1).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Elers et al and Bao et al to include a dielectric spacer layer encircling the conductive feature as taught by Bielefeld et al in order to isolate the metal interconnects [0023]. Further, a person of ordinary skill in the art would have recognized that isolating the metal interconnects would be advantageous in providing insulation to the metal interconnect which would optimize the reliability and durability of the device during operation (see MPEP 2143.I(D)).
The combination of Elers et al, Bao et al, and Bielefeld et al now discloses
a dielectric spacer layer (108 Fig 1 Bielefeld et al) encircling the graphite line (graphene 30 [0036] Fig 6 Bao et al).
Regarding Claim 15, the combination of Elers et al, Bao et al, and Bielefeld et al discloses the limitations of claim 7 as explained above. The combination of Elers et al, Bao et al, and Bielefeld et al further discloses
wherein the dielectric spacer layer (108 Fig 1 Bielefeld et al) comprises a top portion overlapping (shown in Fig 1 Bielefeld et al) the graphite line (graphene 30 [0036] Fig 6 Bao et al).
Regarding Claim 16, the combination of Elers et al, Bao et al, and Bielefeld et al discloses the limitations of claim 15 as explained above. The combination of Elers et al, Bao et al, and Bielefeld et al further discloses
further comprising a via (via 16 [0036] Fig 6 Bao et al/shown in annotated Fig 1 Bielefeld et al) comprising a bottom portion in the top portion of the dielectric spacer layer (108 Fig 1 Bielefeld et al), wherein the via contacts the graphite line (graphene 30 [0036] Fig 6 Bao et al).
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Claims 8 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Elers et al (US 2005/0110145) in view of Bao et al (US 2014/0167268), and Bielefeld et al (US 2008/0073748) and in further view of Yang et al’076 (US 2018/0138076).
Regarding Claim 8, the combination of Elers et al, Bao et al, and Bielefeld et al discloses the limitations of claim 7 as explained above. The combination of Elers et al, Bao et al, and Bielefeld et al does not directly disclose
wherein the graphite has a top width and a bottom width greater than the top width.
Yang et al’076, in the related art of semiconductor devices that include interconnect structures, discloses
wherein the metal conductive line (conductive portions 131 and 132 Fig 9A) has a top width and a bottom width greater than the top width (shown in Fig 9A).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Elers et al, Bao et al, and Bielefeld et al to include wherein the graphite line has a top width and a bottom width greater than the top width as taught by Yang et al’076 in order to have more control over the etching process [0025]. Further, a person of ordinary skill in the art would have recognized that having more control over the etching process would be advantageous in improving the reliability and durability of the device (see MPEP 2143.I(D)).
The combination of Elers et al, Bao et al, Bielefeld et al, and Yang et al’076 now discloses
wherein the graphite line (conductive portions 131 and 132 [0020] Fig 9A Yang et al’076/graphene 30 [0036] Fig 6 Bao et al) has a top width and a bottom width greater than the top width (shown in Fig 9A Yang et al’076).
Regarding Claim 13, the combination of Elers et al, Bao et al, and Bielefeld et al discloses the limitations of claim 7 as explained above. The combination of Elers et al, Bao et al, and Bielefeld et al does not disclose
further comprising a graphite seal ring encircling the graphite line.
Yang et al’076, in the related art of semiconductor devices that include interconnect structures, discloses
further comprising a seal ring (conductive portion 131 [0020] Fig 9A, shown in annotated Fig 13) encircling the conductive line (conductive portion 132 [0020] Fig 9A).
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It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Elers, Bao, and Bielefeld et al include a graphite seal ring encircling the graphite line as taught by Yang et al’076 since it is well known in the art that seal rings provide structural support and protection for the elements in between them. Further, a person of ordinary skill in the art would have recognized that having more structural support and protection would be advantageous in optimizing the reliability and durability of the device (see MPEP 2143.I(D)).
The combination of Elers et al, Bao et al, Bielefeld et al, and Yang et al’076 now discloses
further comprising a graphite seal ring (graphene 30 [0036] Fig 6 Bao et al/conductive portion 131 [0020] Fig 9A, shown above in annotated Fig 13 Yang et al’076) encircling the graphite line (graphene 30 Fig 6 Bao et al/conductive portion 132 [0020] Fig 9A Yang et al’076).
Regarding Claim 14, the combination of Elers et al, Bao et al, Bielefeld et al’ and Yang et al’076 discloses the limitations of claim 13 as explained above. The combination of Elers et al, Bao et al, Bielefeld et al, and Yang et al’076 further discloses
wherein the graphite seal ring (graphene 30 [0036] Fig 6 Bao et al/conductive portion 131 [0020] Fig 9A, shown above in annotated Fig 13 Yang et al’076) and the graphite line (graphene 30 Fig 6 Bao et al/conductive portion 132 [0020] Fig 13 Yang et al’076) comprise top surfaces coplanar with each other, and bottom surfaces coplanar with each other.
Claims 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Elers et al (US 2005/0110145) in view of Bao et al (US 2014/0167268), and Bielefeld et al (US 2008/0073748), and in further view of Yang et al’913 (US 2018/0350913).
Regarding Claim 9, the combination of Elers et al, Bao et al, and Bielefeld et al discloses the limitations of claim 7 as explained above. The combination of Elers et al, Bao et al, and Bielefeld et al does not disclose
further comprising an amorphous carbon layer comprising a top portion over and contacting the graphite line.
Yang et al’913, in the related art of semiconductor devices that include interconnect structures, discloses
further comprising an amorphous carbon layer (amorphous carbon layer 306 [0052] Fig 3) comprising a top portion over and contacting the conductive line (conductive layer 402 [0054] Fig 4).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Elers et al, Bao et al, and Bielefeld et al to include an amorphous carbon layer and contacting the conductive line as taught by Yang et al’913 in order to improve the reliability of the graphite layer [0026]. Further, a person of ordinary skill in the art would have recognized that improving the reliability of the graphite layer would be advantageous in optimizing the electrical functioning capability of the device while improving the durability and reliability of the device (see MPEP 2143.I(D)).
The combination of Elers et al, Bao et al, Bielefeld et al, and Yang et al’913 now discloses
further comprising an amorphous carbon layer (amorphous carbon layer 306 [0052] Fig 3 Yang et al’913) comprising a top portion over and contacting the graphite line (402 Fig 4 Yang et al’913/graphene 30 [0036] Fig 6 Bao et al).
Regarding Claim 10, the combination of Elers et al, Bao et al, Bielefeld et al, and Yang et al’913 discloses the limitations of claim 9 as explained above. The combination of Elers et al, Bao et al, Bielefeld et al, and Yang et al’913 further discloses
wherein the amorphous carbon layer (306 Fig 3 Yang et al’913) comprises a sidewall portion contacting a sidewall of the graphite line (402 Fig 4 Yang et al/graphene 30 [0036] Fig 6 Bao et al) to form an interface (shown in Fig 4 Yang et al) that extends from a top surface to a bottom surface of the graphite line (402 Fig 4 Yang et al’913/graphene 30 [0036] Fig 6 Bao et al).
Regarding Claim 11, the combination of Elers et al, Bao et al, Bielefeld et al, and Yang et al’913 discloses the limitations of claim 9 as explained above. The combination of Elers et al, Bao et al, Bielefeld et al, and Yang et al’913 further discloses
wherein the top portion of the amorphous carbon layer (306 Fig 3 Yang et al’913) forms a horizontal interface (shown in annotated Fig 4 Yang et al’913) with the graphite line (402 Fig 4 Yang et al’913/graphene 30 [0036] Fig 6 Bao et al).
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Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Elers et al (US 2005/0110145) in view of Bao et al (US 2014/0167268), Bielefeld et al (US 2008/0073748) and Yang et al’913 (US 2018/0350913), and in further view of Matsumoto et al (US 5866920).
Regarding Claim 12, the combination of Elers et al, Bao et al, Bielefeld et al, and Yang et al’913 discloses the limitations of claim 9 as explained above. The combination of Elers et al, Bao et al, Bielefeld et al, and Yang et al’913 does not disclose
wherein the amorphous carbon layer comprises fluorine therein.
Matsumoto et al, in the related art of semiconductor devices that include interconnects, discloses
an amorphous carbon layer (amorphous carbon fluoride film 141 [column 9, lines 34-42] Fig 4) comprises fluorine.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Elers et al, Bao et al, Bielefeld et al, and Yang et al’213 to include an amorphous carbon layer that comprises fluorine as taught by Matsumoto et al in order to have an insulating layer with a small dielectric constant to avoid crosstalk and wiring delay [column 1, lines 56-67]-[column 3, lines 1-67]. Further, a person of ordinary skill in the art would have recognized that having an amorphous carbon layer with fluorine would be a simple substitution of one known element for another to obtain predictable results (see MPEP 2143.I(B)) (suitable alternate).
Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al’076 (US 2018/0138076) in view of Bao et al (US 2014/0167268).
Regarding Claim 17, Yang et al’076 discloses a structure comprising:
a first conductive feature (via contacts (not shown) are in the substrate 101 [0014] Fig 1) comprising a first metallic material (via contacts Fig 1); and
a second conductive feature (conductive lines 161 and 162 [0030] Fig 13) over the metal conductive line (conductive portions 131 and 132 [0020] Fig 9A),
wherein the second conductive feature (conductive lines 161 and 162 [0030] Fig 13) comprises a second metallic material (conductive lines 161 and 162 Fig 13).
Yang et al’076 does not disclose
a graphite line over the first conductive feature;
wherein the graphite line electrically connects the first conductive feature to the second conductive feature.
Bao et al, in the related art of semiconductor devices that include graphene and metal interconnect structures, discloses
a graphite conductive feature (graphene 30 [0036] Fig 6) over and electrically coupling to the first conductive feature (via 16 [0036] Fig 6); and
wherein the second conductive feature (via 36 and barrier metal 38 [0032] Fig 6) is over and electrically connected to the graphite conductive feature (30 Fig 6).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Yang et al’076 to include a graphite conductive feature as taught Bao et al in order to have superior current capabilities and thermal conductivity [0003]. Further, a person of ordinary skill in the art would have recognized that having superior current capabilities and thermal conductivity would be advantageous in optimizing the electrical functioning capability of the device when the graphite is electrically connected to the second conductive feature (see MPEP 2143.I(D)). Additionally, a person of ordinary skill in the art would have recognized that having graphite for a conductive feature would be a simple substitution of one known element for another to achieve predictable results (see MPEP 2143.I(B)) (suitable alternate).
Regarding Claim 18, the combination of Yang et al’076 and Bao et al discloses the limitations of claim 17 as explained above. The combination of Yang et al’076 and Bao et al, as applied to claim 17, does not disclose
wherein the second conductive feature comprises copper.
However, Bao et al, in the related art of semiconductor devices that include graphene and metal interconnect structures, discloses
wherein the second conductive feature (via 36 and barrier metal 38 [0032] Fig 6) comprises copper (via 36 is composed of a copper core [0032]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Yang et al’076 and Bao et al, as applied to claim 17, to include wherein the second conductive feature comprises copper as taught by Bao et al in order to optimize the electrical connection capability [0032]. Further, a person of ordinary skill in the art would have recognized that having a second conductive feature comprising copper would be a simple substitution of one known element for another to obtain predictable results (see MPEP 2143.I(B)) (suitable alternate).
The combination of Yang et al’076 and Bao et al now discloses
wherein the second conductive feature (conductive lines 161 and 162 [0030] Fig 13 Yang et al’076/via 36 and barrier metal 38 [0032] Fig 6 Bao et al) comprises copper (copper via 36 [0032]).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Yang et al’076 (US 2018/0138076) in view of Bao et al (US 2014/0167268), and in further view of Elers et al (US 2005/0110145).
Regarding Claim 19, the combination of Yang et al’076 and Bao et al discloses the limitations of claim 17 as explained above. The combination of Yang et al’076 and Bao et al does not disclose
wherein the second conductive feature has a damascene structure.
Elers et al, in the related art of semiconductor devices that include damascene process, discloses
wherein the second conductive feature (250 in trench 232 [0056] Fig 20) has a damascene structure (formed using a damascene process [0035]-[0041]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Yang et al’076 and Bao et al to include wherein the second conductive feature has a damascene structure as taught by Elers et al in order to provide a product that is simpler and cheaper [0004]. Further, a person of ordinary skill in the art would have recognized that providing a product that is simpler and cheaper would be advantageous in providing a more cost-effective device (see MPEP 2143.I(D)).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Yang et al’076 (US 2018/0138076) in view of Bao et al (US 2014/0167268), and in further view of Bielefeld et al (US 2008/0073748).
Regarding Claim 20, the combination of Yang et al’076 and Bao et al discloses the limitations of claim 17 as explained above. The combination of Yang et al’076 and Bao et al does not disclose
further comprising: a dielectric layer, wherein the first conductive feature is in the dielectric layer; and
a dielectric spacer layer contacting a sidewall of the graphite line, wherein the dielectric spacer layer further contacts a top surface of the dielectric layer to form a horizontal surface.
Bielefeld et al, in the related art of semiconductor devices that include dielectric spacers and metal interconnects, discloses
further comprising: a dielectric layer (gap 120 may be comprised of carbon-doped oxide [0023] Fig 1); and
a dielectric spacer layer (dielectric spacer 108 [0024] Fig 1).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Yang et al’076 and Bao et al to include a first dielectric layer encircling the sidewall portions of the dielectric spacer layer as taught by Bielefeld et al in order to isolate the metal interconnects [0023]. Further, a person of ordinary skill in the art would have recognized that having a gap filled with carbon-doped oxide [0023] would be a simple substitution of one known element for another to obtain predictable results (see MPEP 2143.I(B)) (suitable alternate).
The combination of Yang et al’076, Bao et al, and Bielefeld et al now discloses
wherein the first conductive feature (via contacts (not shown) are in the substrate 101 [0014] Fig 1 Yang et al’076/metal interconnects in structure 500 [0029] Fig 5H Bielefeld et al) is in the dielectric layer (dielectric layer as part of 500 [0029] Fig 5H Bielefeld et al); and
a dielectric spacer layer (108 Fig 1 Bielefeld et al) contacting a sidewall of the graphite line (graphene 30 [0036] Fig 6 Bao et al), wherein the dielectric spacer layer (108 Fig 1 Bielefeld et al) further contacts a top surface of the dielectric layer (120 Fig 1 Bielefeld et al) to form a horizontal surface.
Allowable Subject Matter/Statement of Reasons for Allowance
Claims 5-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 5: The prior art does not anticipate or render obvious, alone or in combination, that “further comprising an amorphous carbon layer, wherein the second conductive feature penetrates through the amorphous carbon layer to contact a crystalline inner portion of the graphite conductive feature,” in the combination required by the claim.
Specifically, although an amorphous carbon layer is taught if Fig 3 and Fig 4 of Yang et al’913, Yang et al’913 does not disclose wherein the second conductive feature penetrates through the amorphous carbon layer to contact a crystalline inner portion of the graphite conductive feature. Further, a secondary reference that teaches this feature has not yet been found.
It is these features found in the claim, as they are claimed in the combination that has not been found, taught or suggested by the prior art of record, which makes this claim allowable over the prior art.
Claim 6 would be allowable based on its dependency on Claim 5.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Related Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Briggs et al (US 2017/0301621) which discloses forming interconnect structures that may comprise graphene [0036].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID PAUL SEDOROOK whose telephone number is (571)272-4158. The examiner can normally be reached Monday - Friday 7:30 am -5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge can be reached on (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/D.P.S./Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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