DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3, 4, 18 and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kashima (US 2020/0286910 A1).
In regards to claim 1, Kashima (Figs. 4, 12, 22, 23B and associated text and items) discloses a three-dimensional semiconductor memory device (Fig. 4), comprising: a substrate (item 20); a stacked structure (items 22 plus 23) including gate electrodes (item 23) stacked on the substrate (item 20) in a first direction perpendicular to a lower surface of the substrate (item 20); a semiconductor pattern (item 31) extending in the stacked structure (items 22 plus 23) in the first direction; a back gate plug (item 30) extending in the first direction in the semiconductor pattern (item 31); a back gate plate (bottommost item 24, SGDa) extending on an upper surface of the back gate plug (item 30) in a second direction and a third direction parallel to the lower surface of the substrate (item 20), the third direction intersecting the second direction, the back gate plate (bottommost item 24, SGDa) having an opening (item SH) therein; a bit line (item 25, BL) on the back gate plate (bottommost item 24, SGDa); and a selection channel structure (item UP of MP) electrically connecting the bit line (item 25, BL) and the semiconductor pattern (item 31), wherein the selection channel structure (item UP of MP) is in the opening (item SH).
In regards to claim 3, Kashima (Figs. 4, 12, 22, 23B and associated text and items) discloses further comprising a channel hole (item MH) extending in the stacked structure (items 22 plus 23) in the first direction, wherein the semiconductor pattern (item 31) is in the channel hole (item MH), and wherein the opening (item SH) is offset from the channel hole (item MH) in the first direction (Fig. 23B).
In regards to claim 4, Kashima (Figs. 4, 12, 22, 23B and associated text and items) discloses further comprising a selection line (item 24, SGDb, SGDc or SGDd) on the back gate plate (bottommost item 24, SGDa), wherein the selection channel structure (item UP of MP) extends in the selection line (item 24, SGDb, SGDc or SGDd) in the first direction and extends into the opening (item SH).
In regards to claim 18, Kashima (Figs. 4, 12, 22, 23B and associated text and items) discloses an electronic system (Fig. 1), comprising: a three-dimensional semiconductor memory device (item 1); and a controller (item 2) electrically connected to the three-dimensional semiconductor memory device (item 1) through at least one input/output pad (item 8, I/O, actual pad not shown) and controlling the three-dimensional semiconductor memory device (item 1), wherein the three-dimensional semiconductor memory device (Fig. 4), comprising: a substrate (item 20); a stacked structure (items 22 plus 23) including gate electrodes (item 23) stacked on the substrate (item 20) in a first direction perpendicular to a lower surface of the substrate (item 20); a semiconductor pattern (item 31) extending in the stacked structure (items 22 plus 23) in the first direction; a back gate plug (item 30) extending in the first direction in the semiconductor pattern (item 31); a back gate plate (bottommost item 24, SGDa) extending on an upper surface of the back gate plug (item 30) in a second direction and a third direction parallel to the lower surface of the substrate (item 20), the third direction intersecting the second direction, the back gate plate (bottommost item 24, SGDa) having an opening (item SH) therein; a bit line (item 25, BL) on the back gate plate (bottommost item 24, SGDa); and a selection channel structure (item UP of MP) electrically connecting the bit line (item 25, BL) and the semiconductor pattern (item 31), wherein the selection channel structure (item UP of MP) is in the opening (item SH).
In regards to claim 19, Kashima (Figs. 4, 12, 22, 23B and associated text and items) discloses further comprising a selection line (item 24, SGDb, SGDc or SGDd) on the back gate plate (bottommost item 24, SGDa), wherein the selection channel structure (item UP of MP) extends in the selection line (item 24, SGDb, SGDc or SGDd) in the first direction and extends into the opening (item SH).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kashima (US 2020/0286910 A1) in view of Jung et al. (Jung) (US 2021/0358935 A1).
In regard to claim 2, Kashima (Figs. 4, 12, 22, 23B and associated text and items) does not specifically disclose wherein the opening (item SH) includes a plurality of openings arranged in a zigzag pattern in the second direction.
JUNG (paragraph 87) that holes can be formed in a line or zigzag form.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of JUNG, since it has been held that rearranging parts of an invention involves only routine skill in the art (In re Japiske, 86 USPQ 70).
Claim(s) 5-9 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kashima (US 2020/0286910 A1) in view of LEE et al. (LEE) (US 2017/0040338 A1).
In regards to claim 5, Kashima (Figs. 4, 12, 22, 23B and associated text and items) does not specifically disclose wherein the semiconductor pattern includes a vertical portion extending in the first direction in the stacked structure and a horizontal portion extending further in a horizontal direction than the vertical portion, on the vertical portion, the horizontal direction being any direction in a plane defined by the second and third directions.
LEE (paragraph 181, 183Fig. 18 and associated text) discloses wherein the semiconductor pattern (item AP) includes a vertical portion (item VP) extending in the first direction in the stacked structure (item ST) and a horizontal portion extending further in a horizontal direction than the vertical portion (item VP), on the vertical portion (item VP), the horizontal direction being any direction in a plane defined by the second and third directions.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of LEE for the purpose of an electrical connection, since such a modification would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
In regards to claim 6, Kashima as modified by LEE does not specifically disclose wherein the horizontal portion of the semiconductor pattern has a shape of at least one of a circular shape and an oval shape, when viewed in a plan view.
It would have been obvious to modify the invention to include a horizontal portion of the semiconductor pattern having a shape of at least one of a circular shape and an oval shape, when viewed in a plan view, since such a modification would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)). Applicant has not given any criticality in regards to the shape as to where it yields an unexpected result/advantage.
In regards to claim 7, Kashima (Figs. 4, 12, 22, 23B and associated text and items) as modified by LEE (paragraph 181, 183Fig. 18 and associated text) discloses wherein the opening (item SH, Kashima) at least partially vertically overlaps the horizontal portion (items HP, LEE) of the semiconductor pattern (item 31, Kashima, item AP, LEE).
In regards to claim 8, Kashima as modified by LEE does not specifically disclose wherein a diameter of the opening (item SH) is larger than a diameter of the horizontal portion of the semiconductor pattern (item 31, Kashima, item HP, LEE).
It would have been obvious to modify the invention to include a diameter of the opening is larger than a diameter of the horizontal portion of the semiconductor pattern, since such a modification would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)). Applicant has not given any criticality in regards to the shape as to where it yields an unexpected result/advantage.
In regards to claim 9, Kashima (Figs. 4, 12, 22, 23B and associated text and items) as modified by LEE (paragraph 181, 183Fig. 18 and associated text) discloses further comprising a channel hole (item MH, Kashima) extending in the stacked structure (items 22 plus 23, Kashima) in the first direction, wherein the semiconductor pattern (item 31, Kashima, item AP, LEE) is in the channel hole (item MH, Kashima), and wherein the horizontal portion (item HP, LEE) of the semiconductor pattern (item 31, Kashima, item AP, LEE) is horizontally offset from the channel hole (item MH, Kashima).
In regards to claim 20, Kashima (Figs. 4, 12, 22, 23B and associated text and items) does not specifically disclose wherein the semiconductor pattern includes a vertical portion extending in the first direction in the stacked structure and a horizontal portion extending further in a horizontal direction than the vertical portion, on the vertical portion, the horizontal direction being any direction in a plane defined by the second and third directions, and wherein the opening at least partially vertically overlaps the horizontal portion of the semiconductor pattern.
LEE (paragraph 181, 183Fig. 18 and associated text) discloses wherein the semiconductor pattern (item AP) includes a vertical portion (item VP) extending in the first direction in the stacked structure (item ST) and a horizontal portion extending further in a horizontal direction than the vertical portion (item VP), on the vertical portion (item VP), the horizontal direction being any direction in a plane defined by the second and third directions.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of LEE for the purpose of an electrical connection, since such a modification would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
Kashima (Figs. 4, 12, 22, 23B and associated text and items) as modified by LEE (paragraph 181, 183Fig. 18 and associated text) discloses wherein the opening (item SH, Kashima) at least partially vertically overlaps the horizontal portion (item HP, LEE) of the semiconductor pattern (item 31, Kashima, item AP, LEE).
Claim(s) 10-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kashima (US 2020/0286910 A1) in view of LEE et al. (LEE) (US 2017/0040338 A1) as applied to claims 5-9 above, and further in view of Ryu et al. (RYU) (US 2021/0143160 A1).
In regards to claim 10, Kashima as modified by LEE does not specifically disclose further comprising a ferroelectric layer extending in the first direction between the stacked structure and the semiconductor pattern.
Ryu (paragraphs 39, 49, 50, Figs. 4A-4C and associated text) discloses a ferroelectric layer (item 145 including 144 formed of HfSiO) extending in the first direction between the stacked structure (items 120 plus 130) and the semiconductor pattern (item 140).
Therefore it would have been obvious to one ordinary skill in the art before the effective filing date to incorporate the teachings of Ryu for the purpose of reducing leakage current.
In regards to claim 11, Kashima (Figs. 4, 12, 22, 23B and associated text and items) discloses a three-dimensional semiconductor memory device (Fig. 4), comprising: a substrate (item 20); a stacked structure (items 22 plus 23) including gate electrodes (item 23) stacked on the substrate (item 20) in a first direction perpendicular to a lower surface of the substrate (item 20); a semiconductor pattern (item 31) extending in the stacked structure (items 22 plus 23) in the first direction; a back gate plug (item 30) extending in the first direction in the semiconductor pattern (item 31); a back gate plate (bottommost item 24, SGDa) extending on an upper surface of the back gate plug (item 30) in a second direction and a third direction parallel to the lower surface of the substrate (item 20), the third direction intersecting the second direction, the back gate plate (bottommost item 24, SGDa) having an opening (item SH) therein; a bit line (item 25, BL) on the back gate plate (bottommost item 24, SGDa); and a selection channel structure (item UP of MP) electrically connecting the bit line (item 25, BL) and the semiconductor pattern (item 31), wherein the selection channel structure (item UP of MP) is in the opening (item SH), but does not specifically disclose wherein the semiconductor pattern includes a vertical portion extending in the first direction and a horizontal portion extending further in a horizontal direction than the vertical portion, on the vertical portion, the horizontal direction being any direction in a plane defined by the second and third directions, and wherein the back gate plate includes an opening that at least partially vertically overlaps the horizontal portion of the semiconductor pattern.
LEE (paragraph 181, 183Fig. 18 and associated text) discloses wherein the semiconductor pattern (item AP) includes a vertical portion (item VP) extending in the first direction in the stacked structure (item ST) and a horizontal portion extending further in a horizontal direction than the vertical portion (item VP), on the vertical portion (item VP), the horizontal direction being any direction in a plane defined by the second and third directions.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of LEE for the purpose of an electrical connection, since such a modification would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
Kashima (Figs. 4, 12, 22, 23B and associated text and items) as modified by LEE (paragraph 181, 183Fig. 18 and associated text) discloses wherein the opening (item SH, Kashima) at least partially vertically overlaps the horizontal portion (item HP, LEE) of the semiconductor pattern (item 31, Kashima, item AP, LEE).
Kashima as modified by LEE does not specifically disclose a ferroelectric layer and a semiconductor pattern extending in the stacked structure in the first direction;
Ryu (paragraphs 39, 49, 50, Figs. 4A-4C and associated text) discloses a ferroelectric layer (item 145 including 144 formed of HfSiO) and a semiconductor pattern (item 140) extending in the stacked structure (items 120 plus 130) in the first direction.
Therefore it would have been obvious to one ordinary skill in the art before the effective filing date to incorporate the teachings of Ryu for the purpose of reducing leakage current.
In regards to claim 12, Kashima as modified by LEE and Ryu does not specifically disclose wherein the horizontal portion of the semiconductor pattern has a shape of at least one of a circular shape and an oval shape, when viewed in a plan view.
It would have been obvious to modify the invention to include a horizontal portion of the semiconductor pattern having a shape of at least one of a circular shape and an oval shape, when viewed in a plan view, since such a modification would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)). Applicant has not given any criticality in regards to the shape as to where it yields an unexpected result/advantage.
In regards to claim 13, Kashima (Figs. 4, 12, 22, 23B and associated text and items) as modified by LEE (paragraph 181, 183Fig. 18 and associated text) discloses further comprising a channel hole (item MH, Kashima) extending in the stacked structure (items 22 plus 23, Kashima) in the first direction, wherein the semiconductor pattern (item 31, Kashima, item AP, LEE) is in the channel hole (item MH, Kashima), and wherein the horizontal portion (item HP, LEE) of the semiconductor pattern (item 31, Kashima, item AP, LEE) is horizontally offset from the channel hole (item MH, Kashima).
In regards to claim 14, Kashima as modified by LEE and Ryu does not specifically disclose wherein a diameter of the opening (item SH) is larger than a diameter of the horizontal portion of the semiconductor pattern (item 31, Kashima, item HP, LEE).
It would have been obvious to modify the invention to include a diameter of the opening is larger than a diameter of the horizontal portion of the semiconductor pattern, since such a modification would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)). Applicant has not given any criticality in regards to the shape as to where it yields an unexpected result/advantage.
In regards to claim 15, Kashima (Figs. 4, 12, 22, 23B and associated text and items) discloses further comprising: a selection line (item 24, SGDb, SGDc or SGDd) on the stacked structure (items 22 plus 23); and a selection channel layer (item UP of MP) extending in the selection line(item 24, SGDb, SGDc or SGDd) in the first direction and extending into the opening (item SH).
In regards to claim 16, Kashima (Figs. 4, 12, 22, 23B and associated text and items) as modified by LEE (paragraph 181, 183Fig. 18 and associated text) discloses wherein the selection channel layer (item UP of MP, Kashima) is in contact with the horizontal portion (item HP, LEE) of the semiconductor pattern (item 31, Kashima, item HP, LEE).
In regards to claim 17, Kashima (Figs. 4, 12, 22, 23B and associated text and items) as modified by LEE (paragraph 181, 183Fig. 18 and associated text) and Ryu discloses wherein the horizontal portion (item HP, LEE) of the semiconductor pattern (item 31, Kashima, item HP, LEE) is at a higher level than an upper surface of the stacked structure (item 22 plus 23, Kashima, item ST, LEE), relative to the lower surface of the substrate (item 20, Kashima, item 100, LEE) as a reference layer.
Conclusion
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 July 13, 2026
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