DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed January 8, 2025 fails to fully comply with 37 CFR 1.98(a)(2), which requires a legible copy of each cited foreign patent document; each non-patent literature publication or that portion which caused it to be listed; and all other information or that portion which caused it to be listed. As a result, citation number 441, 442, and 461 have not been considered.
Specification
The disclosure is objected to because of the following informalities:
In ¶ [0195]: “omprise” should read --comprise--.
Appropriate correction is required.
Claim Objections
Claim 17 is objected to because of the following informalities:
In line 2: “passive second waver” should read --passive second wafer--.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 2, the claim recites the limitation "the bonded structure" in line 12. There is insufficient antecedent basis for this limitation in the claim.
It is indefinite as to whether the bonded structure refers to the bonding structure of claim 1, lines 6-7 or some other structure. For the purposes of examination, the former interpretation will be used.
Claims 3-11 depend upon claim 2 and do not rectify the problem. Therefore, they are rejected on at least the same grounds as claim 2.
Regarding claims 12-18, the claims recite the limitation “the bonded structure” in line 1. There is insufficient antecedent basis for this limitation in the claim.
It is indefinite as to whether the bonded structure refers to the bonding structure of claim 1, lines 6-7 or some other structure. For the purposes of examination, the former interpretation will be used.
Regarding claim 7, the claim recites the limitation "the capacitor" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim 7 depends upon claim 2 which does not provide antecedent basis for a capacitor. Further, claim 3 provides antecedent basis for a plurality of capacitors and claim 4 provides antecedent basis for multiple capacitors, but there is no claim that provides separate antecedent basis for a single capacitor. It is unclear if the capacitor of claim 7 is intended to be one of the plurality of capacitors or some other capacitor.
For the purposes of examination, the former interpretation will be used.
Regarding claim 10, the claim recites the limitation the through-signal conductor in lines 1-2. There is insufficient antecedent basis for this limitation in the claim.
Claim 10 depends upon claim 8 which does not provide antecedent basis for a through-signal conductor. It is unclear if the through-signal conductor of claim 10 is intended to be the same through-signal conductor as described in claim 9 lines 1-2 or some other through-signal conductor.
For the purposes of examination, the former interpretation will be used.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 2-4, 7-10, and 18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Wu et al. (US 20180082964 A1) herein after “Wu”.
Regarding claim 2, Figs. 1-13 of Wu disclose a method (Figs. 1-13, “methods of forming the package structure”, ¶ [0010]) comprising:
providing an active first wafer (Fig. 5, integrated circuit dies 42, ¶ [0028]) having a first bonding surface comprising a first non-conductive region (Fig. 7, dielectric material 48, ¶ [0031]) and a first conductive region (Fig. 7, die connectors 46, ¶ [0031]);
providing a passive second wafer (Fig. 7, wafer 20, redistribution structure 28, ¶ [0019]) having a second bonding surface comprising a second non-conductive region (Fig. 7, dielectric layers 32 and 38, ¶ [0019]) and a second conductive region (Fig. 7, bond pads 36, ¶ [0019]);
hybrid bonding the first and second bonding surfaces together to form a bonding structure, said hybrid bonding comprising (“The integrated circuit dies 42 are bonded to the dielectric layer 38 and the bond pads 36 through hybrid bonding”, ¶ [0032]):
directly bonding the first (48) and second non-conductive regions (38) together without an intervening adhesive (“The dielectric layer 38 is also bonded to the dielectric layer 48, with bonds formed therebetween”, ¶ [0034]); and
directly bonding the first (46) and second conductive regions (36) together without an intervening adhesive (“the bond pads 36 and 46 are bonded to each other through direct metal bonding”, ¶ [0035]); and
singulating the bonded structure (100) into a plurality of elements, wherein each element comprises portions of the first and second wafers (“a singulation process is performed by sawing 90 along scribe line regions e.g., between second packages 110 and first packages 100”, ¶ [0060]).
Regarding claim 3, Figs. 1-13 of Wu disclose the method of claim 2 as applied above, and Fig. 1 of Wu further discloses wherein the passive second wafer (20, 28) comprises a plurality of capacitors (Fig. 1, integrated passive devices (IPDs) 26, ¶ [0017]) (“a deep-trench capacitor may be formed by first forming trenches into the substrate 22”, ¶ [0018]).
Regarding claim 4, Fig. 1 of Wu discloses the method of claim 3 as applied above, and Fig. 13 of Wu further discloses wherein each element of the plurality of singulated elements comprises multiple capacitors (shown in Fig. 13).
Regarding claim 7, Figs. 1-13 of Wu disclose the method of claim 2 as applied above, and Fig. 1 of Wu further discloses wherein a dielectric material of the capacitor (26) comprises a high K dielectric (“A dielectric layer may be formed over the first conductive electrode material within the trench. The dielectric layer may comprise high-K dielectric materials”, ¶ [0018]).
Regarding claim 8, Figs. 1-13 of Wu disclose the method of claim 2 as applied above, and Fig. 5 of Wu further discloses wherein the active first wafer (42) comprises a processor (“The integrated circuit dies 42 may be logic dies (e.g., central processing unit”, ¶ [0028]).
Regarding claim 9, Figs. 1-13 of Wu disclose the method of claim 2 as applied above, and Fig. 2 of Wu further discloses comprising providing a through-signal conductor (Fig. 2, through vias 24, ¶ [0012]) extending through the passive electronic component (“The through vias 24 of the wafer 20 may be formed”, ¶ [0014]).
Regarding claim 10, Fig. 5 of Wu discloses the method of claim 8 as applied above, and Fig. 2 of Wu further discloses comprising providing the through-signal conductor (24) before the hybrid bonding (Fig. 2, “The through vias 24 of the wafer 20 may be formed”, ¶ [0014]).
Regarding claim 18, Figs. 1-13 of Wu disclose the method of claim 2 as applied above, and Fig. 7 of Wu further discloses wherein the active first wafer (42) comprises a substrate (Fig. 7, semiconductor substrate 43, ¶ [0029]) and a plurality of active devices on the same side of the substrate (43) as the first bonding surface (“Devices, such as transistors, diodes, capacitors, resistors, etc., may be formed in and/or on the semiconductor substrate 43 and may be interconnected by interconnect structures 44”, ¶ [0029]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Wu (US 20180082964 A1) in view of Sharan et al. (US 20160190113 A1) herein after “Sharan”.
Regarding claim 5, Fig. 13 of Wu disclose the method of claim 4 as applied above, and Fig. 13 of Wu discloses multiple capacitors, but fails to explicitly disclose that the capacitors form part of a power delivery network for each element.
In the similar field of endeavor of stacked integrated circuit packages, Fig. 8 of Sharan discloses the capacitors (Fig. 8, capacitors 812, ¶ [0041]) form part of a power delivery network for each element (“capacitors are embedded in the back side of a bottom die 806, to enable a natural path from a FIVR circuit”, “using passive components for power delivery”, ¶ [0041] and [0048]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Wu with the power delivery as disclosed by Sharan, to power the processing core (see Sharan, ¶ [0064]).
Claims 6, and 13-16 are rejected under 35 U.S.C. 103 as being unpatentable over Wu (US 20180082964 A1).
Regarding claim 6, Fig. 1 of Wu discloses the method of claim 3 as applied above, but Wu fails to disclose wherein the plurality of capacitors reduces impedance at frequencies above 500 MHz, as compared to a configuration in which the active first wafer and the passive second wafer are not directly bonded.
However, the recited limitations describe the characteristics of the bonding structure formed by the claimed method. It has been held that where claimed and prior art contain identical or substantially similar methods, a prima facie case of anticipation or obviousness has been established. MPEP 2112.01, citing In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).
The prior art teaches or at least suggests the claims' positive method steps, it is not required that the prior art also teaches or suggests the features of the intended result of performing said steps. It would not be reasonable to expect different results when performing identical or at least substantially similar steps. Therefore, one of ordinary skill in the art would recognize that Wu renders obvious the claim by disclosing the required method steps.
Regarding claim 13, Figs. 1-13 of Wu disclose the method of claim 2 as applied above, but Wu fails to explicitly disclose wherein the passive second wafer includes an array of capacitive cells having an effective capacitance per unit area of at least 5 nF/mm2.
However, it would have been obvious to one having ordinary skill in the art at the time of the invention to arrive at the claimed effective capacitance per unit area as a matter of design choice and/or since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. See, e.g., In re Boesch, 617 F.2d 272,205 USPQ 215 (CCPA 1980); MPEP 2144.05.
Regarding claim 14, Figs. 1-13 of Wu disclose the method of claim 13 as applied above, but Wu fails to explicitly disclose wherein the passive second wafer includes an array of capacitive cells having an effective capacitance per unit area of at least 50 nF/mm2.
However, it would have been obvious to one having ordinary skill in the art at the time of the invention to arrive at the claimed effective capacitance per unit area as a matter of design choice and/or since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. See, e.g., In re Boesch, 617 F.2d 272,205 USPQ 215 (CCPA 1980); MPEP 2144.05.
Regarding claim 15, Figs. 1-13 of Wu disclose the method of claim 13 as applied above, but Wu fails to explicitly disclose wherein the passive second wafer includes an array of capacitive cells having an effective capacitance per unit area of at least 100 nF/mm2.
However, it would have been obvious to one having ordinary skill in the art at the time of the invention to arrive at the claimed effective capacitance per unit area as a matter of design choice and/or since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. See, e.g., In re Boesch, 617 F.2d 272,205 USPQ 215 (CCPA 1980); MPEP 2144.05.
Regarding claim 16, Figs. 1-13 of Wu disclose the method of claim 13 as applied above, but Wu fails to explicitly disclose wherein the passive second wafer includes an array of capacitive cells having an effective capacitance per unit area of at least 200 nF/mm2.
However, it would have been obvious to one having ordinary skill in the art at the time of the invention to arrive at the claimed effective capacitance per unit area as a matter of design choice and/or since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. See, e.g., In re Boesch, 617 F.2d 272,205 USPQ 215 (CCPA 1980); MPEP 2144.05.
Claim 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Wu (US 20180082964 A1) in view of Muramatsu (US 20110018099 A1).
Regarding claim 11, Figs. 1-13 of Wu disclose the method of claim 2 as applied above, and Wu further discloses that the passive second wafer comprise high-K dielectric materials, but Wu fails to explicitly disclose wherein the passive second wafer comprises materials having a dielectric constant greater than 5.
In the similar field of endeavor of semiconductor integrated circuit devices, Fig. 1 of Muramatsu discloses wherein the passive second wafer (Fig. 1, wiring substrate 10, ¶ [0056]) comprises materials having a dielectric constant greater than 5 (“The ceramic dielectric layers 305 are formed of a sintered body of barium titanate”, ¶ [0059]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Wu with the material as disclosed by Muramatsu, to obtain the desired capacitance properties (see Muramatsu, ¶ [0015]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 12, Wu and Muramatsu together disclose the bonded structure of claim 11 as applied above, and Wu further discloses that the passive second wafer comprise high-K dielectric materials, but Wu fails to explicitly disclose wherein the passive second wafer comprises materials having a dielectric constant greater than 20.
In the similar field of endeavor of semiconductor integrated circuit devices, Fig. 1 of Muramatsu discloses wherein the passive second wafer (Fig. 1, wiring substrate 10, ¶ [0056]) comprises materials having a dielectric constant greater than 5 (“The ceramic dielectric layers 305 are formed of a sintered body of barium titanate”, ¶ [0059]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Wu with the material as disclosed by Muramatsu, to obtain the desired capacitance properties (see Muramatsu, ¶ [0015]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Wu (US 20180082964 A1) and Sharan (US 20160190113 A1) in further view of Muramatsu (US 20110018099 A1).
Regarding claim 17, Wu and Sharan together disclose the bonded structure of claim 5 as applied above, but Wu and Sharan fail to explicitly disclose comprising providing vias in the passive second waver that provide signals separate from the power delivery network.
In the similar field of endeavor of semiconductor integrated circuit devices, Fig. 1 of Muramatsu discloses comprising providing vias (Fig. 1, signal electrodes 313, ¶ [0061]) in the passive second wafer (10) that provide signals separate from the power delivery network (Fig. 1, power-supply electrodes 311, grounding electrodes 312, ¶ [0061]) (“the main-surface-side power-supply electrodes 311, the main-surface-side grounding electrodes 312, and the main-surface-side signal electrodes 313”, ¶ [0081]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Wu with the vias as disclosed by Muramatsu, to control the capacitor (see Muramatsu, ¶ [0062]).
Conclusion
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/C.A.N./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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