DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
2. The information disclosure statement (IDS) submitted on December 11, 2024 has been fully considered by the examiner.
Specification
3. Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” “The disclosure defined by this invention,” “The disclosure describes,” etc. In addition, the form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided.
4. The abstract of the disclosure is objected to because line 2 recites the phrase, “are described,” which can be implied.
A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Objections
5. Claims 3 and 14 are objected to because of the following informalities.
Regarding claim 3, lines 6-7 recite, “…based at least in part on a value of the counter being failing to satisfy a threshold value.” Examiner believes this is a typographical error and is intended to read, “…based at least in part on a value of the counter [[being]] failing to satisfy a threshold value.”
Regarding claim 14, line 4 recites, “the second logic state that is a same as a logic state.” Examiner believes this is a typographical error and is perhaps intended to recite, “the second logic state that is a same logic state.”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
6. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
7. Claims 8 and 13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 recites the limitation “the quantity of memory sections” in line 4. There is insufficient antecedent basis for this limitation in the claim. It is also unclear if “a quantity of memory portions” in line 3 and “the quantity of memory sections” in line 4 describe the same entities. Accordingly, the meanings of the limitations are indefinite.
For the purpose of this action, the limitation “the quantity of memory sections” in line 4 shall be interpreted as “the quantity of memory portions” so that the limitation of line 3 also provides antecedent basis for the limitation of line 4.
Claim 13 recites the limitation “the respective second logic state” in line 4. There is insufficient antecedent basis for this limitation in the claim.
For the purpose of this action, the limitation “the respective second logic state” shall be interpreted as “[[the]] a respective second logic state.”
Claim Rejections - 35 USC § 102
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
9. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
10. Claims 1, 4-7, 10-12, and 15-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang, et al (US 11024393 B1), hereinafter Zhang.
Regarding independent claim 1, Zhang teaches a memory system, comprising:
a memory array (FIG. 2, 212), comprising:
a plurality of memory portions (FIG. 4, e.g., a “portion” may include cells coupled to WLn);
a plurality of word lines (FIG. 4, e.g., WLn); and
a plurality of bit lines (FIG. 4, 462..468; Col. 14, ll. 16-18); and
a memory controller (FIG. 2, 208) coupled with the memory array (FIG. 2, via bus 226) and configured to cause the memory system to:
write a respective first logic state to each memory cell (Col. 4, ll. 17-20; e.g., the state of a cell may be in ZONE 2 524 of FIG. 5) of each of the plurality of memory portions (e.g., pages of cells coupled to word lines; Col. 10, ll. 7-9; Col. 3, ll. 28-34);
bias a first word line (FIG. 8, WLn+1) and a second word line (FIG. 8, WLn) of the plurality of word lines to a first voltage (FIG. 8, pass voltage (VPASS), including spike pulse 812; Col. 4, l. 32; Col. 24, ll. 37-38) based at least in part on receiving a command (Col. 10, ll. 19-22) to validate a write operation (Col. 22, ll. 28-31), wherein the first word line corresponds to a first memory portion (FIG. 4, cells coupled to WLn+1) of the plurality of memory portions and the second word line corresponds to a second memory portion (FIG. 4, cells coupled to WLn) of the plurality of memory portions;
apply a first read pulse (FIG. 8, VSENS; Col. 24, ll. 45-46) to the first word line and a second read pulse (FIG. 8, 820; Col. 26, ll. 41-50) to the second word line based at least in part on biasing the first word line and the second word line to the first voltage (FIG. 8, VPASS spike 812 applied to WLn+1 and VPASS applied to WLn during initialization phase 802; Col. 20, ll. 19-22);
read a second logic state (e.g., the state of a cell may be in ZONE 1, 522, in FIG. 5) from one or more memory cells of the first memory portion and the second memory portion based at least in part on applying the first read pulse to the first word line (FIGS. 5 and 8, the determination of ZONE 1 vs. ZONE 2 is done when applying VSENS to first word line WLn+1) and the second read pulse to the second word line (FIG. 8, the determination of states is done when applying one or more read voltage(s) to WLn; Col. 26, ll. 41-43); and
validate the write operation based at least in part on reading the second logic state from the one or more memory cells of the first memory portion and the second memory portion (e.g., FIG. 5, using read voltage VrD and verify voltage VvD to differentiate ZONE 1 from ZONE 2 and other read and verify voltages shown to differentiate states Er..G; Col. 24, l. 58 – Col. 25, l. 10; see also Col. 17, ll. 43-50 and Col. 22, ll. 28-31).
Regarding independent claim 12, Zhang teaches a method, comprising:
writing a respective first logic state to each memory cell (Col. 4, ll. 17-20; e.g., the state of a cell may be in ZONE 2 524 of FIG. 5) of each of a plurality of memory portions (e.g., pages of cells coupled to word lines; Col. 10, ll. 7-9; Col. 3, ll. 28-34);
biasing a first word line (FIG. 8, WLn+1) and a second word line (FIG. 8, WLn) of a plurality of word lines to a first voltage (FIG. 8, pass voltage (VPASS), including spike pulse 812; Col. 4, l. 32; Col. 24, ll. 37-38) based at least in part on receiving a command (Col. 10, ll. 19-22) to validate a write operation (Col. 22, ll. 28-31), wherein the first word line corresponds to a first memory portion (FIG. 4, cells coupled to WLn+1) of the plurality of memory portions and the second word line corresponds to a second memory portion (FIG. 4, cells coupled to WLn) of the plurality of memory portions;
applying a first read pulse (FIG. 8, VSENS; Col. 24, ll. 45-46) to the first word line and a second read pulse (FIG. 8, 820; Col. 26, ll. 41-50) to the second word line based at least in part on biasing the first word line and the second word line to the first voltage (FIG. 8, VPASS spike 812 applied to WLn+1 and VPASS applied to WLn during initialization phase 802; Col. 20, ll. 19-22);
reading a second logic state (e.g., the state of a cell may be in ZONE 1, 522, in FIG. 5) from one or more memory cells of the first memory portion and the second memory portion based at least in part on applying the first read pulse to the first word line (FIGS. 5 and 8, the determination of ZONE 1 vs. ZONE 2 is done when applying VSENS to first word line WLn+1) and the second read pulse to the second word line (FIG. 8, the determination of states (e.g., FIG. 5, states Er..G) is done when applying one or more read voltage(s) to WLn; Col. 26, ll. 41-43); and
validating the write operation based at least in part on reading the second logic state from the one or more memory cells of the first memory portion and the second memory portion (e.g., FIG. 5, using read voltage VrD and verify voltage VvD to differentiate ZONE 1 from ZONE 2 and other read and verify voltages shown to differentiate states Er..G; Col. 24, l. 58 – Col. 25, l. 10; see also Col. 17, ll. 43-50 and Col. 22, ll. 28-31).
Regarding independent claim 19, Zhang teaches a method, comprising:
reading, during a first duration (FIG. 8, duration from t1 to t2), a first logic state (Col. 4, ll. 17-20; e.g., the state of a cell may be in ZONE 2 524 of FIG. 5) from at least a first memory cell coupled with a first word line of a plurality of word lines (FIG. 4, e.g., memory cell 428 coupled to word line WLn+1);
reading, during a second duration (FIG. 8, duration from t3 to t4), a second logic state (e.g., the state of a cell may be in ZONE 1 522 of FIG. 5) from at least a second memory cell coupled with a second word line of the plurality of word lines (FIG. 4, e.g., memory cell 430 coupled to word line WLn) based at least in part on reading the first logic state from at least the first memory cell (FIG. 8, bit line voltages of reading phase 808 are based upon the result of “zoning” read phase 804; Col. 26, ll. 33-40); and
verifying, during a third duration (the first and second durations of FIG. 8 are for a read operation, whereas a program verify operation is part of a write operation and therefore would be at a “third time” outside of the scope of FIG. 8) and based at least in part on reading the second logic state from the second memory cell, that the first logic state and the second logic state written to at least the first memory cell and the second memory cell were written during respective write operations preceding the first duration (Col. 22, ll. 15-31 teaches both read and program verify operations involve “sensing” whether a memory cell conducts at a reference voltage, such as the verify voltages of various programmed states (see FIG. 5 and Col. 17, ll. 45-50), and therefore “reading” logic states of cells is part of the program verify operation).
Regarding claim 4, Zhang teaches the limitations of claim 1.
Zhang further teaches wherein the respective first logic state comprises more than one bit (FIG. 5, e.g., each of logic states falling within ZONE 1 and ZONE 2 includes four possible data states (two bits equivalent) each, with three bits required to represent all of states Er..G) and wherein, to apply the first read pulse and the second read pulse, the memory controller is configured to cause the memory system to:
bias the first word line and the second word line of the plurality of word lines to a second voltage (it appears from the present disclosure that the “second voltage” is a voltage applied to a read pulse (FIG. 2B, 220; ¶ [0115]; it also appears from FIG. 2B, 220, that the “second voltage” may be applied sequentially – not concurrently – to different word lines) that corresponds to a threshold voltage distribution of a plurality of threshold voltage distributions associated with the respective first logic state (Zhang FIGS. 5 and 8, “first read pulse” VSENS may be associated with data state D in ZONE 2 524; “second read pulse” 820 may be associated with any of the data states of FIG. 5, including those in ZONE 2, depending on the result of the Zoning operation).
Regarding claim 5, Zhang teaches the limitations of claim 1.
Zhang further teaches bias the first word line and the second word line of the plurality of word lines to a second voltage based at least in part on reading the second logic state from the one or more memory cells, wherein the second voltage is less than the first voltage (it appears from the present disclosure that the “second voltage” is a voltage applied to a read pulse (FIG. 2B, 220; ¶ [0115]); in Zhang FIG. 8, the “second voltage” may be VSENS, VCGR1, etc., and is less than “first voltage” VPASS).
Regarding claim 6, Zhang teaches the limitations of claim 1.
Zhang further teaches to apply the first read pulse and the second read pulse, the memory controller is configured to cause the memory system to:
apply the first read pulse and the second read pulse during a respective first duration and second duration, wherein the respective first duration occurs prior to the respective second duration, and wherein the respective first duration and the respective second duration are non-overlapping durations (FIG. 8, first duration t1-t2 precedes second duration t3-t4 and the respective durations are shown as non-overlapping, separated by transition phase t2-t3).
Regarding claim 7, Zhang teaches the limitations of claim 1.
Zhang further teaches to bias the first word line and the second word line to the first voltage, the memory controller is configured to cause the memory system to:
bias the first word line and the second word line to the first voltage during a same duration (biasing of both first word line WLn+1 and second word line WLn occurs during initialization phase 802 of FIG. 8 (duration t0-t1)).
Regarding claim 10, Zhang teaches the limitations of claim 1.
Zhang further teaches the first memory portion and the second memory portion comprise consecutive memory portions (first memory portion associated with WLn+1 is adjacent to second memory portion associated with WLn, meaning they are “consecutive” memory portions); or
the first memory portion and the second memory portion are separated from one another by one or more intervening memory portions.
Regarding claim 11, Zhang teaches the limitations of claim 1.
Zhang further teaches the plurality of memory portions comprise single-level cells, multi-level cells, or tri-level cells (e.g., FIG. 5 illustrates states of tri-level cells; see also Col. 3, ll. 25-27: “This method may be utilized for single- and multi-level memory cells, including 3-level and 4-level memory cells”).
Regarding claim 15, Zhang teaches the limitations of claim 12.
Zhang further teaches the respective first logic state comprises more than one bit (FIG. 5, e.g., each of logic states falling within ZONE 1 and ZONE 2 includes four possible data states (two bits equivalent) each, with three bits required to represent all of states Er..G) and wherein applying the first read pulse and the second read pulse comprises:
biasing the first word line and the second word line of the plurality of word lines to a second voltage (it appears from the present disclosure that the “second voltage” is a voltage applied to a read pulse (FIG. 2B, 220; ¶ [0115]; it also appears from FIG. 2B, 220, that the “second voltage” may be applied sequentially – not concurrently – to different word lines) that corresponds to a threshold voltage distribution of a plurality of threshold voltage distributions associated with the respective first logic state (Zhang FIGS. 5 and 8, “first read pulse” VSENS may be associated with data state D in ZONE 2 524; “second read pulse” 820 may be associated with any of the data states of FIG. 5, including those in ZONE 2, depending on the result of the Zoning operation).
Regarding claim 16, Zhang teaches the limitations of claim 12.
Zhang further teaches biasing the first word line and the second word line of the plurality of word lines to a second voltage based at least in part on reading the second logic state from the one or more memory cells, wherein the second voltage is less than the first voltage (it appears from the present disclosure that the “second voltage” is a voltage applied to a read pulse (FIG. 2B, 220; ¶ [0115]); in Zhang FIG. 8, the “second voltage” may be VSENS, VCGR1, etc., and is less than “first voltage” VPASS).
Regarding claim 17, Zhang teaches the limitations of claim 12.
Zhang further teaches applying the first read pulse and the second read pulse comprises:
applying the first read pulse and the second read pulse during a respective first duration and second duration, wherein the respective first duration occurs prior to the respective second duration, and wherein the respective first duration and the respective second duration are non-overlapping durations (FIG. 8, first duration t1-t2 precedes second duration t3-t4 and the respective durations are shown as non-overlapping, separated by transition phase t2-t3).
Regarding claim 18, Zhang teaches the limitations of claim 12.
Zhang further teaches biasing the first word line and the second word line to the first voltage comprises:
biasing the first word line and the second word line to the first voltage during a same duration (biasing of both first word line WLn+1 and second word line WLn occurs during initialization phase 802 of FIG. 8 (duration t0-t1)).
Regarding claim 20, Zhang teaches the limitations of claim 19.
Zhang further teaches the first memory cell and the second memory cell comprise multi-level memory cells (e.g., FIG. 5 illustrates states of tri-level cells; see also Col. 3, ll. 25-27: “This method may be utilized for single- and multi-level memory cells, including 3-level and 4-level memory cells”), wherein reading the first logic state and the second logic state from the first memory cell and the second memory cell comprises:
reading a single bit of data from each of the first memory cell and the second memory cell (e.g., the zoning read operation 804 of FIG. 8 utilizes a single read pulse, treating the cells as single-level or single-bit cells during the zoning read operation (see also FIG. 5)).
Claim Rejections - 35 USC § 103
11. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
12. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
13. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
14. Claims 2-3 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang, et al (US 11024393 B1), hereinafter Zhang, in view of Song, et al (US 11342033 B1), hereinafter Song.
Regarding claim 2, Zhang teaches the limitations of claim 1.
Zhang does not teach the memory controller is configured to cause the memory system to:
increment a counter for each memory cell of the one or more memory cells that stores the second logic state that is a same as a logic state written to a respective memory cell of the one or more memory cells, wherein validating the write operation is based at least in part on a value of the counter satisfying a threshold value.
Song teaches the memory controller is configured to cause the memory system to:
increment a counter for each memory cell of the one or more memory cells that stores the second logic state that is a same as a logic state written to a respective memory cell of the one or more memory cells, wherein validating the write operation is based at least in part on a value of the counter satisfying a threshold value (It appears from ¶ [0016] and ¶ [0049] of the present application that the counter increments when an incorrect logic state is detected during a program verify operation. Song teaches in Col. 6, ll. 52-55 (FIG. 1B, 152), a counting circuit configured to determine a number of memory cells that are verified to be in a data state and a determination circuit (FIG. 1B, 153) configured to determine, based on the number, whether the block is faulty.).
Regarding claim 3, Zhang teaches the limitations of claim 1.
Zhang does not teach to validate the write operation, the memory controller is configured to cause the memory system to:
increment a counter for each memory cell of the one or more memory cells that stores the second logic state that is different than the respective first logic state written to a respective memory cell of the one or more memory cells, wherein validating the write operation is based at least in part on a value of the counter being failing to satisfy a threshold value (It appears from ¶ [0016] and ¶ [0049] of the present application that the counter increments when an incorrect logic state is detected during a program verify operation. Song teaches in Col. 6, ll. 52-55 (FIG. 1B, 152), a counting circuit configured to determine a number of memory cells that are verified to be in a data state and a determination circuit (FIG. 1B, 153) configured to determine, based on the number, whether the block is faulty.).
Regarding claim 13, Zhang teaches the limitations of claim 12.
Zhang does not teach validating the write operation comprises:
incrementing a counter for each memory cell of the one or more memory cells that stores the respective second logic state that is different than the respective first logic state written to a respective memory cell of the one or more memory cells, wherein validating the write operation is based at least in part on a value of the counter being failing to satisfy a threshold value.
Song teaches incrementing a counter for each memory cell of the one or more memory cells that stores the respective second logic state that is different than the respective first logic state written to a respective memory cell of the one or more memory cells, wherein validating the write operation is based at least in part on a value of the counter being failing to satisfy a threshold value (It appears from ¶ [0016] and ¶ [0049] of the present application that the counter increments when an incorrect logic state is detected during a program verify operation. Song teaches in Col. 6, ll. 52-55 (FIG. 1B, 152), a counting circuit configured to determine a number of memory cells that are verified to be in a data state and a determination circuit (FIG. 1B, 153) configured to determine, based on the number, whether the block is faulty.).
Regarding claim 14, Zhang teaches the limitations of claim 12.
Zhang does not teach validating the write operation comprises:
incrementing a counter for each memory cell of the one or more memory cells that stores the second logic state that is a same as a logic state written to a respective memory cell of the one or more memory cells, wherein validating the write operation is based at least in part on a value of the counter satisfying a threshold value.
Song teaches incrementing a counter for each memory cell of the one or more memory cells that stores the second logic state that is a same as a logic state written to a respective memory cell of the one or more memory cells, wherein validating the write operation is based at least in part on a value of the counter satisfying a threshold value (It appears from ¶ [0016] and ¶ [0049] of the present application that the counter increments when an incorrect logic state is detected during a program verify operation. Song teaches in Col. 6, ll. 52-55 (FIG. 1B, 152), a counting circuit configured to determine a number of memory cells that are verified to be in a data state and a determination circuit (FIG. 1B, 153) configured to determine, based on the number, whether the block is faulty.).
Regarding claims 2-3 and 13-14, it would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Song into the method of Zhang to include a counting circuit configured to determine a number of memory cells that are verified to be in a data state. The ordinary artisan would have been motivated to modify Zhang in the above manner for the purpose of determining, based on the number, whether the block is faulty (Song Col. 6, ll. 52-55).
Allowable Subject Matter
15. Claims 8 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 8 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
16. The following is a statement of reasons for the indication of allowable subject matter.
Regarding claim 8, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of receive signaling indicating a quantity of memory portions greater than one, wherein reading the second logic state is based on the quantity of memory sections.
Regarding claim 9, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of the memory controller is configured to cause the memory system to:
bias a third word line of the plurality of word lines to the first voltage based at least in part on receiving the command to validate the write operation, wherein the third word line corresponds to a third memory portion of the plurality of memory portions; and
apply a third read pulse to the third word line based at least in part on biasing the third word line to the first voltage, wherein reading the second logic state from the one or more memory cells the first memory portion and the second memory portion is based at least in part on applying the third read pulse to the third word line.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRADLEY COON whose telephone number is (571)270-0740. The examiner can normally be reached M-F 8am-5pm (Eastern).
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/B.S.C./Examiner, Art Unit 2827
/AMIR ZARABIAN/ Supervisory Patent Examiner, Art Unit 2827