Prosecution Insights
Last updated: July 17, 2026
Application No. 18/782,574

ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THE SAME

Non-Final OA §103
Filed
Jul 24, 2024
Priority
Aug 31, 2023 — provisional 63/535,812 +1 more
Examiner
BURNS, TREMESHA WILLIS
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Innolux Corporation
OA Round
1 (Non-Final)
78%
Grant Probability
Favorable
1-2
OA Rounds
6m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allowance Rate
673 granted / 867 resolved
+9.6% vs TC avg
Strong +18% interview lift
Without
With
+17.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
54 currently pending
Career history
887
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
47.2%
+7.2% vs TC avg
§102
49.9%
+9.9% vs TC avg
§112
1.8%
-38.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 867 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Claims 1 - 12 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group, there being no allowable generic or linking claim. Election was made with traverse in the reply filed on June 1, 2026. The Restriction Requirement still stands for reasons as set forth in the Requirement for Restriction filed on April 6, 2026. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Clais 13 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Pietambaram et al. (U.S. Patent Publication No. 2023/0092242) in view of Lee et al. (WO 2021/020716). Regarding claim 13, in Figure 3A, Pietambaram discloses an electronic device, comprising: a substrate (comprising layers 334, 330) having a first hole (hole with passive element 347 disposed therein) and a second hole (hole with a copper pillar 572 disposed therein, Figure 5H); an electronic component (347) disposed in the first hole; a connection structure (572) disposed in the second hole; and a first conductive layer (pads 308 disposed on upper surface of layers 334/330) disposed on the first surface of the substrate, wherein the electronic component is electrically connected to the connection structure via the first conductive layer (Figure 3A), a top view profile of the first hole has a different shape from a top view profile of the second hole (Figure 3A), and the top view profile of the first hole comprises a plurality of straight sides, with adjacent ones of the straight sides connected by an arc side. Pietambaram does not specifically disclose the top view profile of the first hole comprising a plurality of straight sides, with adjacent ones of the straight sides connected by an arc side. However, in Figure 7b, Lee teaches top view profile of a first hole (220, Figure 6a; hole 220 is surrounding pad 242) comprising a plurality of straight sides (L1, L2), with adjacent ones of the straight sides connected by an arc side (L3). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the first hole of Pietambaram to have a top view profile comprising a plurality of straight sides with adjacent ones of the straight sides connected by an arc side as taught by Lee in that designing for various through hole shapes in a substrate of an electronic device is common place and well known in the art, and is merely a design option for a skilled artisan without the exercise of inventive skill. Further, more than a mere change of form or rearrangement of parts is necessary for patentability (See Span-Deck Inc. v. Fab-Con, Inc. (CA 8, 1982) 215 USPQ 835), in which it was held that, change in form of any element of prior patent must result in more than useful natural phenomenon that man has accumulated through common knowledge; even though use of new device greatly improves field and provides great utility, and commercial success is enjoyed because of long-felt need, these features cannot sustain patentability where involved is only extended application of obvious attributes from prior art. Regarding claim 14, Pietambaram discloses wherein extension lines of the adjacent ones of straight sides of the top view profile of the first hole intersect at a virtual point, the virtual point is spaced apart from the arc side by a shortest distance d, and a maximum width w of the first hole and the shortest distance d satisfy the following equation: PNG media_image1.png 87 13 media_image1.png Greyscale 0<d/w 0.1 (Figure 3A). Regarding claim 15, Pietambaram discloses wherein in a cross-sectional view of the electronic device, the substrate has a thickness T, a side surface of the second hole is an arc plane with a radius of curvature a, and the thickness T and the radius of curvature a satisfy the following equation: PNG media_image1.png 87 13 media_image1.png Greyscale T/2 < a10T (Figure 3A). Regarding claim 16, Pietambaram discloses a second conductive layer disposed on a second surface opposite to the first surface of the substrate; another electronic component disposed on a side of the first conductive layer away from the substrate and electrically connected to the first conductive layer; and a solder structure disposed on a side of the second conductive layer away from the substrate and electrically connected to the second conductive layer, wherein the connection structure has a first plane that is a flat plane adjacent to the first surface and a second plane that is an arc plane adjacent to the second surface (Figure 3A). Regarding claim 17, Pietambaram discloses wherein in a cross-sectional view of the electronic device, the second plane has a protruding thickness T1 relative to the second surface and has a width W1, and the protruding thickness T1 and the width W1 satisfy the following equation: 0.05 <T1/W1< 0.3 (Figure 3A). Regarding claim 18, Pietambaram discloses wherein the first hole is a blind hole and the second hole is a through hole (Figure 3A). Regarding claim 19, Pietambaram discloses wherein the top view profile of the first hole is approximately rectangular, and the top view profile of the second hole is approximately circular (Figure 3A). Regarding claim 20, Pietambaram discloses wherein in a cross-sectional view of the electronic device, the substrate has a thickness T, a groove at an edge of the electronic device has a depth D, and the thickness T and the depth D satisfy the following equation: 0.1 PNG media_image1.png 87 13 media_image1.png Greyscale D/T <1 (Figure 3A). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to TREMESHA W BURNS whose telephone number is (571)270-3391. The examiner can normally be reached Monday-Friday 8am - 4:30 pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at (571) 272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. TREMESHA W. BURNS Primary Examiner Art Unit 2847 /TREMESHA W BURNS/Primary Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Jul 24, 2024
Application Filed
Jun 17, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
78%
Grant Probability
95%
With Interview (+17.7%)
2y 6m (~6m remaining)
Median Time to Grant
Low
PTA Risk
Based on 867 resolved cases by this examiner. Grant probability derived from career allowance rate.

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