DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a NON-FINAL OFFICE ACTION in response to the Amendment/ Remarks filed 07/14/2026. Claims 5, 7, 8, 13 and 15-20 have been cancelled.
Claims 1-4, 6, 9-12, 14 and 21-30 are pending in the Application, of which Claims 1, 9 and 28 are independent.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/13/2026 has been entered.
Continuity/ Priority Information
The present Application 18782624 filed 07/24/2024 Claims Priority from Provisional Application 63534479, filed 08/24/2023.
Response to Arguments
Applicant's arguments, see Amendment/ Remarks filed 07/14/2026, with respect to the rejection of Claims 1-4, 6, 9-12, 14 and 21-30 under 35 U.S.C. 102(a)(1) as being anticipated by Shuma (U.S. Patent No. 7,386,771), have been fully considered but they are not persuasive, as set forth in the present office action.
Applicant argues that Shuma fails to teach or suggest "a multiplexer configured …..to determine a number of available redundant memory locations for the first address range based on an output of the multiplexer" as currently amended in claim 1.
In response to Applicant arguments, the Examiner notes that the claimed multiplexer is functionally equivalent to Shuma’s repair circuit 130, because they both perform the same function, i.e. of determining a number of available redundant memory locations in memory. According to Applicant’s specification, para. [00073] the multiplexer 255 can allow the memory device 130 to determine a number of redundant memory locations used for the received memory address. As best understood, the memory device 130 determines the number of available redundant memory locations and not the multiplexer as suggested by Applicant.
Nevertheless, for example, Shuma discloses FIG. 3, in the step 350a, the repair circuit 130 determines whether there is an available redundant memory location in the redundant memory 114. In response to the repair circuit 130 determining that there is an available redundant memory location in the redundant memory 114, the repair circuit 130 selects the available redundant location of the redundant memory 114 and re-routes the defective main memory 110 first word address to the selected redundant memory 114 location address.
Clearly, according to Shuman, as illustrated in FIG. 3, the repair circuit 130, which is equivalent to the claimed multiplexer, determines a number of available redundant memory locations 114 that are allocated to the defective main memory 110 corresponding to the claimed “first address range”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6, 9-12, 14 and 21-30 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shuma (U.S. Patent No. 7,386,771) Pub. Date: 2008-06-10.
Regarding independent Claims 1, 9 and 28, Shuma discloses a hard failure repair during normal operation using an ECC (Error Correction Code) circuit and a hard fail identifier circuit, comprising.
a memory array comprising a plurality of memory cells addressable by respective addresses; and control logic, coupled with the memory array, to perform operations: FIG. 1 a memory sub-system 100, comprising a main memory 110 “memory array”, an ECC (Error Correction Code) circuit 112, a redundant memory 114, a hard fail identifier circuit 120, a repair circuit 130, and a threshold setting circuit 140 corresponding to “control logic”.
detecting one or more errors associated with one or more stored data items corresponding to a first address range of the one or more address ranges;
FIG. 3, in step 310, the ECC circuit 112 of FIG. 1 detects whether a bit fail occurs in the main memory 110 during the normal operation of the main memory 110. As an example, during the normal operation of the memory subsystem 100, assume that the ECC circuit 112 detects a first bit fail at a first bit location of a first word address in the main memory 110. Then a step 315 is performed in which the ECC circuit 112 notifies the first bit fail to the hard fail identifier circuit 120. More specifically, in one embodiment, the ECC circuit 112 sends the error flag signal 112a to notify the hard fail identifier circuit 120 about the first bit fail.
determine that a number of the one or more stored data items exceeds a number of available redundant memory locations for the first address range;
Next, FIG. 3, in the step 340a, the control circuit 122 determines whether the fail count field 226a4 of the first bit fail is equal to a predetermined threshold value that was provided previously by the threshold setting circuit 140 of FIG. 1 via the threshold count signal 140a. More specifically, the control circuit 122 compares the value of the fail count field 226a4 that comes via the fail count signal 126b with the predetermined threshold value that comes via the threshold count signal 140a.
remap an association of a first memory address ……… to a second address ………, wherein the second address range comprises one or more available redundant memory locations. In one embodiment, in the step 350a, the repair circuit 130 determines whether there is an available redundant memory location in the redundant memory 114. In response to the repair circuit 130 determining that there is an available redundant memory location in the redundant memory 114, the repair circuit 130 selects the available redundant location of the redundant memory 114 and re-routes “remap” the defective main memory 110 first word address to the selected redundant memory 114 location address.
Regarding Claims 2, 3, 6, 10, 11, Shuma discloses detect one or more errors associated with one or more stored data items; in step 310, the ECC circuit 112 of FIG. 1 detects whether a bit fail occurs in the main memory 110 during the normal operation of the main memory 110.
determine that a number of the one or more stored data items exceeds a number of available redundant memory locations; Next, in one embodiment, in the step 340a, the control circuit 122 determines whether the fail count field 226a4 of the first bit fail is equal to a predetermined threshold value that was provided previously by the threshold setting circuit 140 of FIG. 1 via the threshold count signal 140a.
remap an association of a second memory address of at least one of the stored data items from a third address …. in a third address range, wherein the third address range comprises one or more available redundant memory locations. in the step 350a, in response to the repair circuit 130 determining that there is an available redundant memory location in the redundant memory 114, the repair circuit 130 selects the available redundant location of the redundant memory 114 and re-routes “remap” the defective main memory 110 first word address to the selected redundant memory 114 location address. It should be noted that a main memory 110 location that causes failure a number of times equal to the predetermined threshold value is considered defective and needs to be replaced by an available redundant location of the redundant memory 114.
Regarding Claims 4, 12, 14, Shuma discloses receive a memory address associated with the first address range; compare the received memory address with a second stored memory address indicating a physical location associated with the memory address; and determine a number of unavailable redundant memory locations. Next, in one embodiment, in the step 340a, the control circuit 122 determines whether the fail count field 226a4 of the first bit fail is equal to a predetermined threshold value that was provided previously by the threshold setting circuit 140 of FIG. 1 via the threshold count signal 140a. More specifically, the control circuit 122 compares the value of the fail count field 226a4 that comes via the fail count signal 126b with the predetermined threshold value that comes via the threshold count signal 140a.
determine a difference between a threshold number of available redundant memory locations and the number of unavailable redundant memory locations; compare the difference with the number of one or more stored data items. in the step 350a, the repair circuit 130 determines whether there is an available redundant memory location in the redundant memory 114. In response to the repair circuit 130 determining that there is an available redundant memory location in the redundant memory 114, the repair circuit 130 selects the available redundant location of the redundant memory 114 and re-routes the defective main memory 110 first word address to the selected redundant memory 114 location address. It should be noted that a main memory 110 location that causes failure a number of times equal to the predetermined threshold value is considered defective and needs to be replaced by an available redundant location of the redundant memory 114.
Regarding Claims 21, 22, Shuma discloses wherein each address range of the plurality of address ranges is associated with a respective set of one or more redundant memory locations, and wherein the first address range corresponds to a physical row of memory cells, a physical column of memory cells, or a page of memory cells. FIG. 1 illustrates a memory sub-system 100, comprises a main memory 110, an ECC (Error Correction Code) circuit 112, a redundant memory 114, “redundant memory locations” a hard fail identifier circuit 120, a repair circuit 130, and a threshold setting circuit 140, and a word address signal 112b “physical row”.
Regarding Claims 23, 24, Shuma discloses wherein the control logic is configured to determine the number of available redundant memory locations for the first address range based on the address table, and ……based on an output of the multiplexer. In one embodiment, in the step 350a, the repair circuit 130 determines whether there is an available redundant memory location in the redundant memory 114. In response to the repair circuit 130 determining that there is an available redundant memory location in the redundant memory 114, the repair circuit 130 selects the available redundant location of the redundant memory 114 and re-routes the defective main memory 110 first word address to the selected redundant memory 114 location address.
Regarding Claim 25, Shuma discloses wherein ……during a read operation, and wherein at least one address of the first address range is replaceable by an address of a redundant address range. In the step 350a, it should be noted that a main memory 110 location that causes failure a number of times equal to the predetermined threshold value is considered defective and needs to be replaced by an available redundant location of the redundant memory 114. Next, the repair circuit 130 sends the repaired data signal 130a and a write repaired data signal 130b to the redundant memory 114. This causes the repaired data 130a to be written into the selected location in the redundant memory 114.
Regarding Claim 26, Shuma discloses wherein a threshold number ……. is based on an error-correction-code (ECC) limit, or a memory management algorithm. In summary, the ECC circuit 112 of FIG. 1 detects the first bit fail and notifies to the hard fail identifier circuit 120 of FIG. 1. In response, the hard fail identifier circuit 120 of FIG. 1 stores the first bit fail into the entry 226a of the failure stack 126.
Regarding Claim 27, Shuma discloses wherein the control logic is configured to update the address register to reflect the remap of the association of the first memory address. In one embodiment, the failure stack 126 comprises multiple entries (like entries 226a, 226b, and 226c). In FIG. 2, the entry 226a comprises a use bit 226a1, an address field 226a2, a bit location field 226a3, a fail count field 226a4, and an age field 226a5. Illustratively, the use bit 226a1 indicates whether the entry 226a is available or unavailable; the address field 226a2 stores address of the fail wordline; and the bit location field 226a3 indicates the location of a bit fail in the fail wordline.
Regarding Claims 29, 30, Shuma discloses detect one or more errors associated with one or more data items stored at memory cells; and remap an association of a second memory address of at least one of the data items. In one embodiment, in step 310, the ECC circuit 112 of FIG. 1 detects whether a bit fail occurs in the main memory 110 during the normal operation of the main memory 110. As an example, during the normal operation of the memory subsystem 100, assume that the ECC circuit 112 detects a first bit fail at a first bit location of a first word address in the main memory 110.
In one embodiment, in the step 350a, the repair circuit 130 determines whether there is an available redundant memory location in the redundant memory 114. In response to the repair circuit 130 determining that there is an available redundant memory location in the redundant memory 114, the repair circuit 130 selects the available redundant location of the redundant memory 114 and re-routes the defective main memory 110 first word address to the selected redundant memory 114 location address.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES C KERVEROS whose telephone number is (571)272-3824. The examiner can normally be reached 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARK FEATHERSTONE can be reached at (571) 270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAMES C KERVEROS/Primary Examiner, Art Unit 2111
Date: August 24, 2026
Non-Final Rejection 20260821
JAMES C. KERVEROS
Primary Examiner, Art Unit 2111
James.Kerveros@USPTO.GOV
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