DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a NON-FINAL OFFICE ACTION in response to the present Application filed 07/24/2024. Claims 1-20 are pending in the Application, of which Claims 1, 9 and 17 are independent.
Continuity/ Priority Information
The present Application 18782624 filed 07/24/2024 Claims Priority from Provisional Application 63534479, filed 08/24/2023.
Claim Objections
Claims 1-8 and 17-20 objected to because of the following informalities:
Claim 1, amend to recite “control logic, operatively coupled with the memory array, configured to
Claim 17, “control logic, operatively coupled with the memory array, configured to receive a memory address;”
Any Claims not specifically mentioned above are objected due to their dependency on an objected claim. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 9 and 17, “detect one or more errors associated with one or more stored data items corresponding to a first address range of the one or more address ranges” is indefinite because the Claims fail to clearly define the term “stored data items”. There is no sufficient support in the specification for the term in relation to the memory. For the purpose of examination, the term is interpreted as storing bits in a memory.
Claims 7, 8, 15, 16, 20, the limitation “wherein the control logic is configured to remap the association of the first memory address before a predecoder of the memory device receives the first address, and wherein the control logic is configured to remap the association of the first memory address at a predecoder of the memory device” is indefinite, because the Claims fail to define the time in relation to the event, i.e. ”remapping the association of the first memory address before a predecoder” and “remapping the association of the first memory address at a predecoder”.
Any Claims not specifically mentioned above are rejected due to their dependency on a rejected claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shuma (U.S. Patent No. 7,386,771) Pub. Date: 2008-06-10.
Regarding independent Claims 1, 9 and 17, Shuma discloses a hard failure repair during normal operation using an ECC (Error Correction Code) circuit and a hard fail identifier circuit, comprising.
a memory array comprising a plurality of memory cells addressable by respective addresses; and control logic, coupled with the memory array, to perform operations: FIG. 1 a memory sub-system 100, comprising a main memory 110 “memory array”, an ECC (Error Correction Code) circuit 112, a redundant memory 114, a hard fail identifier circuit 120, a repair circuit 130, and a threshold setting circuit 140 corresponding to “control logic”.
detecting one or more errors associated with one or more stored data items corresponding to a first address range of the one or more address ranges;
FIG. 3, in step 310, the ECC circuit 112 of FIG. 1 detects whether a bit fail occurs in the main memory 110 during the normal operation of the main memory 110. As an example, during the normal operation of the memory subsystem 100, assume that the ECC circuit 112 detects a first bit fail at a first bit location of a first word address in the main memory 110. Then a step 315 is performed in which the ECC circuit 112 notifies the first bit fail to the hard fail identifier circuit 120. More specifically, in one embodiment, the ECC circuit 112 sends the error flag signal 112a to notify the hard fail identifier circuit 120 about the first bit fail.
Determine that a number of the one or more stored data items exceeds a number of available redundant memory locations for the first address range;
Next, FIG. 3, in the step 340a, the control circuit 122 determines whether the fail count field 226a4 of the first bit fail is equal to a predetermined threshold value that was provided previously by the threshold setting circuit 140 of FIG. 1 via the threshold count signal 140a. More specifically, the control circuit 122 compares the value of the fail count field 226a4 that comes via the fail count signal 126b with the predetermined threshold value that comes via the threshold count signal 140a.
remap an association of a first memory address ……… to a second address ………, wherein the second address range comprises one or more available redundant memory locations. In one embodiment, in the step 350a, the repair circuit 130 determines whether there is an available redundant memory location in the redundant memory 114. In response to the repair circuit 130 determining that there is an available redundant memory location in the redundant memory 114, the repair circuit 130 selects the available redundant location of the redundant memory 114 and re-routes “remap” the defective main memory 110 first word address to the selected redundant memory 114 location address.
Regarding Claims 2, 3, 10, 11, Shuma discloses detect one or more errors associated with one or more stored data items; in step 310, the ECC circuit 112 of FIG. 1 detects whether a bit fail occurs in the main memory 110 during the normal operation of the main memory 110.
determine that a number of the one or more stored data items exceeds a number of available redundant memory locations;
Next, in one embodiment, in the step 340a, the control circuit 122 determines whether the fail count field 226a4 of the first bit fail is equal to a predetermined threshold value that was provided previously by the threshold setting circuit 140 of FIG. 1 via the threshold count signal 140a.
remap an association of a second memory address of at least one of the stored data items from a third address …. in a third address range, wherein the third address range comprises one or more available redundant memory locations. in the step 350a, in response to the repair circuit 130 determining that there is an available redundant memory location in the redundant memory 114, the repair circuit 130 selects the available redundant location of the redundant memory 114 and re-routes “remap” the defective main memory 110 first word address to the selected redundant memory 114 location address. It should be noted that a main memory 110 location that causes failure a number of times equal to the predetermined threshold value is considered defective and needs to be replaced by an available redundant location of the redundant memory 114.
Regarding Claims 4, 5, 12, 13,14, Shuma discloses receive a memory address associated with the first address range; compare the received memory address with a second stored memory address indicating a physical location associated with the memory address; and determine a number of unavailable redundant memory locations. Next, in one embodiment, in the step 340a, the control circuit 122 determines whether the fail count field 226a4 of the first bit fail is equal to a predetermined threshold value that was provided previously by the threshold setting circuit 140 of FIG. 1 via the threshold count signal 140a. More specifically, the control circuit 122 compares the value of the fail count field 226a4 that comes via the fail count signal 126b with the predetermined threshold value that comes via the threshold count signal 140a.
determine a difference between a threshold number of available redundant memory locations and the number of unavailable redundant memory locations; compare the difference with the number of one or more stored data items. in the step 350a, the repair circuit 130 determines whether there is an available redundant memory location in the redundant memory 114. In response to the repair circuit 130 determining that there is an available redundant memory location in the redundant memory 114, the repair circuit 130 selects the available redundant location of the redundant memory 114 and re-routes the defective main memory 110 first word address to the selected redundant memory 114 location address. It should be noted that a main memory 110 location that causes failure a number of times equal to the predetermined threshold value is considered defective and needs to be replaced by an available redundant location of the redundant memory 114.
Regarding Claims 6, 18, Shuma discloses determine a number of the one or more available redundant memory locations in the second address range is equal to or exceeds the number of errors. Next, in one embodiment, in the step 340a, the control circuit 122 determines whether the fail count field 226a4 of the first bit fail is equal to a predetermined threshold value that was provided previously by the threshold setting circuit 140 of FIG. 1 via the threshold count signal 140a. More specifically, the control circuit 122 compares the value of the fail count field 226a4 that comes via the fail count signal 126b with the predetermined threshold value that comes via the threshold count signal 140a. Assume that the predetermined threshold value is 3.
Regarding Claims 7, 8, 15, 16, 20, Shuma discloses wherein the control logic is configured to remap the association of the first memory address before a predecoder of the memory device receives the first address, and wherein the control logic is configured to remap the association of the first memory address at a predecoder of the memory device. In light of the 112b rejection, the Examiner interprets the limitation as disclosed by Shuma. In response, in the step 315, the ECC circuit 112 notifies the hard fail identifier circuit 120 about the third bit fail in a manner similar to the manner in which the ECC circuit 112 notifies the hard fail identifier circuit 120 about the first and the second bit fails. in the step 350a, in response to the repair circuit 130 determining that there is an available redundant memory location in the redundant memory 114, the repair circuit 130 selects the available redundant location of the redundant memory 114 and re-routes the defective main memory 110 first word address to the selected redundant memory 114 location address.
Regarding Claim 19, Shuma discloses receive the memory address; and determine at least one physical address associated with the memory address is at a redundant memory location within the second address range. FIG. 4 illustrates a memory sub-system 400. The resulting fuse arrangement is used by the FARR 116 such that whenever the word address of the bit fail appears on the address bus of the main memory 110, the replacing redundant memory 114 location “redundant memory location” is accessed instead of the defective main memory location of the main memory 110.
Prior Art References Cited
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See References Cited on PTO-892 form.
Yoel et al. (US 20130232384) see Abstract. The repair module performs the iterative testing of the array until (i) the repair module does not detect a defective memory cell or (ii) no memory cells of the memory cells that are redundant remain available for replacement of a defective memory cell.
Pekny (U.S. Patent No. 6,553,510) In another embodiment, a method of correcting random memory cell failures in a memory device includes initiating an erase operation on a plurality of primary memory cells, individually verifying each one of the plurality of primary memory cells to determine in each memory cell has been properly erased, applying one or more additional erase operations on a defective one of the plurality of primary memory cells which fails to properly verify that an erase operation was successful, and programming access circuitry to replace the defective memory cell with an available redundant memory cell.
Kobayashi (U.S. Patent No. 6,523,143) Description of the Related Art. Thus, there is available a method in which the memory device is equipped with a redundant structure in advance, so that a failure cell can be saved by replacing the failure cell with a spare memory. In this method, a memory device which is non-defective as a whole can be produced even though part of cell is defective, so that the yield can be improved. Moreover, a defective spot can be scrutinized so as to perform the failure analysis for finding and mending a cause of the failure, thus being desirable in the course of improving the yield of the devices.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES C KERVEROS whose telephone number is (571)272-3824. The examiner can normally be reached 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARK FEATHERSTONE can be reached at (571) 270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAMES C KERVEROS/Primary Examiner, Art Unit 2111
Date: January 29, 2026
Non-Final Rejection 20260126
JAMES C. KERVEROS
Primary Examiner, Art Unit 2111
James.Kerveros@USPTO.GOV