Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The following is in response to the communication filed 7/24/2024.
Claims 1-20 are currently pending.
Claims 1-20 have been examined.
Priority
Applicant' s claim for the benefit of prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, or 365(c) is acknowledged.
The application is the continuation of 18451366 filed 09/27/2021, being a continuation of 17486633 filed 09/27/2021, where 17486633 filed 10/18/2019, being a continuation of 16657696 filed 10/18/2019, where 16657696 claims benefit to Provisional Patent Application Serial No. 62/902,207 and 62/748,653 filed 9/18/2019 and 10/22/2018 has been received and acknowledged
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 9/5/2024 has been considered by the Examiner.
Applicant is reminded that per MPEP 2004, it is desirable to avoid the submission of long lists of documents if it can be avoided and that if a long list is submitted, Applicant is encouraged to highlight those documents which have been specifically brought to Applicant’s attention and/or are known to be of most significance. Applicant is also encouraged to submit a concise statement of the relevance of each reference in the IDS(s).
For this application, it is noted that the aforementioned IDSs collectively include a very lengthy list of documents. As best as can be ascertained from the record, however, no particular listed document has been specifically brought to the Examiner's attention or otherwise highlighted to be of particular significance. Thus, by signing the accompanying IDS document(s), the Examiner is acknowledging the submission of the document(s) and indicating that a cursory review has been made of the listed document only to the extent reasonably possible in view of the very large number of documents listed.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
INTERCONNECT STRUCTURES WITH EMBEDDED FILL LAYERS
Claim Objections
Claim 6 is objected to because of the following informalities:
Claim 6 includes the number “7” before rest of the claim. The Examiner believes this to be an typo and suggests that it be removed in any subsequent action.
Appropriate correction is required.
Claim Rejections - 35 USC § 101
Double Patenting:
STATUTORY:
A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101.
Claims 1-20 are rejected under 35 U.S.C. 101 as claiming the same invention as that of claims 1, 3-18, and 20-23 of prior U.S. Patent No. 11756880. This is a statutory double patenting rejection.
U.S. Application 18782629
U.S. Patent No. 11756880
1. A method of manufacturing a device, the method comprising:
forming a cavity in a substrate extending at least partially through a thickness of the substrate from a surface of the substrate;
providing a conductive material in the cavity and over the surface of the substrate;
removing a portion of the conductive material thereby forming a recess on an upper surface of the conductive material;
providing a fill layer over the upper surface of the conductive material and the surface of the substrate;
removing at least a portion of the fill layer to expose at least a portion of the conductive material; and
forming a second cavity in the substrate extending at least partially though the thickness of the substrate from the surface of the substrate, a width of the second cavity being wider than a width of the cavity.
1. A method of manufacturing a device, the method comprising:
forming a cavity in a substrate extending at least partially through a thickness of the substrate from a surface of the substrate;
providing a conductive material in the cavity and over the surface of the substrate;
removing a portion of the conductive material thereby forming a recess on an upper surface of the conductive material;
providing a fill layer over the upper surface of the conductive material and the surface of the substrate;
removing at least a portion of the fill layer to expose at least a portion of the conductive material; and
forming a second cavity in the substrate extending at least partially though the thickness of the substrate from the surface of the substrate, a width of the second cavity being wider than a width of the cavity.
2. The method of claim 1, further comprising preparing the substrate for direct bonding.
3. The method of claim 1, further comprising preparing the substrate for direct bonding.
3. The method of claim 1, wherein the removing the portion of the fill layer comprises preparing the substrate for direct bonding.
4. The method of claim 1, wherein the removing the portion of the fill layer comprises preparing the substrate for direct bonding.
4. The method of claim 1, wherein the removing the portion of the fill layer defines a bonding surface including the surface of the substrate, a portion of the upper surface of the conductive material, and the fill layer disposed in the recess.
5. The method of claim 1, wherein the removing the portion of the fill layer defines a bonding surface including the surface of the substrate, a portion of the upper surface of the conductive material, and the fill layer disposed in the recess.
5. The method of claim 1, further comprising providing a barrier layer in the cavity and over the surface of the substrate before providing the conductive material.
6. The method of claim 1, further comprising providing a barrier layer in the cavity and over the surface of the substrate before providing the conductive material.
6. The method of claim 1, further comprising providing a seed layer in the cavity and over the surface of the substrate before providing the conductive material.
7. The method of claim 1, further comprising providing a seed layer in the cavity and over the surface of the substrate before providing the conductive material.
7. The method of claim 1, wherein the substrate comprises silicon dioxide.
8. The method of claim 1, wherein the substrate comprises silicon dioxide
8. The method of claim 1, wherein the fill layer comprises a dielectric material or a conductive material.
9. The method of claim 1, wherein the fill layer comprises a dielectric material.
10. The method of claim 1, wherein the fill layer comprises a conductive material.
9. The method of claim 1, further comprising providing the conductive material in the second cavity.
11. The method of claim 1, further comprising providing the conductive material in the second cavity.
10. A method of manufacturing a microelectronic assembly comprising:
providing the device of claim 1;
providing a second device comprising a conductive feature and a non-conductive region;
directly bonding the surface of the substrate of the device and the non-conductive region of the second device without an intervening adhesive; and
directly bonding the conductive material of the device and the conductive feature of the second device.
12. A method of manufacturing a microelectronic assembly comprising:
providing the device of claim 1;
providing a second device comprising a conductive feature and a non-conductive region;
directly bonding the surface of the substrate of the device and the non-conductive region of the second device without an intervening adhesive; and
directly bonding the conductive material of the device and the conductive feature of the second device.
11. The method of claim 1, wherein a depth of the recess is greater than 20 nm.
13. The method of claim 1, wherein a depth of the recess is larger than 20 nm.
12. The method of claim 1, wherein a depth of the cavity is greater than 100 nm.
14. The method of claim 1, wherein a depth of the cavity is greater than 100 nm.
13. The method of claim 1, wherein a melting point of the fill layer is higher than a melting point of the conductive material.
15. The method of claim 1, wherein a melting point of the fill layer is higher than a melting point of the conductive material.
14. A method of manufacturing a microelectronic assembly, the method comprising:
providing a first device having a first conductive feature disposed in a first cavity formed in a first substrate and a fill material disposed in a recess formed in the first conductive feature, a portion of the conductive feature and a portion of the fill material defining a contact surface of a contact pad;
providing a second device having a second conductive feature disposed in a second cavity formed in a second substrate; and
bonding the first device and the second device such that the first substrate is directly bonded to the second substrate without an intervening adhesive, and the contact surface of the contact pad directly bonded to the second conductive feature without an intervening adhesive.
16. A method of manufacturing a microelectronic assembly, the method comprising:
providing a first device having a first conductive feature disposed in a first cavity formed in a first substrate and a fill material disposed in a recess formed in the first conductive feature, a portion of the conductive feature and a portion of the fill material defining a contact surface of a contact pad;
providing a second device having a second conductive feature disposed in a second cavity formed in a second substrate; and
bonding the first device and the second device such that the first substrate is directly bonded to the second substrate without an intervening adhesive, and the contact surface of the contact pad directly bonded to the second conductive feature without an intervening adhesive.
15. The method of claim 14, wherein the first device further comprises a plurality of conductive features formed in a plurality of cavities formed in the first substrate.
17. The method of claim 16, wherein the first device further comprises a plurality of conductive features formed in a plurality of cavities formed in the first substrate.
16. The method of claim 14 wherein the second device further comprises a second fill material disposed in a second recess formed in the second conductive feature, the second conductive feature and the second fill material define a second contact pad.
18. The method of claim 16, wherein the second device further comprises a second fill material disposed in a second recess formed in the second conductive feature, the second conductive feature and the second fill material define a second contact pad.
17. A method of manufacturing a device: forming a cavity in a substrate extending at least partially through a thickness of the substrate from a surface of the substrate;
providing a conductive material in the cavity and over the surface of the substrate by way of a damascene technique so as to have an upper surface of the conductive material recessed below the surface of the substrate; providing a protective layer over the upper surface of the conductive material; and removing at least a portion of the protective layer and at least a portion of the conductive material above the surface of the substrate after providing the protective layer to form a bonding surface defined at least partially by the conductive material, the bonding surface pre-pared to bond to another device.
20. A method of manufacturing a device:
forming a cavity in a substrate extending at least partially through a thickness of the substrate from a surface of the substrate;
providing a conductive material in the cavity and over the surface of the substrate by way of a damascene technique so as to have an upper surface of the conductive material recessed below the surface of the substrate;
providing a protective layer over the upper surface of the conductive material; and
removing at least a portion of the protective layer and at least a portion of the conductive material above the surface of the substrate after providing the protective layer to form a bonding surface defined at least partially by the conductive material, the bonding surface prepared to bond to another device.
18. The method of claim 17, wherein the protective layer comprises SiC, SiC/SiO2, or SiN/SiO2.
21. The method of claim 20, wherein the protective layer comprises SiC, SiC/SiO2, or SiN/SiO2.
19. The method of claim 17, wherein the protective layer comprises tungsten, an alloy of tungsten, nickel, a nickel alloy, cobalt, an alloy of cobalt, tantalum, an alloy of tantalum, titanium, or an alloy of titanium.
22. The method of claim 20, wherein the protective layer comprises tungsten, an alloy of tungsten, nickel, a nickel alloy, cobalt, an alloy of cobalt, tantalum, an alloy of tantalum, titanium, or an alloy of titanium.
20. The method of claim 17, wherein the removing the portion of the protective layer and the portion of the conductive material defines a bonding surface including the surface of the substrate, the conductive material, and the protective layer.
23. The method of claim 20, wherein the removing the portion of the protective layer and the portion of the conductive material defines a bonding surface including the surface of the substrate, the conductive material, and the protective layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HEIM KIRIN GREWAL whose telephone number is (703)756-1515. The examiner can normally be reached Monday - Thursday 9:30 a.m. - 5:30 p.m. EST.
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/HEIM KIRIN GREWAL/Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812
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