DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
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Claims 1-26 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-26 of U.S. Patent No. 12,052,160. Although the claims at issue are not identical, they are not patentably distinct from each other because they contain substantially similar subject matter (see chart below.
Claims 2-8, 10-17 and 19-26 are also rejected as being dependent on claims 1, 9 and 18 respectively, and may also correspond to claims 2-8, 10-17 and 19-26 of the ‘160 patent.
Instant Application
US Patent No. 12,052,160
1. A field programmable gate array (FPGA) apparatus comprising: a plurality of logic block tiles including one or more first logic block tiles and one or more second logic block tiles, wherein one or more first wires are coupled to one or more outputs of the one or more first logic block tiles; and one or more additional connections extending from the one or more outputs of the one or more first logic block tiles to the one or more second logic block tiles, wherein the one or more second logic block tiles are neighboring logic block tiles to the one or more first logic block tiles, and wherein the one or more additional connections are added to the one or more outputs of the one or more first logic block tiles to drive one or more second wires that start at one or more outputs of the one or more second logic block tiles.
1. An field programmable gate array (FPGA) apparatus comprising: a plurality of logic block tiles including one or more first logic block tiles and one or more second logic block tiles, wherein one or more first wires are coupled to one or more outputs of the one or more first logic block tiles; and one or more (direct) connections extending from the one or more outputs of the one or more first logic block tiles to (one or more inputs of output multiplexors (muxes) of) the one or more second logic block tiles, wherein the one or more second logic block tiles are neighboring logic block tiles to the one or more first logic block tiles, and wherein the one or more (direct) connections are to drive one or more second wires that are coupled to one or more outputs of the one or more second logic block tiles.
9. An apparatus, comprising: a memory; and a processor coupled to the memory, wherein the processor is configured to: determine routing for one or more first logic block tiles of a plurality of FPGA logic block tiles, wherein one or more first wires are coupled to one or more outputs of the one or more first logic block tiles; determine routing for one or more second logic block tiles of the plurality of FPGA logic block tiles that are neighboring block tiles to the one or more first logic block tiles; and additionally connect the one or more outputs of the one or more first logic block tiles to the one or more second logic block tiles to drive one or more second wires that start at one or more outputs of the one or more second logic block tiles.
9. An apparatus, comprising: a memory; and a processor coupled to the memory, wherein the processor is configured to: determine routing for one or more first logic block tiles of a plurality of FPGA logic block tiles, wherein one or more first wires are coupled to one or more outputs of the one or more first logic block tiles; determine routing for one or more second logic block tiles of the plurality of FPGA logic block tiles that are neighboring block tiles to the one or more first logic block tiles; and (directly) connect the one or more outputs of the one or more first logic block tiles to (one or more inputs of output multiplexors (muxes) of) the one or more second logic block tiles to drive one or more second wires that are coupled to one or more outputs of the one or more second logic block tiles.
18. A non-transitory machine readable medium storing instructions that cause a data processing system to perform operations comprising: determining routing for one or more first logic block tiles of a plurality of FPGA logic block tiles, wherein one or more first wires are coupled to one or more outputs of the one or more first logic block tiles; determining routing for one or more second logic block tiles of the plurality of FPGA logic block tiles that are neighboring block tiles to the one or more first logic block tiles, and additionally connecting the one or more outputs of the one or more first logic block tiles to the one or more second logic block tiles to drive one or more second wires that start at one or more outputs of the one or more second logic block tiles.
18. A non-transitory machine readable medium storing instructions that cause a data processing system to perform operations comprising: determining routing for one or more first logic block tiles of a plurality of FPGA logic block tiles, wherein one or more first wires are coupled to one or more outputs of the one or more first logic block tiles; determining routing for one or more second logic block tiles of the plurality of FPGA logic block tiles that are neighboring block tiles to the one or more first logic block tiles, and (directly) connecting the one or more outputs of the one or more first logic block tiles to (one or more inputs of output multiplexors (muxes) of) the one or more second logic block tiles to drive one or more second wires that are coupled to one or more outputs of the one or more second logic block tiles.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 5-6, 8-10, 13-14, 16, 18-19, 22-23 and 25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gribok et al. (US 2019/0324724).
In regards to claim 1, Gribok discloses of a field programmable gate array (FPGA, see Paragraphs 0002, 0020-0021, 0024) apparatus comprising: a plurality of logic block tiles (for example 48, 122A-B, 182A-G, 222A-B see Figs 2, 4, 6, 8 and Paragraphs 0024-0029) including one or more first logic block tiles (for example 122A) and one or more second logic block tiles (for example 122B), wherein one or more first wires are coupled to one or more outputs of the one or more first logic block tiles (122A); and one or more additional connections (see 134) extending from the one or more outputs of the one or more first logic block tiles (122A) to the one or more second logic block tiles (122B), wherein the one or more second logic block tiles (122B) are neighboring logic block tiles to the one or more first logic block tiles (122A), and wherein the one or more additional connections (134) are added to the one or more outputs of the one or more first logic block tiles (122A) to drive one or more second wires (see 124, started and output from 132B) that start at one or more outputs of the one or more second logic block tiles (122B, see Figs 2, 4, 6, 8).
In regards to claim 2, Gribok discloses of the apparatus of claim 1 wherein the one or more first logic block tiles (122A) includes a first logic block having one or more first output muxes (132A) and the one or more second logic block tiles (122B) includes a second logic block having one or more second output muxes (132B), wherein an output of the one or more first output muxes (132A) is additionally connected to an input of the one or more second output muxes (132B, see Fig 4).
In regards to claim 5, Gribok discloses of the apparatus of claim 1, wherein the one or more additional connections (see 134) is at least one of a horizontal connection, a vertical connection, or a diagonal connection (see Fig 4).
In regards to claim 6, Gribok discloses of the apparatus of claim 1, wherein the one or more additional connections (see 134) carry a signal that is the signal on the one or more first wires (see Fig 4).
In regards to claim 8, Gribok discloses of the apparatus of claim 1, wherein a number of the one or more additional connections is determined based on a design constraint (for example see at least Paragraphs 0018, 0021-0023, 0025, 0027).
In regards to claim 9, Gribok discloses of an apparatus, comprising: a memory (see 404 in Fig 12); and a processor (see 402) coupled to the memory (404), wherein the processor (402) is configured to: determine routing for one or more first logic block tiles of a plurality of FPGA logic block tiles (48, 122A-B, 82A-G, 222A-B within 12; see Figs 2, 4, 6, 8, 12 and Paragraphs 0024-0029, 0054-0056), wherein one or more first wires are coupled to one or more outputs of the one or more first logic block tiles (for example 122A); determine routing for one or more second logic block tiles (for example 122B) of the plurality of FPGA logic block tiles that are neighboring block tiles to the one or more first logic block tiles (122A); and additionally connect (see 134) the one or more outputs of the one or more first logic block tiles (122A) to the one or more second logic block tiles (122B) to drive one or more second wires that start at one or more outputs (see 124, started and output from 132B) of the one or more second logic block tiles (122B, see Figs 2, 4, 6, 8, 12).
In regards to claim 10, Gribok discloses of the apparatus of claim 9, wherein the one or more first logic block tiles (122A) includes a first logic block having one or more first output muxes (see 132A) and the one or more second logic block tiles (122B) includes a second logic block having one or more second output muxes (see 132B), wherein the processor is further configured to additionally connect an output of the one or more first output muxes (132A) to an input of the one or more second output muxes (132B, see Fig 4).
In regards to claim 13, Gribok discloses of the apparatus of claim 10, wherein the one or more additional connections (see 134) is at least one of a horizontal connection, a vertical connection, or a diagonal connection (see Fig 4).
In regards to claim 14, Gribok discloses of the apparatus of claim 10, wherein the one or more additional connections (see 134) carry a signal that is the signal on the one or more first wires (see Fig 4).
In regards to claim 16, Gribok discloses of the apparatus of claim 10, wherein the processor is further configured to determine a number of the one or more additional connections based on a design constraint (for example see at least Paragraphs 0018, 0021-0023, 0025, 0027).
In regards to claim 18, Gribok discloses of a non-transitory machine readable medium storing instructions that cause a data processing system to perform operations comprising: determining routing for one or more first logic block tiles (for example 122A) of a plurality of FPGA logic block tiles (48, see Figs 2, 4, 6, 8 and Paragraphs 0024-0029), wherein one or more first wires are coupled to one or more outputs of the one or more first logic block tiles (122A); determining routing for one or more second logic block tiles (for example 122B) of the plurality of FPGA logic block tiles (48) that are neighboring block tiles to the one or more first logic block tiles (122A, see Fig 4), and additionally connecting (see 134) the one or more outputs of the one or more first logic block tiles (122A) to the one or more second logic block tiles (122B) to drive one or more second wires that start at one or more outputs (see 124, started and output from 132B) of the one or more second logic block tiles (122B, see Figs 2, 4, 6, 8).
In regards to claim 19, Grobok discloses of the non-transitory machine readable medium of claim 18, wherein the one or more first logic block tiles (122A) includes a first logic block having one or more first output muxes (see 132A) and the one or more second logic block tiles (122B) includes a second logic block having one or more second output muxes (see 132B), wherein the processor is further configured to additionally connect an output of the one or more first output muxes (132A) to an input of the one or more second output muxes (132B, see Fig 4).
In regards to claim 22, Gribok discloses of the non-transitory machine readable medium of claim 18, wherein the one or more additional connections (see 134) is at least one of a horizontal connection, a vertical connection, or a diagonal connection (see Fig 4).
In regards to claim 23, Gribok discloses of the non-transitory machine readable medium of claim 18, wherein the one or more additional connections (see 134) carry a signal that is the signal on the one or more first wires (see Fig 4).
In regards to claim 25, Gribok discloses of the non-transitory machine readable medium of claim 18, wherein the instructions further cause the data processing system to perform operations comprising: determining a number of the one or more additional connections based on a design constraint (for example see at least Paragraphs 0018, 0021-0023, 0025, 0027).
Conclusion
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/JASON M CRAWFORD/Primary Examiner, Art Unit 2844