DETAILED ACTION
Response to Amendment
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (U.S. Patent Application Publication Number 2023/0251866), Xie et al. (U.S. Patent Application Publication Number 2024/0134625), and Banik et al. (U.S. Patent Application Publication Number 2022/0156205).
Regarding Claim 1, Lin discloses a method comprising:
determining, by a processor (Figure 1, item 104, paragraph 0038), whether a current boot process (Figure 3, item 300) of an information handling system (Figure 1, item 100) is a first boot process of the information handling system subsequent to programming of an image (Figure 3, item 306, paragraph 0039; i.e., the BIOS 110, which is run by the CPU 104, determines whether the current boot process is the first boot process since a last BIOS update [the “image”]);
when the current boot process is the first boot process, determining whether a record in an image is to be updated (Figure 3, items 308 and 310, paragraphs 0039-0040; i.e., it is determined whether there are any modified BIOS settings in the future setting data structure; if so, then the corresponding records in the BIOS image that is stored in the flash chip are updated accordingly); and
subsequent to the updating of the record, proceeding with executing the current boot process of the information handling system (Figure 3, item 316 or 318, paragraph 0041; i.e., after the BIOS settings are updated, the current boot process 300 can proceed to either reboot the computer [step 304] or allow it to boot into the OS [step 318]).
Lin does not expressly disclose programming of a serial peripheral image (SPI) image with flash descriptor records common to a group of platforms that includes the information handling system;
that the record to be updated is a record of the flash descriptor records in a serial peripheral interface (SPI) image and is based on a lookup table;
updating the record in the SPI image based on data values included in the lookup table.
In the same field of endeavor (e.g., BIOS updating techniques), Xie teaches programming of a serial peripheral image (SPI) image common to a group of platforms that includes the information handling system (Figure 5, items 502, paragraph 0076; i.e., a single SPI image can be distributed two multiple system platforms 502, which indicates that it is common to those platforms);
that the record to be updated is in a serial peripheral interface (SPI) image (Figure 1, “BIOS SPI Flash”, paragraphs 0030 and 0037; i.e., a BIOS firmware image stored in an SPI flash memory) and is based on a lookup table (paragraph 0039; i.e., the firmware update includes an updated profile configuration table 214 [Figure 2] [equivalent to the claimed “lookup table”]);
updating the record in the SPI image based on data values (Figure 2, items 234, paragraph 0047) included in the lookup table (paragraphs 0039, 0041, 0055, and 0061; i.e., an existing profile configuration table ["the record in the SPI image"] is updated based on data values 234 in a received updated profile configuration table 214).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Xie’s teachings of BIOS updating techniques with the teachings of Lin, for the purpose of providing a simple and efficient mechanism to determine which exact settings of the BIOS need to be updated as opposed to having the processor have to determine which BIOS settings have been changed as required by Lin.
Also in the same field of endeavor (e.g., BIOS updating techniques), Banik teaches an SPI image (Figure 1, item 114) includes flash descriptor records (Figure 3, item 302, paragraph 0043); and
the record to be updated is a record of the flash descriptor records in the SPI image (paragraphs 0063-0064; i.e., records in the flash descriptor region 302 within the SPI image are updated).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Banik’s teachings of BIOS updating techniques with the teachings of Lin, for the purpose of providing the system with a layout of the SPI flash device and configuration parameters of the user device (see Banik, paragraph 0043). By allowing these records to be updated, the SPI image can be modified to control hardware configuration policies (see Banik, paragraph 0026).
Regarding Claim 2, Xie teaches wherein the record is a chipset configuration setting (paragraph 0046).
Regarding Claim 3, Xie teaches wherein the record is stored in a region of an SPI flash memory device (paragraphs 0037 and 0056).
Regarding Claim 4, Xie teaches wherein the lookup table is stored in a platform data region of an SPI flash memory device (paragraph 0061; i.e., the entire updated profile configuration table [the claimed “lookup table”] can replace the existing profile configuration table that is stored in a platform data region [the primary flash memory region - see paragraph 0056] of the SPI flash memory device).
Regarding Claim 5, Xie teaches wherein the SPI image is common between at least two system platforms (Figure 5, items 502, paragraph 0076; i.e., a single SPI image can be distributed two multiple system platforms 502).
Regarding Claim 6, Xie teaches wherein the updating of the record is performed by an embedded controller (paragraph 0036; i.e., a baseboard management controller [BMC] is known in the art to be a type of specialized embedded controller; see also instant specification at paragraph 0023 [“embedded controller … is similar to BMC”]).
Regarding Claim 7, Xie teaches wherein the lookup table is generated based on configuration settings of a base system platform (paragraph 0046; i.e., the updated profile configuration table contains values for hardware configuration settings such as chipset settings, hardware disk configurations, and external device configurations designed specifically for the receiving computer [the “base system platform”]).
Regarding Claim 8, Xie teaches wherein the SPI image is generated based on a base system platform (paragraph 0033; i.e., the BIOS firmware image located in the SPI flash memory contains values for hardware configuration settings such as chipset settings, hardware disk configurations, and external device configurations designed specifically for the computer on which it resides [the “base system platform”]).
Regarding Claim 9, Lin discloses an information handling system (Figure 1, item 100) comprising:
a memory (Figure 1, item 106); and
a processor (Figure 1, item 104) to communicate with the memory, the processor configured to:
determine whether a current boot process (Figure 3, item 300) of the information handling system is a first boot process of the information handling system subsequent to programming of an image (Figure 3, item 306, paragraph 0039; i.e., the BIOS 110, which is run by the CPU 104, determines whether the current boot process is the first boot process since a last BIOS update [the “image”]);
when the current boot process is the first boot process, determine whether a record in an image is to be updated (Figure 3, items 308 and 310, paragraphs 0039-0040; i.e., it is determined whether there are any modified BIOS settings in the future setting data structure; if so, then the corresponding records in the BIOS image that is stored in the flash chip [the claimed “image”] are updated accordingly); and
subsequent to the update of the record, proceed with execution of the current boot process of the information handling system (Figure 3, item 316 or 318, paragraph 0041; i.e., after the BIOS settings are updated, the current boot process 300 can proceed to either reboot the computer [step 304] or allow it to boot into the OS [step 318]).
Lin does not expressly disclose programming of a serial peripheral image (SPI) image with flash descriptor records common to a group of platforms that includes the information handling system;
that the record to be updated is a record of the flash descriptor records in a serial peripheral interface (SPI) image and is based on a lookup table;
update the record in the SPI image based on data included in the lookup table.
In the same field of endeavor, Xie teaches programming of a serial peripheral image (SPI) image common to a group of platforms that includes the information handling system (Figure 5, items 502, paragraph 0076; i.e., a single SPI image can be distributed two multiple system platforms 502, which indicates that it is common to those platforms);
that the record to be updated is in a serial peripheral interface (SPI) image (Figure 1, “BIOS SPI Flash”, paragraphs 0030 and 0037; i.e., a BIOS firmware image stored in an SPI flash memory) and is based on a lookup table (paragraph 0039; i.e., the firmware update includes an updated profile configuration table 214 [Figure 2] [equivalent to the claimed “lookup table”]);
update the record in the SPI image based on data (Figure 2, items 234, paragraph 0047) included in the lookup table (paragraphs 0039, 0041, 0055, and 0061; i.e., an existing profile configuration table ["the record in the SPI image"] is updated based on data values 234 in a received updated profile configuration table 214).
Also in the same field of endeavor, Banik teaches an SPI image (Figure 1, item 114) includes flash descriptor records (Figure 3, item 302, paragraph 0043); and
the record to be updated is a record of the flash descriptor records in the SPI image (paragraphs 0063-0064; i.e., records in the flash descriptor region 302 within the SPI image are updated).
The motivation discussed above with regards to Claim 1 applies equally as well to Claim 9.
Regarding Claim 10, Xie teaches wherein the record is a chipset configuration setting (paragraph 0046).
Regarding Claim 11, Xie teaches wherein the record is stored in a region of an SPI flash memory device (paragraphs 0037 and 0056).
Regarding Claim 12, Xie teaches wherein the lookup table is stored in a platform data region of an SPI flash memory device (paragraph 0061; i.e., the entire updated profile configuration table [the claimed “lookup table”] can replace the existing profile configuration table that is stored in a platform data region [the primary flash memory region - see paragraph 0056] of the SPI flash memory device).
Regarding Claim 13, Xie teaches wherein the SPI image is common between at least two system platforms (Figure 5, items 502, paragraph 0076; i.e., a single SPI image can be distributed two multiple system platforms 502).
Regarding Claim 14, Xie teaches wherein the update of the record is performed by an embedded controller (paragraph 0036; i.e., a baseboard management controller [BMC] is known in the art to be a type of specialized embedded controller; see also instant specification at paragraph 0023 [“embedded controller … is similar to BMC”]).
Regarding Claim 15, Xie teaches wherein the lookup table is generated based on configuration settings of a base system platform (paragraph 0046; i.e., the updated profile configuration table contains values for hardware configuration settings such as chipset settings, hardware disk configurations, and external device configurations designed specifically for the receiving computer [the “base system platform”]).
Regarding Claim 16, Xie teaches wherein the SPI image is generated based on a base system platform (paragraph 0033; i.e., the BIOS firmware image located in the SPI flash memory contains values for hardware configuration settings such as chipset settings, hardware disk configurations, and external device configurations designed specifically for the computer on which it resides [the “base system platform”]).
Regarding Claim 17, Lin discloses a non-transitory computer-readable medium to store instructions that are executable to perform operations (paragraph 0004) comprising:
determining whether a current boot process (Figure 3, item 300) of an information handling system (Figure 1, item 100) is a first boot process of the information handling system subsequent to programming of an image (Figure 3, item 306, paragraph 0039; i.e., the BIOS 110, which is run by the CPU 104, determines whether the current boot process is the first boot process since a last BIOS update [the “image”]);
when the current boot process is the first boot process, determining whether a record in an image is to be updated (Figure 3, items 308 and 310, paragraphs 0039-0040; i.e., it is determined whether there are any modified BIOS settings in the future setting data structure; if so, then the corresponding records in the BIOS image that is stored in the flash chip [the claimed “image”] are updated accordingly); and
subsequent to the updating of the record, proceeding with executing the current boot process of the information handling system (Figure 3, item 316 or 318, paragraph 0041; i.e., after the BIOS settings are updated, the current boot process 300 can proceed to either reboot the computer [step 304] or allow it to boot into the OS [step 318]).
Lin does not expressly disclose programming of a serial peripheral image (SPI) image with flash descriptor records common to a group of platforms that includes the information handling system;
that the record to be updated is a record of the flash descriptor records in a serial peripheral interface (SPI) image and is based on a lookup table;
updating the record in the SPI image based on data included in the lookup table.
In the same field of endeavor, Xie teaches programming of a serial peripheral image (SPI) image common to a group of platforms that includes the information handling system (Figure 5, items 502, paragraph 0076; i.e., a single SPI image can be distributed two multiple system platforms 502, which indicates that it is common to those platforms);
that the record to be updated is in a serial peripheral interface (SPI) image (Figure 1, “BIOS SPI Flash”, paragraphs 0030 and 0037; i.e., a BIOS firmware image stored in an SPI flash memory) and is based on a lookup table (paragraph 0039; i.e., the firmware update includes an updated profile configuration table 214 [Figure 2] [equivalent to the claimed “lookup table”]);
updating the record in the SPI image based on data (Figure 2, items 234, paragraph 0047) included in the lookup table (paragraphs 0039, 0041, 0055, and 0061; i.e., an existing profile configuration table ["the record in the SPI image"] is updated based on data values 234 in a received updated profile configuration table 214).
Also in the same field of endeavor, Banik teaches an SPI image (Figure 1, item 114) includes flash descriptor records (Figure 3, item 302, paragraph 0043); and
the record to be updated is a record of the flash descriptor records in the SPI image (paragraphs 0063-0064; i.e., records in the flash descriptor region 302 within the SPI image are updated).
The motivation discussed above with regards to Claim 1 applies equally as well to Claim 17.
Regarding Claim 18, Xie teaches wherein the record is a chipset configuration setting (paragraph 0046).
Regarding Claim 19, Xie teaches wherein the record is stored in a region of an SPI flash memory device (paragraphs 0037 and 0056).
Regarding Claim 20, Xie teaches wherein the lookup table is stored in a platform data region of an SPI flash memory device (paragraph 0061; i.e., the entire updated profile configuration table [the claimed “lookup table”] can replace the existing profile configuration table that is stored in a platform data region [the primary flash memory region - see paragraph 0056] of the SPI flash memory device).
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAISAL M ZAMAN whose telephone number is (571)272-6495. The examiner can normally be reached Monday - Friday, 8 am - 5 pm, alternate Fridays.
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/FAISAL M ZAMAN/ Primary Examiner, Art Unit 2175
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