Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/24/2024 was filed before the mailing date of the Non-final rejection on 8/14/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-16 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Morimoto et al. (US 2018/0108800).
With respect to Claim 1, Morimoto teaches a semiconductor substrate 15 including a first surface and a pixel region in which a plurality of pixels each including an avalanche diode is arranged on the semiconductor substrate. The avalanche diode includes in cross sectional view a first semiconductor region 71 of a first conductivity type disposed at a first depth. A second semiconductor region 74 of a second conductivity type disposed at a second depth deeper than the first depth with respect to the first surface. An avalanche multiplication region being formed between the first semiconductor region and the second semiconductor region. A third semiconductor region 75 of the first conductivity type disposed at a third depth deeper than the second depth with respect to the first surface and in contact with the second semiconductor region 74. A first separation region 16 and a second separation region 16 each extending from the first depth to the third depth. The second semiconductor region 74 extends from the first separation region 16 to the second separation region 16. In the avalanche diode in planar view, an area of the first semiconductor region 71 is smaller than an area of the second semiconductor region 74. The first semiconductor region 71, the second semiconductor region 74, and the third semiconductor region 75 have portions that overlap one another (see paragraphs 31-49, 80-92, and 142-149; Figs. 1, 6, and 10).
With respect to Claim 2, Morimoto teaches each of the first separation region 16 and the second separation region is a semiconductor region of the
second conductivity type (see Figs. 1, 6, and 10).
With respect to Claim 3, Morimoto teaches the first separation region 16 and the second separation region 16 are connected to a contact plug applied with a
predetermined potential (see Figs. 1, 6, and 10).
With respect to Claim 4, Morimoto teaches a semiconductor region 6, 76 of the first conductivity type (i.e. N- type) that has an impurity concentration lower than an impurity concentration of the first semiconductor region 6 (i.e. N+ type) and is in contact with the first semiconductor region and the first separation region at the first depth (see Figs. 1, 6, and 10).
With respect to Claim 5, Morimoto teaches a semiconductor region 6, 76 of the first conductivity type (i.e. N- type) that has an impurity concentration lower than an impurity concentration (i.e. N+ type) of the first semiconductor region and is in contact with the first semiconductor region and the second separation region at the first depth (see Figs. 1, 6, and 10).
With respect to Claim 6, Morimoto teaches the avalanche diode includes a fourth semiconductor region 8 of the second type disposed at a fourth depth deeper than the third depth with respect to the first surface in cross sectional view (see Figs. 1, 6, and 10).
With respect to Claim 7, Morimoto teaches the fourth semiconductor region 8 is in contact with the first separation region and the second separation region an impurity concentration of the fourth semiconductor region is higher than an impurity
concentration of the second semiconductor region (see Figs. 1, 6, and 10).
With respect to Claim 8, Morimoto teaches an impurity concentration of the fourth semiconductor region 8 is higher than an impurity concentration of the second semiconductor region (see Figs. 1, 6, and 10).
With respect to Claim 9, Morimoto teaches an area of the third semiconductor region 75 is larger than the area of the first semiconductor region 71 in planar view (see Figs. 1, 6, and 10).
With respect to Claim 10, Morimoto teaches an area of the third semiconductor region 5 is larger than the area of the first semiconductor region 1 in planar view (see Figs. 1, 6, and 10).
With respect to Claims 11 and 12, Morimoto teaches the semiconductor substrate 15 includes a second surface opposing the first surface. The second surface is a light-incident surface (see paragraph 66; Figs. 1, 6, and 10).
With respect to Claim 13, Morimoto teaches a wavelength conversion unit 1201 configured to convert light in a first wavelength band into light in a second wavelength band different from the first wavelength band. A signal processing unit configured to synthesize a plurality of images obtained from a plurality of digital signals held in the light detection device. The light in the second wavelength band output from the wavelength converting unit is incident on the light detection device (see paragraphs 194-199).
With respect to Claims 14, Morimoto teaches a light emission unit configured to emit light detected by the light detection device; and a distance calculation unit 1309 configured to perform distance calculation using digital signals held in the light detection device (see paragraphs 204 and 208).
With respect to Claims 15, Morimoto teaches the light detection system comprising a signal processing unit 102 configured to process a signal from the light detection device (see paragraph 55; Fig. 4).
With respect to Claims 16, Morimoto teaches a distance information acquisition unit configured to acquire distance information relating to a distance to an object, using a signal from the light detection device; and a control unit configured to control the moving body based on the distance information (see paragraphs 211 and 212).
Allowable Subject Matter
8. Claims 7, 11, 14, 18, and 19 are objected to as being dependent upon a rejected
base claim, but would be allowable if rewritten in independent form including all of the
limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowance subject
matter: none of the prior art of record teaches or suggest the combination of
one third terminal element arranged at the center of symmetry. The one or more
dimensions and the one or more materials of the first electrical connection element are
identical to the one or more dimensions and the one or more materials of the second
electrical connection element. A length of the first segment of the third section
is identical to a length of the second segment of the third section in claim 7.
The prior art made of record and not relied upon is cited primarily to show the
product of the instant invention.
Conclusion
10. Any inquiry concerning the communication or earlier communications from the
examiner should be directed to Alonzo Chambliss whose telephone number is (571)
272-1927.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's
supervisor, Jacob Y. Choi can be reached on (469) 295-9060. The fax phone number
for the organization where this application or proceeding is assigned is (571) 273-8300.
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AC/August 14, 2026 /Alonzo Chambliss/
Primary Examiner, Art Unit 2897
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