DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi (U.S. Publication No. 2020/0381399 A1) in view of Siang et al. (U.S. Publication No. 2012/0228783 A1; Siang).
With respect to claim 1, Choi discloses an apparatus, comprising: a memory cell die [300]; a plurality of signal pads [2500S] under the memory cell die (see Figure 2 and 10; each die has multiple pads, based on orientation, signal pads [2500S] of one die are under the die of the upper die; furthermore based on orientation of the entire structure being inverted, all pads can be considered under their respective dies), wherein each bonding wire coupled to a respective one of the plurality of signal pads has a first wire size diameter (See Figure 10); and a plurality of power pads [2500P] under the memory cell die, wherein each bonding wire coupled to a respective one of the plurality of power pads has a second wire size diameter Choi fails to disclose a second wire size diameter larger than the first wire size diameter.
In the same field of endeavor, Siang teaches a second wire [208A] size diameter larger than the first wire [208B] size diameter (See Figure 2B and ¶[0020]). Implementation of multiple diameters of wire within a single package structure as taught by Siang allows for improved differential impedance requirements and efficient power delivery circuits (see Siang ¶[0020]- ¶[0026]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 2, the combination of Choi and Siang discloses wherein at least a portion of the plurality of signal pads and the plurality of power pads are arranged in an alternating pattern (see Choi Figure 10; alternating pattern of power, signal, signal, ground, signal, signal, power and Siang ¶[0020-0022]).
With respect to claim 3, the combination of Choi and Siang discloses wherein the first wire size diameter is approximately 0.7 millimeters (see Siang ¶[0020]).
With respect to claim 4, the combination of Choi and Siang discloses wherein the second wire size diameter is approximately 1.0 millimeters (see Siang ¶[0020]).
With respect to claim 5, the combination of Choi and Siang discloses wherein the memory cell die is a non-volatile memory cell die (see Choi ¶[0084])
With respect to claim 6, the combination of Choi and Siang discloses wherein the memory cell die is a volatile memory cell die (see Choi ¶[0084])
With respect to claim 7, the combination of Choi and Siang discloses a different memory cell die stacked on the memory cell die and comprising: a different plurality of signal pads under the different memory cell die, wherein each bonding wire coupled to a respective one of the different plurality of signal pads has the first wire size diameter; and a different plurality of power pads under the different memory cell die, wherein each bonding wire coupled to a respective one of the different plurality of power pads has the second wire size diameter (See Choi Figure 10 and Siang Figure 2B).
With respect to claim 8, the combination of Choi and Siang discloses wherein a distance between a power pad of the plurality of power pads and an adjacent signal pad of the plurality of signal pads is below a distance threshold (See Choi Figure 10)
With respect to claim 9, the combination of Choi and Siang discloses wherein the distance threshold comprises a size of the smaller of the power pad or the signal pad (see Choi Figure 10 and Siang Figure 2B).
With respect to claim 10, Choi discloses an apparatus, comprising: a stack of memory cell dies [2300S], wherein each memory cell die in the stack comprises: a plurality of alternating signal pads [2500S] and power pads [2500P] under the memory cell die, wherein each bonding wire coupled to a respective one of the plurality of signal pads has a first wire size diameter; and wherein each bonding wire coupled to a respective one of the plurality of power pads has a second wire size diameter (See Figure 10). Choi fails to disclose a second wire size diameter larger than the first wire size diameter.
In the same field of endeavor, Siang teaches a second wire [208A] size diameter larger than the first wire [208B] size diameter (See Figure 2B and ¶[0020]).
Implementation of multiple diameters of wire within a single package structure as taught by Siang allows for improved differential impedance requirements and efficient power delivery circuits (see Siang ¶[0020]- ¶[0026]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 11, the combination of Choi and Siang discloses wherein the stack of memory cell dies comprises a stack of non-volatile memory cell dies (see Choi ¶[0084])
With respect to claim 12, the combination of Choi and Siang discloses wherein the stack of memory cell dies comprises a stack of volatile memory cell dies (see Choi ¶[0084])
With respect to claim 13, the combination of Choi and Siang discloses wherein the stack of memory cell dies comprises a stack of sixteen memory cell dies (See Choi ¶[0030]).
With respect to claim 14, the combination of Choi and Siang discloses wherein each bonding wire coupled to a respective one of the plurality of signal pads is separated from an adjacent bonding wire coupled to a respective one of the plurality of signal pads by a distance that reduces a wire bond shorting risk below a particular threshold risk (see Figure 10).
With respect to claim 15, the combination of Choi and Siang discloses wherein the first wire size diameter is approximately 0.7 millimeters, and wherein the second wire size diameter is approximately 1.0 millimeters (see Siang ¶[0020]).
With respect to claim 16, Choi discloses a system, comprising: a memory cell die [2300]; a first section comprising a first plurality of power pads [2500S] under a first section of the memory cell die (see Figure 2 and 10; each die has multiple pads, based on orientation, signal pads [2500S] of one die are under the die of the upper die; furthermore based on orientation of the entire structure being inverted, all pads can be considered under their respective dies); a second section comprising a second plurality of power pads [2500P] under a second section of the memory cell die, wherein each bonding wire coupled to a respective one of the first plurality of power pads and each bonding wire coupled to a respective one of the second plurality of power pads has a first wire size diameter; and a third section comprising a plurality of signal pads under a third section of the memory cell die and between the first plurality of power pads and the second plurality of power pads (See Figure 10), Choi fails to disclose wherein each bonding wire coupled to a respective one of the plurality of signal pads has a second wire size diameter smaller than the first wire size diameter.
In the same field of endeavor, Siang teaches each bonding wire coupled to a respective one of the plurality of signal pads has a second wire [208A] size diameter smaller than the first wire [208B] size diameter. (See Figure 2B and ¶[0020]).
Implementation of multiple diameters of wire within a single package structure as taught by Siang allows for improved differential impedance requirements and efficient power delivery circuits (see Siang ¶[0020]- ¶[0026]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 17, the combination of Choi and Siang discloses an individual power pad located within the third section and between two of the plurality of signal pads (see Choi Figure 10).
With respect to claim 18, the combination of Choi and Siang discloses wherein a bonding wire coupled to the individual power pad comprises the first wire size diameter (see Figure 10 and Siang Figure 2B). With respect to claim 19, the combination of Choi and Siang discloses wherein the first section of the memory cell die is located below a first outer edge of the memory cell die, and the second section of the memory cell die is located below a second outer edge of the memory cell die opposite the first outer edge of the memory cell die (see Choi Figure 10).
With respect to claim 20, the combination of Choi and Siang discloses wherein the third section of the memory cell die is located below an approximate center of the memory cell die (see Choi Figure 10).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kuroda et al. (U.S. Publication No. 2010/0320623 A1) discloses a mixed wiring package structure
Nickerson et al. (U.S. Publication No. 2006/0000876 A1) discloses a mixed wiring package structure
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/JONATHAN HAN/Primary Examiner, Art Unit 2818
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