Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 3 – 7, 14, 16 - 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki (US 20110188215), in view of Park (US 20100207855).
Regarding claim 1, Suzuki discloses an electronic device comprising:
a printed circuit board (the circuit substrate 13, Fig. 8); and
wherein the printed circuit board comprises: a conductive layer (the ground layer 25 or 51) comprising at least one slit (the recess on layer 51 similar to the recess 30a in Fig. 5) in an area adjacent to the component (14); and
an insulation layer (the insulation 52) directly on the conductive layer (51) and comprising a portion in the at least one slit (30a), wherein the at least one slit is parallel to at least one side surface (the side surface of the component 14) of the component (14), and is spaced apart from the at least one side surface of the capacitor by a first distance or less, and wherein the at least one slit does not overlap the capacitor when viewed from above (Fig. 8).
Suzuki does not explicitly disclose a capacitor on the printed circuit board.
Park suggests one of the components mounted on the pads (41, Fig. 10) of the circuit board is a capacitor (the capacitor 30 with the dielectric substance 31).
It would have been obvious to one having skill in the art at the effective filing date of the invention to include capacitor into a circuit board in order to complete an intended circuitry.
Regarding claim 3, Suzuki, in view of Park, discloses the claimed invention as set forth in claim 1.
Suzuki does not explicitly disclose the capacitor is a multilayer ceramic capacitor (MLCC).
Park suggests the capacitor having multilayer of ceramic (paragraph 61).
It would have been obvious to one having skill in the art at the effective filing date of the invention to use multiplayers ceramic capacitor in order to complete a circuitry of the electronic device.
Regarding claim 4, Suzuki, in view of Park, discloses the claimed invention as set forth in claim 1.
Suzuki does not explicitly disclose the at least one side surface of the capacitor comprises: a first side surface facing a first direction, a second side surface facing a second direction opposite to the first direction, a third side surface facing a third direction perpendicular to the first direction and the second direction, and a fourth side surface facing a fourth direction opposite to the third direction.
Park suggests the capacitor (30, Fig. 4) having sides facing four directions.
It would have been obvious to one having skill in the art at the effective filing date of the invention to rearrange the components on the circuit board in order to fit all components on the limited space of the circuit substrate.
Regarding claim 5, Suzuki, in view of Park, discloses the claimed invention as set forth in claim 4. Park further suggests at least one solder pad (solder pads 41 & 43, paragraph 63) between the capacitor and the printed circuit board, wherein the at least one solder pad comprises a first solder pad (the solder pad 41) coupled to a first direction side (left side) of a lower surface of the capacitor and a second solder pad (the solder pad 42) coupled to a second direction side (right side) of the lower surface of the capacitor.
Regarding claim 6, Suzuki, in view of Park, discloses the claimed invention as set forth in claim 1. Suzuki further suggests the at least one slit (the slit 30a) is recessed downward (Fig. 5) from one surface of the conductive layer contacting the insulation layer.
Regarding claim 7, Suzuki, in view of Park, discloses the claimed invention as set forth in claim 1. Suzuki further suggests a thickness of the at least one slit (30a) is less than or equal to a thickness of the conductive layer (31 & 25, Fig. 5).
Regarding claim 14, Suzuki discloses the claimed invention as set forth in claim 3. Suzuki further suggests the portion protrudes downward and fills the at least one slit (the insulator 26 protrudes downward into the slit 30a, Fig. 5).
Regarding claim 16, Suzuki discloses an electronic device comprising:
a printed circuit board (the circuit board 13, Fig. 8); and
wherein the printed circuit board comprises:
a first conductive layer (51) comprising a first slit layer (the slit on layer 51 adjacent to the component 14) in an area adjacent to the component;
a first insulation layer (52) on the first conductive layer and comprising a first portion in the first slit layer;
a second conductive layer (45) on the first insulation layer and comprising a second slit layer (the slit on layer 45 adjacent to the component 14) in the area adjacent to the component; and
a second insulation layer (46) on the second conductive layer and comprising a second portion in the second slit layer, and wherein a slit (the slit similar to 30a of Fig. 5) in the first slit layer and the second slit layer is adjacent to at least one side surface of the capacitor and spaced apart from the at least one side surface of the capacitor by a first distance or less.
Suzuki does not explicitly disclose a capacitor on the printed circuit board.
Park suggests one of the components mounted on the pads (41, Fig. 10) of the circuit board is a capacitor (the capacitor 30 with the dielectric substance 31).
It would have been obvious to one having skill in the art at the effective filing date of the invention to include capacitor into a circuit board in order to complete an intended circuitry.
Regarding claim 17, Suzuki, in view of Park, discloses the claimed invention as set forth in claim 16.
Suzuki does not explicitly disclose the capacitor is a multilayer ceramic capacitor (MLCC).
Park suggests the capacitor having multilayer of ceramic (paragraph 61).
It would have been obvious to one having skill in the art at the effective filing date of the invention to use multiplayers ceramic capacitor in order to complete a circuitry of the electronic device.
Regarding claim 18, Suzuki, in view of Park, discloses the claimed invention as set forth in claim 16. Suzuki further suggests the slit comprises at least one slit in the first slit layer and a slit in the second slit layer (the slits in both layers 45 and 51).
Claim(s) 2, 8, 9, 10, 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki (US 20110188215), in view of Park (US 20100207855), in further view of Li (US 20240251503).
Regarding claim 2, Park discloses the claimed invention as set forth in claim 1.
Park does not explicitly disclose the at least one slit comprises one side having a second length extending parallel to the at least one side surface of the capacitor, and wherein the second length is at least 1.4 times longer than a length of the at least one side surface of the capacitor.
Li suggests the at least one slit (C1 & C2; Fig. 1) comprises one side having a second length extending parallel to the at least one side surface of the capacitor (the capacitor to mounted on the pads 23; Fig. 4), and wherein the second length is at least 1.4 times longer than a length of the at least one side surface of the capacitor (the length of C1 is at least 1.4 times longer than the length of the capacitor).
It would have been obvious to one having skill in the art at the effective filing date of the invention to adjust the size of the components and other features such as the slits in order to fit all components into the limited space of the circuit substrate.
Regarding claim 8, Suzuki, in view of Park, discloses the claimed invention as set forth in claim 1.
Suzuki does not explicitly disclose the at least one slit comprises: a first slit parallel to the first side of the capacitor, and a third slit perpendicular to the first slit and parallel to the third side surface of the capacitor.
Li suggests the at least one slit comprises: a first slit (C1) parallel to the first side of the capacitor, and a third slit (C2) perpendicular to the first slit and parallel to the third side surface of the capacitor.
It would have been obvious to one having skill in the art at the effective filing date of the invention to rearrange the position of the components on the circuit board in order to fit all the components into the limited space of the circuit substrate.
Regarding claim 9, Suzuki, in view of Park, discloses the claimed invention as set forth in claim 1.
Suzuki does not explicitly disclose the at least one slit comprises: a first side of a second length parallel to an adjacent side of the at least one side surface of the capacitor, and a second side of a third length extending perpendicular to the first side, and wherein the second length is at least twice a length of an adjacent side of the at least one side surface of the capacitor.
Li suggests the at least one slit (C1 and C2) comprises: a first side of a second length parallel to an adjacent side of the at least one side surface of the capacitor (C1 is parallel to the first side of the capacitor), and a second side of a third length extending perpendicular to the first side (C2 is perpendicular to C1), and wherein the second length is at least twice a length of an adjacent side of the at least one side surface of the capacitor (the length of C2 is at least twice the length of C1).
It would have been obvious to one having skill in the art at the effective filing date of the invention to adjust the size and rearrange the components on the circuit board in order to fit all of the intended components into the limited space of the circuit substrate.
Regarding claim 10, Suzuki, in view of Park, discloses the claimed invention as set forth in claim 1.
Suzuki does not explicitly disclose the at least one slit comprises: a first slit adjacent to the first side surface and extending in the third direction, and a second slit adjacent to the second side surface and extending in the third direction.
Li suggests the at least one slit comprises: a first slit (C2 is adjacent to one side of the capacitor) adjacent to the first side surface and extending in the third direction, and a second slit (another C2 parallel to the first C2 is adjacent to another side of the capacitor and extending to the same direction as the other C2) adjacent to the second side surface and extending in the third direction.
It would have been obvious to one having skill in the art at the effective filing date of the invention to rearrange the components on the circuit board in order to fit all of the intended components into the limited space of the circuit substrate.
Regarding claim 15, Suzuki discloses the claimed invention as set forth in claim 4.
Suzuki does not explicitly disclose the at least one slit comprises: a first portion at the third side of the capacitor and parallel to the third side, a second portion at the fourth side of the capacitor and parallel to the fourth side, and a third portion connected to the first portion and the second portion and facing a lower surface of the capacitor.
Li teaches the at least one slit comprises: a first portion (C2) at the third side of the capacitor and parallel to the third side, a second portion (another C2 parallel to the C2) at the fourth side of the capacitor and parallel to the fourth side, and a third portion (C1 connects two C2 together) connected to the first portion and the second portion and facing a lower surface of the capacitor.
It would have been obvious to one having skill in the art at the effective filing date of the invention to rearrange the components on the circuit board in order to fit all the intended components into the limited space of the circuit substrate.
Allowable Subject Matter
Claims 11 – 13, 19, 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reasons for Allowance
The following is an examiner’s statement of reasons for allowance:
Regarding claim 11, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in claims 1 and 10, a combination of limitations that the at least one slit further comprises: a third slit adjacent to the third side surface, and extending in the first direction, and a fourth slit adjacent to the fourth side surface, and extending in the first direction. None of the reference art of record discloses or renders obvious such a combination.
Regarding claim 13, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in claim 1, a combination of limitations that the first distance is 0.2 mm or less. None of the reference art of record discloses or renders obvious such a combination.
Regarding claim 19, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in claim 16, a combination of limitations that the slit comprises a slit in the first slit layer and a slit in the second slit layer having a shape different than the slit in the first slit layer. None of the reference art of record discloses or renders obvious such a combination.
Regarding claim 20, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in claim 16, a combination of limitations that the first slit layer and the second slit layer include at least one of: a first slit at a first side surface of the capacitor and adjacent to the first side surface, a second slit at a the second side surface of the capacitor and adjacent to the second side surface, a third slit at a third side surface of the capacitor and adjacent to the third side surface, a fourth slit at a fourth side surface of the capacitor and adjacent to the fourth side surface, and a fifth slit facing a lower surface of the capacitor. None of the reference art of record discloses or renders obvious such a combination.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lee (US 20190372202) discloses a circuit board having a component and a slit, Fig. 1.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BINH B TRAN whose telephone number is (571)272-9289. The examiner can normally be reached M-F 8:00 AM - 6:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy J Dole can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BINH B TRAN/Primary Examiner, Art Unit 2847
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