DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: GaN power transistor with an active clamp circuit.
Claim Objections
Claims 3-15 is/are objected to because of the following informalities:
Claim 3 recites “the clamp transistor includes a drain electrode, a source electrode, and a gate electrode” in Lines L2-3 but should read –the clamp transistor includes a second drain electrode, a second source electrode, and a second gate electrode--.
Claim 5 recites “including a gate electrode” in Line L3 but should read –including a third gate electrode--.
Claim 6 recites “the GaN transistor and the clamp transistor each include” in Lines L2-3 but should read – the GaN transistor and the clamp transistor each includes--.
The balance of claims is objected to for being dependent upon an already objected claim.
Appropriate correction is required. The applicant is kindly requested to check the other claims for inconsistency in claim language.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2 and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Otake (US20200365495A1 from IDS-Otake95).
Regarding claim 1, Otake95 discloses a semiconductor device (Semiconductor device 7-Examiner's annotated Fig 7), comprising:
a semiconductor substrate (Substrate 701-Examiner's annotated Fig 7);
a GaN transistor formed on the semiconductor substrate (GaN-Transistor 791 formed on substrate 701-[0056] L1-7, Examiner's annotated Fig 7) and including
a drain electrode (Source electrode 72-Examiner's annotated Fig 7),
a source electrode (Source electrode 71-Examiner's annotated Fig 7), and
a gate electrode (Gate electrode 73-Examiner's annotated Fig 7);
an active clamp circuit formed on the semiconductor substrate (Active clamp circuit 792 formed on substrate 701-Examiner's annotated Fig 7) and
electrically connected to the GaN transistor (Active clamp circuit 792 formed on substrate 701 and electrically connected to GaN-transistor 791 with the connection between source electrode 75 and gate electrode 73-Examiner's annotated Fig 7),
the active clamp circuit including a clamp transistor configured to be activated based on a rise of drain-source voltage of the GaN transistor (Clamp transistor 792 in the dashed line area configured to be activated based on fluctuation so rise of the drain-source-voltage of GaN transistor 791-[0054] L1-16, Examiner's annotated Fig 9);
a drain pad electrically connected to the drain electrode of the GaN transistor (Drain Pad 709c connected to drain electrode 72-Examiner's annotated Fig 7);
a source pad electrically connected to the source electrode of the GaN transistor (Source Pad 709e electrically connected to source electrode 71-Examiner's annotated Fig 7); and
a gate pad electrically connected to the gate electrode of the GaN transistor (Gate Pad 709a electrically connected to gate electrode 73-Examiner's annotated Fig 7).
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Regarding claim 2, Otake95 discloses all the elements of claim1, as noted above.
Otake further discloses a semiconductor device
wherein the GaN transistor includes a main drift layer (GaN-Transistor 791 including Main drift layer 703-[0058] L10-14, Examiner's annotated Fig 7),
the clamp transistor includes a sub drift layer (Active clamp circuit 792 including Sub-drift layer 703-[0058] L10-14, Examiner's annotated Fig 7), and
the sub drift layer and the main drift layer are composed of a same material (Layer 703 as a GaN layer separated by 707 so composed of the same material[0058] L10-14-Examiner's annotated Fig 7).
Regarding claim 16, Otake95 discloses all the elements of claim1, as noted above.
Otake further discloses a semiconductor module, comprising:
an encapsulation resin encapsulating the semiconductor device (Encapsulation resin 8 encapsulating semiconductor device 7, covering portions of leads 1-6 so exposing terminals 1-6 so exposing drain terminal, source terminal, and gate terminal-Fig 1, [0068] L1-3);
a drain terminal exposed from the encapsulation resin and electrically connected to the drain pad (Drain terminal/second lead 2 electrically connected to drain electrode 72, electrically connected to drain pad 709c-[0061] L12-13, Fig 2, Examiner's annotated Fig 7);
a source terminal exposed from the encapsulation resin and electrically connected to the source pad (source terminal/first lead 1 electrically connecting to electrode 71 connected to source pad 709e-[0055] L7-10-Examiner's annotated Fig 7); and
a gate terminal exposed from the encapsulation resin and electrically connected to the gate pad (Gate terminal/third lead 3 electrically connected to gate electrode 73, electrically connected to gate pad 709a-[0061] L15-16, Fig 2, Examiner's annotated Fig 7).
Allowable Subject Matter
Claims 3-15 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3, the prior art of record does not teach or suggest a semiconductor device, namely “a clamp capacitor connected between the drain electrode of the GaN transistor and the gate electrode of the clamp transistor”, along with other recited claim limitations.
References such as Otake (US20200365495A1 from IDS-Otake95) and Uemura et al. (US20220158448A1-Uemura48) combination, teaches a semiconductor device, but does not teach or suggest a semiconductor device, namely “a clamp capacitor connected between the drain electrode of the GaN transistor and the gate electrode of the clamp transistor”, in combination with other claimed elements.
Regarding claim 3, Otake95 discloses all the elements of claim1, as noted above.
Otake95 further discloses a semiconductor device
wherein the clamp transistor (792-Fig 7) includes
a drain electrode (drain electrode 75-Fig 7),
a source electrode (Source electrode 74-Fig 7), and
a gate electrode (Gate electrode-Fig 7),
the source electrode of the clamp transistor is electrically connected to the source electrode of the GaN transistor (source electrode 74 of the clamp transistor 792 electrically connected to source electrode 71-Fig 16),
the drain electrode of the clamp transistor is electrically connected to the gate electrode of the GaN transistor (drain electrode 75 of clamp transistor792 electrically connected to gate electrode 73 of GaN transistor 791-Fig 7).
Otake95 does not disclose a semiconductor device wherein
the active clamp circuit includes
a pull-down resistor connected between the source electrode and the gate electrode of the clamp transistor, and
a clamp capacitor connected between the drain electrode of the GaN transistor and the gate electrode of the clamp transistor.
Uemura48 teaches a semiconductor device wherein
the active clamp circuit (60-Fig 7) includes
a pull-down resistor connected between the source electrode and the gate electrode of the clamp transistor (pull-down resistor 22 connected between the source electrode and the gate electrode of the clamp transistor 50), and
a clamp capacitor connected to the gate electrode of the clamp transistor(clamp capacitor 40 connected to the gate electrode of the clamp transistor 50-Fig 7).
Uemura48 does not teach a semiconductor device wherein
a clamp capacitor connected between the drain electrode of the GaN transistor and the gate electrode of the clamp transistor.
The balance of the claims are allowable for at least the above-stated reasons.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHALIE R FAYETTE whose telephone number is (571)272-1220. The examiner can normally be reached Monday-Friday 8:30 am-6pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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NATHALIE R. FAYETTE
Examiner
Art Unit 2812
/NATHALIE R FAYETTE/Examiner, Art Unit 2812 09/10/2026
/FAZLI ERDEM/Primary Examiner, Art Unit 2812 9/14/2026
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