DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 and 15-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Otake et al. (Otake, US 2016/0308523 A1).
Regarding claim 1, Otake shows a semiconductor module ( power circuit 1 in FIG. 1), comprising: a first chip ( MISFET Q1 in FIG. 1 and [0190]) including a main transistor ( Q1 in FIG. 1) including a main drift layer ( drift layer 26 see FIG. 2 with respect to FIG. 1); a second chip (Q 4 in FIG. 1) including at least part of an active clamp circuit ( circuit connected to Q4 and [0183]) including a sub transistor (Q4 in FIG. 1) configured to be activated based on a rise of drain-source voltage of the main transistor (Q4); a connection member ( G4/Dg4 in FIG. 1) electrically connecting the main transistor and the active clamp circuit (see FIG. 1); an encapsulation resin (resin layer 120 as shown in FIG. 16) encapsulating the first chip (Q1), the second chip (Q4), and the connection member, wherein the sub transistor includes a sub drift layer composed of a material that differs ( 28-P /26-n- in FIG. 4A) from a material composing the main drift layer ( [0015]).
Regarding claim 2, Otake shows a semiconductor module ( power circuit 1 in FIG. 1), comprising, wherein the main transistor is a GaN transistor in which the main drift layer is composed of GaN ([0082]), and the sub transistor is a Si transistor in which the sub drift layer is composed of Si ([0087]).
Regarding claim 3, Otake shows a semiconductor module ( power circuit 1 in FIG. 1), comprising, wherein the main transistor (Q1 in FIG. 1) includes a drain electrode (D1 in FIG. 1), a source electrode (S1), and a gate electrode (G1), the semiconductor module further comprising: a drain terminal (P in FIG. 1) electrically connected to the drain electrode; a source terminal (O in FIG. 1) electrically connected to the source electrode (S1); and a gate terminal electrically connected to the gate electrode (G1).
Regarding claim 15, Otake shows a semiconductor module ( power circuit 1 in FIG. 1), comprising, wherein the first chip (Q1 in FIG. 1) includes first chips arranged separately from each other, and as viewed in a thickness-wise direction of the encapsulation resin, the second chip (Q4) is separated from the first chips in a direction orthogonal to an arrangement direction of the first chips (see FIG. 1 with respect to FIG. 2).
Regarding claim 16, Otake shows a semiconductor module ( power circuit 1 in FIG. 1), comprising, wherein the second chip includes second chips (Q4) arranged separately from each other in the arrangement direction of the first chips (Q1).
Regarding claim 17, Otake shows a semiconductor module ( power circuit 1 in FIG. 1), comprising, wherein a third chip (Q2/Q5 as shown in FIG. 9) arranged in the encapsulation resin separately from the first chip and the second chip and including a driver circuit (50 in 9) configured to drive the main transistor; and a control connection member electrically connecting the third chip to the first chip and the second chip (Q1/Q4).
Regarding claim 18, Otake shows a semiconductor module ( power circuit 1 in FIG. 1), comprising, wherein the main transistor and the sub transistor each include a drain electrode (D1/D4), a source electrode (S1/S4) and a gate electrode (G1/G4), and the control connection member connects the driver circuit, the drain electrode of the sub transistor, and the gate electrode of the main transistor (see FIG. 1).
Allowable Subject Matter
Claims 4-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS M ULLAH whose telephone number is (571)272-1415. The examiner can normally be reached M-F at 8AM-5PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at 571-270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ELIAS ULLAH/ Primary Examiner, Art Unit 2893
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