DETAILED ACTION
This Office Action is responsive to the Applicant’s communication filed 24 July 2024. In view of this communication, claims 1-20 are pending in the application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 11 recites the limitation "the first via electrode" in line 5 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 13 recites the limitation "the semiconductor device" in lines 1 and 3 of the claim. There is insufficient antecedent basis for this limitation in the claim. Claim 13 depends on claims 1, 2, and 11, none of which recite a semiconductor device. For the purposes of the rejection, claim 13 will be taken to depend on claim 7.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-6, 9-12, and 16 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Jeon et al. (US 20220141953 A1), hereinafter referred to as Jeon et al.
Regarding claim 1, Jeon et al. teaches a circuit board comprising:
a first insulating layer (117) (Fig. 4C, paragraph 38: insulating layer 117);
a second insulating layer (115) disposed on the first insulating layer (117) (Fig. 4C, paragraph 38: insulating layer 115 stacked on insulating layer 117);
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a protective layer (160) disposed under the first insulating layer (117) (Fig. 4C, paragraph 38: passivation layer 160 on the outermost surface of the circuit board); and
a cavity (C) provided in the first insulating layer (117), the second insulating layer (115), and the protective layer (160) (Fig. 4C and paragraph 38: cavity C penetrates the passivation layer 160 and the insulating layers 115, 117); and
wherein the cavity (C) penetrates from a lower surface of the protective layer (160) to a partial region of the second insulating layer (115) (Fig. 4C and paragraph 38: insulating layer 115 serves as the lower boundary of the cavity C).
Regarding claim 2, Jeon et al. teaches the circuit board of claim 1, wherein the cavity (C) includes:
a first side wall (portion of cavity C through protective layer 160) provided in the protective layer (160) and having a first slope angle,
a second side wall (portion of cavity C through first insulating layer 117) provided in the first insulating layer (117) and having a second slope angle, and
a third side wall (portion of cavity C through second insulating layer 115) provided in the second insulating layer (115) and having a third slope angle,
wherein the second slope angle is different from the first slope angle or the third slope angle (Fig. 4C: the slope of the walls of the cavity C in layer 117 is different from the angle of the walls of the cavity C in layer 115).
Regarding claim 3, Jeon et al. teaches the circuit board of claim 2, wherein the protective layer (160) includes a first through hole (C) to form the first side wall (portion of cavity C through protective layer 160),
wherein the first insulating layer (117) includes a second through hole (C) to form the second side wall (portion of cavity C through first insulating layer 117), and
wherein the second insulating layer (115) includes a recess portion to form the third side wall (see Fig. 3 and paragraph 41: the cavity C extends partially into the insulating layer 115).
Regarding claim 4, Jeon et al. teaches the circuit board of claim 2, wherein the second slope angle with respect to an upper surface of the cavity (C) is greater the first slope angle or the third slope angle with respect to the upper surface of the cavity (C) (the angle of the wall of cavity C through layer 117, which is the second slope angle, is greater than the angle of the wall of cavity C through protective layer 160, which is perpendicular to the surface of the board).
Regarding claim 5, Jeon et al. teaches the circuit board of claim 2, wherein the second slope angle is greater than 90 degrees with respect to an upper surface of the cavity (C) (see Fig. 3: the slope angle of the wall of cavity C through layer 117 is greater than 90 degrees), and
wherein the first slope angle or the third slope angle is 90 degrees or less with respect to the upper surface of the cavity (C) (the first slope angle of the wall of cavity C through protective layer 160 is 90).
Regarding claim 6, Jeon et al. teaches the circuit board of claim 2, comprising:
a first via electrode (137) including a portion disposed in the first insulating layer (117) (paragraph 52: wiring via 137 embedded in insulating layer 117);
a second via electrode (135) disposed in the second insulating layer (115) (paragraph 52: wiring via 135 embedded in insulating layer 115); and
an intermediate circuit layer (126) disposed between the portion of the first via electrode (137) and the second via electrode (135) (paragraphs 50 and 52: wiring layer 126 is electrically connected to vias 135 and 137); and
wherein the second via electrode (135) overlaps the portion of the first via electrode (137) and the intermediate circuit layer (126) in a vertical direction (see Fig. 4C).
Regarding claim 9, Jeon et al. teaches the circuit board of claim 2, wherein the second side wall (portion of cavity C through first insulating layer 117) and the third side wall (portion of cavity C through second insulating layer (115)) directly contact each other (see Fig. 3: layers 115 and 117 are formed directly in contact with one another).
Regarding claim 10, Jeon et al. teaches the circuit board of claim 2, wherein the first side wall (portion of cavity C through protective layer 160) and the second side wall (portion of cavity C through first insulating layer 117) directly contact each other (see Fig. 3: layers 160 and 117 are formed directly in contact with one another).
Regarding claim 11, Jeon et al. teaches the circuit board of claim 2, comprising:
a third insulating layer (113) disposed on the second insulating layer (115) (paragraph 38 and 47: insulating layer 113 disposed on insulating layer 115),
wherein the second side wall (portion of cavity C through first insulating layer 117) and the third side wall (portion of cavity C through second insulating layer 115) directly contact each other at a contact portion (see Figs. 3 and 4C), and
wherein the contact portion is higher than the portion of the first via electrode (137) with respect to an upper surface of the third insulating layer (113) (Figs 3 and 4C: via 137 does not extend all the way to layer 115).
Regarding claim 12, Jeon et al. teaches the printed circuit board of claim 2, wherein a width of the second through hole (C) of the cavity (C) is largest at a lower portion of the second through hole positioned in a same plane as a lower surface of the first insulating layer (117) (Figs. 3 and 4C: with the walls of cavity C in layer 160 being perpendicular to the surface of the board, the cavity C is at its widest at the point of layer 117 that is farthest from the center of the board), and
wherein the width of the second through hole (C) of the cavity (C) at the lower portion of the second through hole is greater than a width of a recess portion of the cavity (C) at a lower portion of the recess portion (see Figs. 3 and 4C: the width of cavity C declines closer to the bottom of the cavity, such that the walls are narrowest in layer 115).
Regarding claim 16, Jeon et al. teaches the circuit board of claim 7, wherein the cavity (C) overlaps the intermediate circuit layer (126) in the horizontal direction (see Fig. 3).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 7-8, 13, and 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. in view of Kim et al (US 20220322528 A1), hereinafter referred to as Kim et al.
Regarding claim 7, Jeon et al. teaches the circuit board of claim 6, but does not teach a semiconductor device disposed in the cavity (C), and wherein the semiconductor device overlaps the portion of the first via electrode (137), the second side wall (portion of cavity C through first insulating layer 117) of the cavity (C), and the third side wall (portion of cavity C through second insulating layer 115) in a horizontal direction perpendicular to the vertical direction.
Kim et al. does teach a semiconductor device (EC) disposed in the cavity (CA), and wherein the semiconductor device (EC) overlaps the portion of the first via electrode (TV), the second side wall (portion of cavity CA through first insulating layer 300) of the cavity (CA), and the third side wall (portion of cavity CA through second insulating layer 200) in a horizontal direction perpendicular to the vertical direction (see Kim et al. Fig. 6 and paragraph 83: component EC disposed in cavity CA).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to place a semiconductor device as taught by Kim et al. overlapping the first via electrode, the second side wall, and the third side wall of Jeon et al. in a horizontal direction because the semiconductor device of Kim et al. increases the functionality of the board (Kim et al. paragraphs 82-5) and the size of the component is a simple matter of design choice. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Regarding claim 8, Jeon et al. in view of Kim et al. teaches the circuit board of claim 7, but does not teach that the semiconductor device overlaps the first side wall (portion of cavity C through protective layer 160) of the cavity (C) in the horizontal direction.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a semiconductor device that overlaps the first sidewall of Jeon et al. because the size of the component is a simple matter of design choice and a change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Regarding claim 13, Jeon et al. in view of Kim et al. teaches the circuit board of claim 11, wherein the semiconductor device includes an upper surface and a lower surface, and wherein the lower surface of the semiconductor device is lower than a lower surface of the first insulating layer (117) with respect to a lower surface of the third insulating layer (113) (Kim et al. Fig. 6 and paragraph 83: electronic component EC disposed in cavity CA with a surface that extends past Kim’s equivalent first insulating layer 300).
Regarding claim 17, Jeon et al. teaches a semiconductor package substrate comprising:
a first insulating layer (117) (Fig. 4C, paragraph 38: insulating layer 117);
a second insulating layer (115) disposed on the first insulating layer (117) (Fig. 4C, paragraph 38: insulating layer 115 stacked on insulating layer 117);
a protective layer (160) disposed under the first insulating layer (117) (Fig. 4C, paragraph 38: passivation layer 160 on the outermost surface of the circuit board);
a cavity (C) provided in the first insulating layer (117), the second insulating layer (115), and the protective layer (160) (Fig. 4C and paragraph 38: cavity C penetrates the passivation layer 160 and the insulating layers 115, 117); and
wherein the cavity (C) includes:
a first side wall (portion of cavity C through protective layer 160) provided in the protective layer (160) and having a first slope angle,
a second side wall (portion of cavity C through first insulating layer 117) provided in the first insulating layer (117) and having a second slope angle,
and a third side wall (portion of cavity C through second insulating layer (115)) provided in the second insulating layer (115) and having a third slope angle,
wherein the second slope angle with respect to an upper surface of the cavity (C) is greater than the first slope angle or the third slope angle with respect to the upper surface of the cavity (C) (Fig. 4C: the slope of the walls of the cavity C in layer 117 is different from the angle of the walls of the cavity C in layer 115), and
Jeon et al. does not teach a semiconductor device disposed in the cavity (C), wherein the semiconductor device overlaps the first side wall (portion of cavity C through protective layer 160) of the cavity (C), the second side wall (portion of cavity C through first insulating layer 117) of the cavity (C), and the third side wall (portion of cavity C through second insulating layer 115) in a horizontal direction.
Kim et al. does teach a semiconductor device (EC) disposed in the cavity (CA), and wherein the semiconductor device (EC) overlaps the portion of the first via electrode (TV), the second side wall (portion of cavity CA through first insulating layer 300) of the cavity (CA), and the third side wall (portion of cavity CA through second insulating layer 200) in a horizontal direction perpendicular to the vertical direction (see Kim et al. Fig. 6 and paragraph 83: component EC disposed in cavity CA).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to place a semiconductor device as taught by Kim et al. overlapping the first via electrode, the second side wall, and the third side wall of Jeon et al. in a horizontal direction because the semiconductor device of Kim et al. increases the functionality of the board (Kim et al. paragraphs 82-5) and the size of the component is a simple matter of design choice. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Regarding claim 18, Jeon et al. in view of Kim et al. teaches the semiconductor package substrate of claim 17, comprising:
a first via electrode (137) including a portion disposed in the first insulating layer (117) (paragraph 52: wiring via 137 embedded in insulating layer 117);
a second via electrode (135) disposed in the second insulating layer (115) (paragraph 52: wiring via 135 embedded in insulating layer 115); and
an intermediate circuit layer (126) disposed between the portion of the first via electrode (137) and the second via electrode (135) (paragraphs 50 and 52: wiring layer 126 is electrically connected to vias 135 and 137); and
wherein the portion of the first via electrode (137) overlaps the second via electrode (135) and the intermediate circuit layer (126) in a vertical direction (see Fig. 4C), and
wherein the semiconductor device overlaps the portion of the first via electrode (137) and the intermediate circuit layer (126) in the horizontal direction (see Kim et al. Fig. 6 and paragraph 83: the semiconductor device EC overlaps the vias TV in a horizontal direction).
Regarding claim 19, Jeon et al. teaches the semiconductor package substrate of claim 17, wherein a width of the second through hole (C) of the cavity (C) is largest at a lower portion of the second through hole positioned in a same plane as a lower surface of the first insulating layer (117) (Figs. 3 and 4C: with the walls of cavity C in layer 160 being perpendicular to the surface of the board, the cavity C is at its widest at the point of layer 117 that is farthest from the center of the board), and
wherein the width of the second through hole (C) of the cavity (C) at the lower portion of the second through hole is greater than a width of a recess portion of the cavity (C) at a lower portion of the recess portion (see Figs. 3 and 4C: the width of cavity C declines closer to the bottom of the cavity, such that the walls are narrowest in layer 115).
Claim(s) 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. in view of Hwang et al. (US 20220039261 A1), hereinafter referred to as Hwang et al.
Regarding claim 14, Jeon et al. teaches the circuit board of claim 2, wherein the second side wall (portion of cavity C through first insulating layer 117) of the cavity (C) has a first height, and the third side wall (portion of cavity C through second insulating layer 115) of the cavity (C) has a second height, but does not teach that the first height of the second side wall (portion of cavity C through first insulating layer 117) of the cavity (C) is different from the second height of the third side wall (portion of cavity C through second insulating layer 115) of the cavity (C) (see Figs. 3 and 4C).
Hwang et al. does teach that the first height of the second side wall (portion of cavity C through Hwang et al.’s first insulating layer 111) of the cavity (C) is different from the second height of the third side wall (portion of cavity C through Hwang et al.’s second insulating layer 113, 115) of the cavity (C) (see Hwang et al. Fig. 3 and paragraph 87: layer 111 is thicker than layers 112-117).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the first insulating layer of Jeon et al. thicker than the second insulating layer as taught by Hwang et al. because a change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Regarding claim 15, Jeon et al. teaches the circuit board of claim 14, wherein the first height is greater than the second height (see Hwang et al. paragraph 87: layer 111 is thicker than layers 112-117).
Claim(s) 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. in view of Kim et al., in further view of Hwang et al.
Regarding claim 20, Jeon et al. in view of Kim et al. teaches the semiconductor package substrate of claim 17, wherein the second side wall (portion of cavity C through first insulating layer 117) of the cavity (C) has a first height, and the third side wall (portion of cavity C through second insulating layer (115)) of the cavity (C) has a second height, but does not teach that the first height of the second side wall (portion of cavity C through first insulating layer 117) of the cavity (C) is greater than the second height of the third side wall (portion of cavity C through second insulating layer (115)) of the cavity (C).
Hwang et al. does teach that the first height of the second side wall (portion of cavity C through Hwang et al.’s first insulating layer 111) of the cavity (C) is different from the second height of the third side wall (portion of cavity C through Hwang et al.’s second insulating layer 113, 115) of the cavity (C) (see Hwang et al. Fig. 3 and paragraph 87: layer 111 is thicker than layers 112-117).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the first insulating layer of Jeon et al. thicker than the second insulating layer as taught by Hwang et al. because a change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Conclusion
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/JOHN B FREAL/Examiner, Art Unit 2847
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