Prosecution Insights
Last updated: October 22, 2026
Application No. 18/782,996

MANAGING CONNECTION STRUCTURES IN SEMICONDUCTOR DEVICES

Non-Final OA §102§103§112
Filed
Jul 24, 2024
Priority
May 20, 2024 — CN 202410627887.0
Examiner
HAIDER, WASIUL
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Yangtze Memory Technologies Co., Ltd.
OA Round
1 (Non-Final)
92%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allowance Rate
510 granted / 554 resolved
+24.1% vs TC avg
Moderate +6% lift
Without
With
+6.4%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 11m
Avg Prosecution
30 currently pending
Career history
571
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
56.5%
+16.5% vs TC avg
§102
22.2%
-17.8% vs TC avg
§112
13.6%
-26.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 554 resolved cases

Office Action

§102 §103 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election with traverse of Species II in the reply filed on 9/14/2026 is acknowledged. Claims 8,15-16,18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected claim, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 9/14/2026. The examiner disagrees. The species are different with different structural and material layout. For example, Species III teaches air gap 404 inside polysilicon (402) which is not stated in other species. Species II teaches the silicide 308a in between 306 and 308b not present in other embodiments. These require separate search strategies causing a search burden. "Serious burden" is a technical term specifically defined in the MPEP. For purposes of the initial requirement, appropriate explanation of separate classification, or separate status in the art, or a different field of search as defined in MPEP § 808.02 may prima facie show a serious burden on the examiner. See MPEP § 803 part II. It is because of such situation the stated restriction is considered as proper. Drawings Corrected drawing is required in this application because Fig. 1 shows gate insulation layer 132 between doped source drain 138 and semiconductor body 130. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 10 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 10, it is not clear as to how the “second end of the connection structure is coupled to the bit line” is being met. For the purpose of examination, it is considered as “second end of the semiconductor body is coupled to the bit line”. Proper connection is requested. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 1. Claim(s) 1,9-12,19 is/are rejected under 35 U.S.C. 102a(2) as being anticipated by US 20250267836 A1 (Liu). Regarding claim 1, Liu shows (Fig. 3G) a semiconductor device, comprising: PNG media_image1.png 346 698 media_image1.png Greyscale a transistor (300, para 24) comprising a semiconductor body (306+316+312, para 26,28,31) having a first end (top of 316) and a second end (bottom of 312) that are doped (para 28,31); and a connection structure (320, para 38) comprising a first end (bottom) and a second end (top), wherein the first end of the connection structure is a seamless conductive portion comprising a conductive material (metal silicide) without air gap, and wherein the first end of the connection structure is in contact with the first end of the semiconductor body. Regarding claim 9, Liu shows (Fig. 3G) further comprising a capacitor having a first electrode (324, para 46), wherein the second end of the connection structure (320) is coupled to the first electrode of the capacitor. Regarding claim 10, Liu shows (Fig. 3G) further comprising a bit line (304, para 24), wherein the second end of the semiconductor body (bottom of 312) is coupled to the bit line. Regarding claim 11, Liu shows (Fig. 3) a method, comprising: forming a transistor (300, para 24) comprising a semiconductor body (306+316+312, para 26,28,31) on a substrate (304 with substrate below not shown, para 24); depositing a dielectric layer (318, para 35) on the semiconductor body; forming an opening (before forming the 320 portion in Fig. 3E) extending through the dielectric layer to expose the semiconductor body; and forming a seamless conductive portion (320, para 38) inside the opening, wherein the seamless conductive portion comprises a conductive material without air gap. Regarding claim 12, Liu shows (Fig. 3G) wherein forming the seamless conductive portion (320) inside the opening (before forming the 320 portion in Fig. 3E) comprises: growing the conductive material (320) from a bottom of the opening towards a top of the opening. Regarding claim 19, Liu shows (Fig. 3F) further comprising: depositing a titanium nitride (TiN) layer and a tungsten (W) layer (322, para 41) on the seamless conductive portion (320). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 1. Claim(s) 2,13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu, as applied to claim 1 or 11 above, further in view of US 20250201727 A1 (Fang). Regarding claim 2, Liu shows the conductive material. Liu does not show wherein the conductive material comprises germanium silicon (GeSi). Fang shows (Fig. 3A) wherein the conductive material (1221, para 64) comprises germanium silicon (GeSi) [64]. It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to modify the invention of Liu, including the conductive material, with the invention of Fang. The motivation to do so is that the combination produces higher conductivity (para 64). Regarding claim 13, the prior art/s as noted in the above rejection of claim 2, discloses the entire claimed invention. 2. Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Fang as applied to claim 2 above further in view of US 20230284439 A1 (Seo). Regarding claim 3, Liu shows the conductive material. Liu does not show wherein the conductive material comprises a N type dopant or a P type dopant. Seo shows (Fig. 9) wherein the conductive material (460) comprises a N type dopant or a P type dopant (doped polysilicon, para 150). It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to modify the invention of Liu, including the conductive material, with the invention of Seo. The motivation to do so is that the combination produces capacitor electrode suitable for the DRAM. 3. Claim(s) 4-5,7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu as applied to claim 1 above further in view of Seo. Regarding claim 4, Liu teaches the connection structure comprises a seamless conductive portion. Liu does not show the connection structure comprises a second conductive portion on the seamless conductive portion. Seo shows (Fig. 9) wherein the conductive material (460) comprises doped polysilicon (para 150). Liu in combination with Lee teaches wherein the connection structure comprises a second conductive portion (460, Seo) on the seamless conductive portion (320, Liu). It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to modify the invention of Liu, including the conductive material, with the invention of Seo. The motivation to do so is that the combination produces capacitor electrode suitable for the DRAM. Regarding claim 5, Liu in combination with Seo teaches wherein the second conductive portion (460, Seo) comprises a silicide material having silicon (Si) and at least one of cobalt (Co) (para 150), nickel (Ni) or tungsten (W). Regarding claim 7, Liu in combination with Seo teaches wherein the second conductive portion (460, Seo) comprises a tungsten (W) layer and a titanium nitride (TiN) layer (Seo, para 150). 4. Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu, as applied to claim 12 above, further in view of US 20110019460 A1 (Wu). Regarding claim 14, Liu teaches wherein the conductive material is grown from the bottom of the opening towards the top of the opening using chemical vapor deposition (CVD) [para 39]. Liu does not show wherein the conductive material is grown from the bottom of the opening towards the top of the opening using epitaxial growth or low-pressure chemical vapor deposition (LPCVD). Wu shows wherein the conductive material is grown from the bottom of the opening towards the top of the opening using epitaxial growth or low-pressure chemical vapor deposition (LPCVD) (para 38). It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to add the invention of Wu, with process for the conductive material growth, to the invention of Liu. The motivation to do so is that the selection of an art recognized process of Wu is suitable for the intended use of Liu (MPEP §2144.07). 5. Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of US 20220149046 A1 (Karda). Regarding claim 20, Liu shows (Fig. 3G) a memory device (DRAM, para 23) configured to store data, the memory device comprising: a transistor (300, para 24) comprising a semiconductor body (306+316+312, para 26,28,31) having a first end (316) and a second end (312) that are doped (para 28,31), and a connection structure (320, para 38) comprising a first end (bottom) and a second end (top), wherein the first end of the connection structure is a seamless conductive portion comprising a conductive material without air gap, and wherein the first end of the connection structure is in contact with the first end of the semiconductor body. Liu is silent regarding a memory controller coupled to the memory device and configured to operate the memory device. PNG media_image2.png 586 630 media_image2.png Greyscale Karda shows (Fig. 4) a memory controller (493, para 77) coupled to the memory device (491, para 77) and configured to operate the memory device. It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to add the invention of Karda, with memory controller, to the invention of Liu. The motivation to do so is that the combination produces the predictable result of a control operation required for the memory device. Allowable Subject Matter Claims 6,17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claim 6, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “wherein the silicide material further comprises germanium (Ge)”. Regarding claim 17, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “depositing a conductive layer on the seamless conductive portion and annealing the conductive layer such that the conductive layer reacts with the conductive material in the seamless conductive portion to form a composite conductive material”. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to WASIUL HAIDER whose telephone number is (571)272-1554. The examiner can normally be reached M-F 9 a.m. - 6 p.m.. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /WASIUL HAIDER/Primary Examiner, Art Unit 2812
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Prosecution Timeline

Jul 24, 2024
Application Filed
Sep 30, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
92%
Grant Probability
98%
With Interview (+6.4%)
1y 11m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 554 resolved cases by this examiner. Grant probability derived from career allowance rate.

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