DETAILED ACTION
This Office Action is in response to Applicant’s application 18/783,070 filed on July 24, 2024 in which claims 1 to 20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings submitted on July 24, 2024 have been reviewed and accepted by the Examiner.
Information Disclosure Statement
The Information Disclosure Statements (IDS), filed on July 24, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein has been considered by the Examiner.
Priority
Receipt is acknowledged of paper submitted under 35 U.S.C. 119(a)-(d) or under 35 U.S.C. 120, 121, 365(c), or 386(c) which has been placed of record in the file.
Notation
References to patents will be in the form of [C:L] where C is the column number and L is the line number. References to pre-grant patent publications will be to the paragraph number in the form of [xxxx].
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 5, 8-9 and 11-12 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by U.S. 10,510,620 (Chanemougame).
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Regarding claim 1 and referring to annotated Figures 1 and 17, Chanemougame discloses a semiconductor device, comprising:
a substrate, 112 [7:22-25], having a first region, nFET 200 [13:38] and annotated, and a second region, pFET 202 [13:38] and annotated;
a first active region, 120N [7:22-25], extending in a first direction, as annotated, on the first region, as shown;
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a second active region, 120P [7:22-25], extending in the first direction, as annotated, on the second region, as shown;
a device isolation layer. 114 [7:24], defining the first and second active regions in the substrate, as shown;
a first gate electrode,196 [12:34-35], crossing the first active region, as shown, and extending in a second direction, as annotated and shown;
a second gate electrode, 170/196 [13:5-40] crossing the second active region, as shown, and extending in the second direction, as annotated and shown;
a plurality of first channel layers, 126 [12:66-13:25], spaced apart from each other, as shown, in a third direction perpendicular to an upper surface of the substrate, as annotated and shown, and surrounded by the first gate electrode on the first active region, as shown;
a plurality of second channel layers, 126 [12:66-132:25], spaced apart from each other in the third direction, as shown, and surrounded by the second gate electrode on the second active region, as shown;
gate insulating layers, 172 [11:60], between the plurality of first channel layers and the first gate electrode, as shown, and between the plurality of second channel layers and the second gate electrode, as shown; and
a gate isolation layer, 160 [13:45-50; 9:11-25], between the first gate electrode and the second gate electrode, as shown, the gate isolation layer including an insulating material, e.g., SiN [9:11-25],
wherein the second gate electrode includes a first conductive layer, 170 [13:5-40], and a second conductive layer, 196 [13:5-40] stacked in order from the plurality of second channel layers, as shown,
wherein the first gate electrode includes the second conductive layer, 196, covering the plurality of first channel layers, as shown, and is spaced apart from the first conductive layer, as shown, and
wherein each of first and second side surfaces of the gate isolation layer in the second direction is in contact with the second conductive layer, as shown.
Regarding claim 2 which depends upon claim 1, Chanemougame, teaches the second side surface of the gate isolation layer is in contact with the first conductive layer in a lower portion of the gate isolation layer as annotated in Figure 17.
Regarding claim 5 which depends upon claim 1, Chanemougame teaches the first conductive layer fills a space between the plurality of second channel layers, and wherein the second conductive layer fills a space between the plurality of first channel layers at Figure 17.
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Regarding claim 8 which depends upon claim 1, Chanemougame teaches the gate insulating layers are isolated from each other by the gate isolation layer and are in contact with the first and second side surfaces of the gate isolation layer in a lower portion of the gate isolation layer, respectively, see Figure 11 and related discussion for Figures 10-11 at [11:59-12:31].
Regarding claim 9 which depends upon claim 1, Chanemougame teaches the first gate electrode does not include the first conductive layer.
Regarding claim 11 which depends upon claim 1, Chanemougame teaches the gate isolation layer is configured as a single layer formed of an insulating material, e.g., SiN.
Regarding claim 12 which depends upon claim 1, Chanemougame teaches at Figure 9 a lower surface of the gate isolation layer is on a level lower than a level of upper surfaces of the first and second active regions.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 13-17 are rejected under 35 U.S.C. 103 as being unpatentable over Chanemougame and U.S. 2023/0369466 (Huang).
Regarding claim 13 which depends upon claim 1, Chanemougame does not explicitly teach the first active region and the second active region include impurities of different conductivity types.
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Huang is directed to MUGFETs using work function gate metallurgy. Huang discloses a semiconductor device, comprising: a first active region, 204-2 [0021], and a second active region, 204-1 [0021], extending in a first direction, X, on a substrate, 202 [0016], spaced apart from each other in a second direction, Y, intersecting the first direction, as shown, the first and second active regions including impurities of different conductivity types from each other as described [0021]; a first gate electrode, 234 [0033], crossing the first active region, as shown, and extending in the second direction, Y as shown; a second gate electrode, 230 / 234 [0033], crossing the second active region, as shown, and extending in the second direction, Y as shown; and a gate isolation layer, 214 [0031], between the first and second gate electrodes, as shown, wherein the second gate electrode includes a first conductive layer, 230 [0033], and a second conductive layer, 234 [0033], stacked in order, as shown, wherein the first gate electrode includes the second conductive layer, 234 [0033], wherein a first side surface of the gate isolation layer in the second direction faces the first gate electrode and is in contact with the second conductive layer, 234 as shown, and wherein a second side surface opposing the first side surface of the gate isolation layer faces the second gate electrode and is in contact with the first conductive layer, 230 as shown, and the second conductive layer in order from a lower portion of the gate isolation layer.
Taken as a whole the prior art is directed to CMOS devices. Huang teaches the use of n wells for pFETs which is recognized in the art for utility in isolating the pFET device to improve device functionality.
Accordingly, it would have been obvious to a person of ordinary skill in the art at the time of Applicant’s invention to configure the device of claim 1 wherein the first active region and the second active region include impurities of different conductivity types, as taught by Huang, to improve performance of the p-device and because the combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
Regarding claim 14 and referring to the discussion at claim 1, Chanemougame discloses a semiconductor device, comprising: a first active region, 120N [7:22-25], and a second active region, 120P [7:22-25], extending in a first direction, as annotated, on a substrate, 112 [7:22-25], spaced apart from each other in a second direction, as annotated, intersecting the first direction, as shown; a first gate electrode, 196 [13:35-45], crossing the first active region, as shown, and extending in the second direction, as shown; a second gate electrode, 170/196 [13:5-50], crossing the second active region, as shown, and extending in the second direction, as shown,; and a gate isolation layer, 60 [13:45-50; 9:11-25], between the first and second gate electrodes, as shown, wherein the second gate electrode includes a first conductive layer, 170, and a second conductive layer, 196, stacked in order, wherein the first gate electrode includes the second conductive layer, 196 as shown, and is spaced apart from the first conductive layer, as shown, wherein a first side surface of the gate isolation layer in the second direction faces the first gate electrode and is in contact with the second conductive layer, as shown, and wherein a second side surface opposing the first side surface of the gate isolation layer faces the second gate electrode and is in contact with the first conductive layer and the second conductive layer in order from a lower portion of the gate isolation layer, as shown.
Chanemougame does not explicitly teach the first and second active regions including impurities of different conductivity types from each other.
Referring to the discussion above, Huang teaches the first and second active regions including impurities of different conductivity types from each other, i.e., well for the p-FET.
Taken as a whole the prior art is directed to MUFETS. An artisan would recognize that a p-device in a n-well improves the functionality of the device.
Accordingly, it would have been obvious to a person of ordinary skill in the art at the time of Applicant’s invention to configure the device of claim 1 wherein the first active region and the second active region include impurities of different conductivity types, as taught by Huang, to improve performance of the p-device and because the combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
Regarding claim 15 which depends upon claim 14, Chanemougame teaches a first height of a first portion of the second side surface in contact with the first conductive layer is less than a second height of a second portion of the second side surface in contact with the second conductive layer where the datum is the bottom of the first conductive film on the sidewall of the gate isolation.
Regarding claim 16 which depends upon claim 15, Chanemougame suggests the second height is 10 times the first height or more at Figure 17.
Regarding claim 17 which depends upon claim 14, Chanemougame teaches the first conductive layer and the second conductive layer have different compositions [13:5-10].
Allowable Subject Matter
Claims 3-4, 6-7, 10 and 18 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3 the prior art does not teach the device of claim 1, wherein the second conductive layer extends horizontally from the first and second side surfaces of the gate isolation layer along an upper surface of the device isolation layer.
Claim 4 depends upon claim 3 and is allowable on that basis.
Regarding claim 6 the prior art does not teach the device of claim 1, wherein the first gate electrode further includes a third conductive layer on the second conductive layer and between the gate isolation layer and the plurality of first channel layers in the second direction.
Claim 7 depends upon claim 6 and is allowable on that basis.
Regarding claim 10 the prior art does not teach the device of claim 1, wherein an upper surface of the gate isolation layer is coplanar with an upper surface of the first gate electrode and an upper surface of the second gate electrode.
Regarding claim 18 the prior art does not teach the device of claim 14, wherein the first side surface is entirely covered by the gate insulating layer and the second conductive layer.
Claims 19-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 19, the prior art fails to disclose the device of claim 19 wherein the first gate electrode includes the second conductive layer and the third conductive layer stacked in order, and is spaced apart from the first conductive layer, and wherein each of side surfaces of the gate isolation layer in the second direction is in contact with the second conductive layer and is spaced apart from the third conductive layer.
Claim 20 depends upon claim 19 and is allowable on that basis.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is listed on the notice of references cited.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Joe Schoenholtz whose telephone number is (571)270-5475. The examiner can normally be reached M-Thur 7 AM to 7 PM PST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ms. Yara Green can be reached at (571) 272-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.E. Schoenholtz/Primary Examiner, Art Unit 2893
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