DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “a gate structure formed around each of the CNTs in a channel region; a doped semiconductor layer wrapping around each of the CNTs in a source/drain region; wherein the doped semiconductor layer is not in contact with the substrate” of claim 1 and claim 11, “the work function adjustment layer partially wraps around the CNTs with the gate dielectric layer” of claim 13; “the source/drain structures are disposed between the support layer and the CNTs; a gate structure wrapped around the CNTs in a channel region” of claim 17; “ must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The specification is objected to as failing to provide a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o).
Correction of the following is required: claim 1 and claim 11 each recites the limitation “a gate structure formed around each of the CNTs in a channel region; a doped semiconductor layer wrapping around each of the CNTs in a source/drain region; wherein the doped semiconductor layer is not in contact with the substrate;” claim 17 recites “the source/drain structures are disposed between the support layer and the CNTs; a gate structure wrapped around the CNTs in a channel region”. However, there is no evidence of a complete specific application or embodiment in which a gate structure formed around each of the CNTs in a channel region and the doped semiconductor layer is not in contact with the substrate to satisfy the requirement that the description is set forth “in such full, clear, concise, and exact terms” to make and use the same. Specifically, the specification discloses embodiments having a gate structure formed around each of the CNTs in a channel region in Fig. 14B and Fig. 21. However, these embodiments require the doped semiconductor layer is in contact with the substrate. The specification discloses an embodiment in which the doped semiconductor layer is not in contact with the substrate in Fig. 29B. However, this embodiment does not have a gate structure formed around each of the CNTs in a channel region. The gate structure in Fig. 29B is formed on one side of each of the CNTs in a channel region.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claims 1, 11 and 17, claim 1 and claim 11 each recites the limitation “a gate structure formed around each of the CNTs in a channel region; a doped semiconductor layer wrapping around each of the CNTs in a source/drain region; wherein the doped semiconductor layer is not in contact with the substrate”; claim 17 recites ““the source/drain structures are disposed between the support layer and the CNTs; a gate structure wrapped around the CNTs in a channel region”. However, there is no evidence of a complete specific application or embodiment having “a gate structure formed around each of the CNTs in a channel region and the doped semiconductor layer is not in contact with the substrate” to satisfy the requirement that the description is set forth “in such full, clear, concise, and exact terms” to make and use the same. Specifically, the specification discloses embodiments having a gate structure formed around each of the CNTs in a channel region in Fig. 14B and Fig. 21. However, these embodiments require the doped semiconductor layer is in contact with the substrate. The specification discloses an embodiment in which the doped semiconductor layer is not in contact with the substrate in Fig. 29B. However, this embodiment does not have a gate structure formed around each of the CNTs in a channel region. The gate structure in Fig. 29B is formed on one side of each of the CNTs in a channel region.
Further, there is no description of any such steps whether conventional or inventive that demonstrates possession thereof or therefor.
The purpose of the written description requirement in 35 U.S.C. §112(a) is to determine if “the description clearly allow persons of ordinary skill in the art to recognize that he or she invented what is claimed." In re Gosteli, 872 F.2d 1008, 1012, 10 USPQ2d 1614, 1618 (Fed. Cir. 1989). See also MPEP § 2163.02. In addition, the written description requirement of 35 U.S.C.§112(a) applies to all claims including original claims that are part of the disclosure as filed. Ariad, 598 F.3d at 1349. As stated by the Federal Circuit, “[a]lthough many original claims will satisfy the written description requirement, certain claims may not.” Ariad, 598 F.3d at 1349; "[e]ven if a claim is supported by the specification, the language of the specification, to the extent possible, must describe the claimed invention so that one skilled in the art can recognize what is claimed. The appearance of mere indistinct words in a specification or a claim, even an original claim, does not necessarily satisfy that requirement." Enzo Biochem, Inc. v. Gen-Probe, Inc., 323 F.3d 956, 968, 63 USPQ2d 1609, 1616 (Fed. Cir. 2002); see also LizardTech, Inc. v. Earth Res. Mapping, Inc., 424 F.3d 1336, 1343–46 (Fed. Cir. 2005). "Generic claim language appearing in ipsis verbis in the original specification does not satisfy the written description requirement if it fails to support the scope of the genus claimed [see Ariad Pharmaceuticals, Inc. v. Eli Lilly & Co. (Fed. Cir. 2010) (en banc)].” See also MPEP §2163.03.
The instant specification lacks any description of an actual reduction to practice which would be evidenced by specific examples, drawings and an accompanied description of structural features and/or an accompanied description of processing steps, etc. that are sufficiently detailed to show that Applicant was in possession of the claimed invention as a whole. Thus there is no evidence of a complete specific application or embodiment to satisfy the requirement that the description is set forth “in such full, clear, concise, and exact terms” to show possession of the claimed invention. Fields v. Conover, 443 F.2d 1386, 1392, 170 USPQ 276, 280 (CCPA 1971).
Accordingly, claim 1, claim 11, claim 17 and all claims depending therefrom were not in possession of Applicant at the time of filing.
Claims depending from the rejected claims noted above are rejected at least on the same basis as the claim(s) from which the dependent claims depend.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 7, claim 7 recites “the gate dielectric layer does not fully surround the CNTs” while claim 1 and claim 6 on which claim 7 depend require “a gate structure formed around each of the CNTs” and “a gate dielectric layer wrapping around the CNTs in the channel region.” It is unclear how a gate dielectric layer wrapping around the CNTs and does not fully surround the CNTs.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 8-11, 16-17, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Cohen et al. (US Pub. 20140014904) in view of Cheng et al. (US Pub. 20160027870) and Lu et al. (US Pub. 20180366666).
Regarding claims 1, 8 and 9, Cohen et al. discloses in Fig. 12, Fig. 14 a semiconductor device having a field effect transistor (FET), comprising:
one-dimensional structures [104] disposed over a substrate [101];
a gate structure [110 and 112] formed around each of the one-dimensional structures [104] in a channel region;
a conductive S/D layer [290] wrapping around each of the one-dimensional structures [104] in a source/drain region, wherein the conductive S/D layer [290] is not in contact with the substrate [101];
a support layer [102] disposed between the conductive S/D layer [290] and the substrate [101];
wherein the support layer [102] comprises an insulating material [BOX].
Cohen et al. fails to disclose
the one-dimensional structures comprise carbon nanotubes (CNTs).
Lu et al. discloses in Fig. 1A, paragraph [0002]
the one-dimensional structures comprise carbon nanotubes (CNTs).
It would have been obvious to one of ordinary skill in the art at the time of the effective filling date of the invention to incorporate the teachings of Lu et al. into the method of Cohen et al. to include the one-dimensional structures comprise carbon nanotubes (CNTs). The ordinary artisan would have been motivated to modify Cheng et al. in the above manner for the purpose of providing suitable material for forming GAA device that provides superior electrostatics and high performance [paragraph [0002] of Lu et al.].
Cohen et al. fails to disclose
the conductive S/D layer comprises a doped semiconductor layer; and
a source/drain contact formed over the doped semiconductor layer.
Lu et al. discloses in Fig. 1A
a source/drain contact [40] formed over the conductive S/D layer [35].
Cheng et al. discloses in Fig. 1A, paragraph [0042]-[0043], [0068]-[0070]
the conductive S/D layer [25 or 30] comprises a doped semiconductor layer;
a source/drain contact [40] formed over the doped semiconductor layer [25 or 30].
It would have been obvious to one of ordinary skill in the art at the time of the effective filling date of the invention to incorporate the teachings of Cheng et al. and Lu et al. into the method of Cohen et al. to include the conductive S/D layer comprises a doped semiconductor layer; a source/drain contact formed over the doped semiconductor layer. The ordinary artisan would have been motivated to modify Cohen et al. in the above manner for the purpose of forming S/D contact structure that dictates the conductivity type of the device [paragraph [0042], [0043] of Cheng et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 2, Cheng et al. discloses in paragraph [0042]-[0043], [0068]-[0070] wherein the doped semiconductor layer [25 or 30] is crystalline silicon.
Regarding claim 3, Cohen et al., Cheng et al. and Lu et al. fails to disclose wherein an impurity concentration in the doped semiconductor layer is in a range from 1 x 1020 atoms/cm3 to 1 x 1021 atoms/cm3.
However, Applicant has not provided any criticality of the claimed range. Thus, it would have been obvious to modify Cohen et al., Cheng et al. and Lu et al. to provide the claimed range for at least the purpose of optimization and routine experimentation to obtain desired conductivity for the S/D region [paragraph [0071] of Cheng et al.] The claimed ranges are merely optimizations, and as such are not patentable over the prior art. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). "The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages." Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382.
Regarding claims 4-5, Cheng et al. discloses in paragraph [0042]
wherein the GAA FET is an n-type FET and the doped semiconductor layer [25, 30] contains at least one of P and As as impurities;
wherein the GAA FET is a p-type FET and the doped semiconductor layer contains at least one of B and Ga as impurities.
Regarding claim 10, Cohen discloses in paragraph [0033] the substrate [101] is made of one of Si and SiGe [Si substrate].
Lu et al. discloses in paragraph [0052] the substrate [10] is made of one of Si and SiGe.
Cheng et al. discloses in paragraph [0026], [0042], [0043], [0069] wherein the doped semiconductor layer [25, 30] and the substrate [5] are made of one of Si and SiGe.
Regarding claims 11 and 16, Cohen et al. discloses in Fig. 12, Fig. 14 a semiconductor device having a gate-all-around field effect transistor, comprising:
an isolation insulating layer [102] disposed over a substrate [101];
one-dimensional structures [104] disposed over the substrate [101];
a gate structure [110 and 112] formed around each of the one-dimensional structures [104] in a channel region;
a conductive S/D layer [290] wrapping around each of the one-dimensional structures [104] in a source/drain region, wherein the conductive S/D layer [290] is not in contact with the substrate [101];
wherein the conductive S/D layer [290] is in contact with the isolation insulating layer [102].
Cohen et al. fails to disclose
the one-dimensional structures comprise carbon nanotubes (CNTs).
Lu et al. discloses in Fig. 1A, paragraph [0002]
the one-dimensional structures comprise carbon nanotubes (CNTs).
It would have been obvious to one of ordinary skill in the art at the time of the effective filling date of the invention to incorporate the teachings of Lu et al. into the method of Cohen et al. to include the one-dimensional structures comprise carbon nanotubes (CNTs). The ordinary artisan would have been motivated to modify Cheng et al. in the above manner for the purpose of providing suitable material for forming GAA device that provides superior electrostatics and high performance [paragraph [0002] of Lu et al.].
Cohen et al. fails to disclose
the conductive S/D layer comprises a doped semiconductor layer; and
a source/drain contact formed over the doped semiconductor layer;
wherein the doped semiconductor layer is made of SiGe.
Lu et al. discloses in Fig. 1A
a source/drain contact [40] formed over the conductive S/D layer [35].
Cheng et al. discloses in Fig. 1A, paragraph [0042]-[0043], [0068]-[0070]
the conductive S/D layer [25 or 30] comprises a doped semiconductor layer;
a source/drain contact [40] formed over the doped semiconductor layer [25 or 30];
wherein the doped semiconductor layer [25 or 30] is made of SiGe.
It would have been obvious to one of ordinary skill in the art at the time of the effective filling date of the invention to incorporate the teachings of Cheng et al. and Lu et al. into the method of Cohen et al. to include the conductive S/D layer comprises a doped semiconductor layer; a source/drain contact formed over the doped semiconductor layer; wherein the doped semiconductor layer [25 or 30] is made of SiGe. The ordinary artisan would have been motivated to modify Cohen et al. in the above manner for the purpose of forming S/D contact structure that dictates the conductivity type of the device [paragraph [0042], [0043] of Cheng et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claims 17 and 20, Cohen et al. discloses in Fig. 12, Fig. 14 a semiconductor device comprising:
one-dimensional structures [104] disposed over a substrate [101];
a support layer [102] between the substrate [101] and the one-dimensional structures [104];
source/drain structures [290] wrapped around the one-dimensional structures [104], wherein the source/drain structures [290] are disposed between the support layer [102] and the one-dimensional structures [104], and
a gate structure [110 and 112] wrapped around the one-dimensional structures [104] in a channel region.
Cohen et al. fails to disclose
the one-dimensional structures comprise carbon nanotubes (CNTs).
Lu et al. discloses in Fig. 1A, paragraph [0002]
the one-dimensional structures comprise carbon nanotubes (CNTs).
It would have been obvious to one of ordinary skill in the art at the time of the effective filling date of the invention to incorporate the teachings of Lu et al. into the method of Cohen et al. to include the one-dimensional structures comprise carbon nanotubes (CNTs). The ordinary artisan would have been motivated to modify Cheng et al. in the above manner for the purpose of providing suitable material for forming GAA device that provides superior electrostatics and high performance [paragraph [0002] of Lu et al.].
Cohen et al. fails to disclose
the source/drain structures comprise a doped semiconductor material;
source/drain contacts disposed over the source/drain structures;
wherein the doped semiconductor layer comprises SiGe.
Lu et al. discloses in Fig. 1A
a source/drain contact [40] formed over the source/drain structures [35].
Cheng et al. discloses in Fig. 1A, paragraph [0042]-[0043], [0068]-[0070]
the source/drain structures [25 or 30] comprises a doped semiconductor layer;
a source/drain contact [40] disposed over the source/drain structures [25 or 30];
wherein the doped semiconductor layer [25 or 30] comprises SiGe.
It would have been obvious to one of ordinary skill in the art at the time of the effective filling date of the invention to incorporate the teachings of Cheng et al. and Lu et al. into the method of Cohen et al. to include the source/drain structures comprise a doped semiconductor material; source/drain contacts disposed over the source/drain structures; wherein the doped semiconductor layer comprises SiGe. The ordinary artisan would have been motivated to modify Cohen et al. in the above manner for the purpose of forming S/D contact structure that dictates the conductivity type of the device [paragraph [0042], [0043] of Cheng et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claims 12-15, 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Cohen et al. (US Pub. 20140014904) in view of Cheng et al. (US Pub. 20160027870) and Lu et al. (US Pub. 20180366666) as applied to claim 11 and claim 17 above and further in view of Kim et al. (US Pub. 20200381311).
Regarding claims 12-15, Cohen et al. discloses in Fig. 14
wherein the gate structure [112 and 110] includes a gate dielectric layer [112] wrapping around the one-dimensional structures [104], a body gate electrode layer [110] formed on the gate dielectric layer [112].
Lu et al. discloses in Fig. 1A, paragraph [0002]
the one-dimensional structures comprise carbon nanotubes (CNTs).
Cohen et al. and Lu et al. fails to disclose
a work function adjustment layer formed on the gate dielectric layer, and the body gate electrode layer formed on the work function adjustment layer;
wherein the work function adjustment layer partially wraps around the CNTs with the gate dielectric layer;
wherein the gate dielectric layer includes one selected from the group consisting of HfO2 and Al2O3;
wherein the work function adjustment layer includes TiN.
Kim et al. discloses in Fig. 2B, paragraph [0047], [0051], [0055]
a work function adjustment layer [WF1 and/or WF2] or [WF1’ and/or WF2] formed on the gate dielectric layer [GI], and the body gate electrode layer [GE] formed on the work function adjustment layer [WF1 and/or WF2];
wherein the work function adjustment layer [WF2] partially wraps around the one-dimensional structures [NS] with the gate dielectric layer [GI];
wherein the gate dielectric layer [GI] includes one selected from the group consisting of HfO2 and Al2O3;
wherein the work function adjustment layer includes TiN.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Kim et al. into the method of Cohen et al. and Lu et al. to include a work function adjustment layer formed on the gate dielectric layer, and the body gate electrode layer formed on the work function adjustment layer; wherein the work function adjustment layer partially wraps around the CNTs with the gate dielectric layer; wherein the gate dielectric layer includes one selected from the group consisting of HfO2 and Al2O3; wherein the work function adjustment layer includes TiN. The ordinary artisan would have been motivated to modify Cohen et al. and Lu et al. in the above manner for the purpose of providing transistor with desired threshold voltage [paragraph [0049]-[0050], [0052] of Kim et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 18, Cohen et al. discloses in Fig. 14
wherein the gate structure [112 and 110] includes a gate dielectric layer [112] wrapping around the one-dimensional structures [104], a body gate electrode layer [110] formed on the gate dielectric layer [112].
Lu et al. discloses in Fig. 1A, paragraph [0002]
the one-dimensional structures comprise carbon nanotubes (CNTs).
Cohen et al. and Lu et al. fails to disclose
a work function adjustment layer formed on the gate dielectric layer, and the gate electrode layer formed on the work function adjustment layer.
Kim et al. discloses in Fig. 2B, paragraph [0047], [0051], [0055]
a work function adjustment layer [WF1 and WF2] or [WF1’ and WF2] formed on the gate dielectric layer [GI], and the gate electrode layer [GE] formed on the work function adjustment layer [WF1 and WF2].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Kim et al. into the method of Cohen et al. and Lu et al. to include a work function adjustment layer formed on the gate dielectric layer, and the gate electrode layer formed on the work function adjustment layer. The ordinary artisan would have been motivated to modify Cohen et al. and Lu et al. in the above manner for the purpose of providing transistor with desired threshold voltage [paragraph [0049]-[0050], [0052] of Kim et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 19, Lu et al. discloses in Fig. 1A
wherein the source/drain contacts [60] are not in contact with the substrate [10].
Cheng et al. discloses in Fig. 1A
wherein the source/drain contacts [40] are not in contact with the substrate [5].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SOPHIA T NGUYEN whose telephone number is (571)272-1686. The examiner can normally be reached 9:00am -5:00 pm, Monday-Friday.
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/SOPHIA T NGUYEN/ Primary Examiner, Art Unit 2893
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