DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 3/4/2026 have been fully considered but they are not persuasive.
Note: the amendment filed is a different version compared to what was discussed in an interview dated 2/11/2026.
The amended claim 1 recites “a voltage adjustment portion that applies the total voltage offset to the second bit line and not to the first bit line”: the fig 10 of prior art Cao (reproduced below) shows voltage on BL is adjusted, but voltage on BLB is not changed during t2-t3, comparing to the voltages during t1-t2.
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The argument to claim 16/20 is not persuasive for the same reason as stated above.
Allowable Subject Matter
Claim 11, 13-15 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-4, 16 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cao et al. (PGPUB 20220013152), hereinafter as Cao.
Regarding claim 1, Cao teaches a memory device comprising:
a memory cell (present but not shown); and
a differential latch sense amplifier (Fig 1) connected to a first bit line (Fig 1, BLB) that shares charge with the memory cell and a second bit line (Fig 1, BL) that does not share charge with the memory cell (in a sensing case, one of the BL of the two BLs will have same potential as that of precharged voltage, thus no charge share), the differential latch sense amplifier comprising:
a voltage offset determining portion that determines a total voltage offset for the first bit line and the second bit line (Fig 10, t1-t2, and [0106] circuits involved);
a voltage adjustment portion that applies the total voltage offset to the second bit line and not to the first bit line to generate an adjusted second voltage (Fig 10, t2-t3 and circuits involved, voltage on BL changed while on BLB is not changed, and also argument used in section Response to Argument); and
a voltage comparison portion that compares a first voltage of the first bit line to the adjusted second voltage to determine a value of the memory cell (Fig 10, t4-t5 and circuits involved).
Regarding claim 3, Cao teaches the voltage adjustment portion comprises a differential amplifier (Fig 1, the SA is a latching and also a differential amplifier).
Regarding claim 4, Cao teaches the differential amplifier comprises a first input connected to the first bit line and a second input connected to the second bit line (Fig 1, NODE1 to BL and NODE2 to BLB).
Regarding claim 16, Cao teaches a method comprising: determining, for a differential latch sense amplifier (Fig 1), a voltage offset between a first portion of the differential latch sense amplifier connected to a first bit line and a second portion of the differential latch sense amplifier connected to a second bit line (Fig 10, t1-t2); and pre-charging the second bit line and the first bit line to different voltages by applying the voltage offset to the second bit line and not to the first bit line (Fig 10, t2-t3, and arguments used in rejection of claim 1/Response to Argument above applies).
Regarding claim 20, Cao teaches a memory device comprising: a memory cell; and a sense amplifier coupled to a first bit line that shares charge with the memory cell and a second bit line that does not share charge with the memory cell (Fig 1, BL and BLB);
wherein in a first phase of a sense operation, first devices of the sense amplifier are configured as a differential amplifier to measure an offset characteristic of the sense amplifier (Fig 10, t1-t2, and circuits involved) and apply the offset characteristic to the second bit line and not to the first bit line (Fig. 10, and argument used in rejection of claim 1 applies), and
wherein in a second phase of the sense operation, at least a portion of the same first devices of the sense amplifier are configured to provide information about a charge stored in the memory cell, and the information about the charge stored in the memory cell is based in part on the measured offset characteristic (Fig 10, and [0106-0107]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 5-10, 12, 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cao.
Regarding claim 2, Cao teaches an output portion that is connected to the voltage comparison portion of the differential latch sense amplifier to provide a binary indication of a data value stored by the memory cell (the examiner takes note that an output circuit is well known for a memory device).
Regarding claim 5, Cao teaches the differential amplifier comprises an output connected to the second bit line (the examiner takes note that an output circuit is well known for a memory device).
Regarding claim 6, Cao teaches the differential latch sense amplifier comprises: a first transistor, the first bit line connected to a source of the first transistor (Fig 1, BLB connected to a source of P1 when S3 is connected); and a second transistor, the first bit line connected to a gate of the second transistor (Fig 1, gate of N2).
Regarding claim 7, Cao teaches the differential latch sense amplifier comprises: a third transistor, the second bit line connected to a source of the third transistor (Fig 1, BL connected to a source of P2 when S4 is connected); and a fourth transistor (Fig 1, N1), the second bit line connected to a gate of the fourth transistor.
Regarding claim 8, Cao teaches the differential latch sense amplifier comprises: a fifth transistor (Fig 1, S2), the first bit line connected to a source of the fifth transistor; and a sixth transistor (Fig 1, S3), the first bit line connected to a drain of the sixth transistor.
Regarding claim 9, Cao teaches a seventh transistor (Fig 1, S4), the second bit line connected to a source of the seventh transistor; and an eighth transistor (Fig 1, S1), the second bit line connected to a drain of the eighth transistor.
Regarding claim 10, Cao teaches a source of the sixth transistor is connected to a source of the eighth transistor (Fig 1, S1 and S3 have a common connection NODE2).
Regarding claim 12, Cao teaches
a first transistor (Fig 1, P3), wherein a voltage source is connected to a drain of the first transistor and a control signal (Fig 1, Sense_P) is connected to a gate of the first transistor;
a second transistor (P1), wherein a source of the first transistor is connected to a source of the second transistor; a third transistor (N1), wherein a drain of the second transistor is connected to a source of the third transistor;
a fourth transistor (P2), wherein the source of the first transistor is connected to a source of the fourth transistor; and a fifth transistor (N2), wherein a drain of the fourth transistor is connected to a source of the fifth transistor.
Regarding claim 17, Cao teaches configuring a differential amplifier based on the determined voltage offset, wherein the pre-charging of the second bit line and the first bit line includes using the differential amplifier (Fig 10, t1-t2-t3).
Regarding claim 18, Cao teaches sharing charge from a memory cell with the pre-charged first and second bit lines; and after the sharing of the charge, determining a value of the memory cell based on a comparison of a first voltage of the first bit line to a second voltage of the second bit line (Fig 10, t1-t5).
Regarding claim 19, Cao teaches providing a comparison result indicating the value of the memory cell, wherein the comparison result comprises a differential voltage signal ([0020] output …readout).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIN HUANG whose telephone number is (571)270-5798. The examiner can normally be reached M-F 9-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571)272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MIN HUANG/Primary Examiner, Art Unit 2827