DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on September 18, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The disclosure is objected to because of the following informalities:
The specification has several problems causing confusion.
The two biggest problems are the following:
A single memory string 108 is disclosed in FIG. 1, which is consistent with the standard definition used in the art BUT then Applicant starts referring to multiple strings in block 408 as a memory string, which conflicts not only with grammar but with the standard definitions in the art. Examiner believes that block 408 in FIG. 4 is consistent with what one of ordinary skill in the art refers to as a sub-block. A plurality of NAND strings having select gates commonly connected by a same select line such as DSG0 is known as a sub-block in the art.
The other major problem is Applicant discloses applying a select voltage (see [0073]) to an unselected select line DSG in a prepulse phase of a verification operation, and the duration of applying this voltage to an unselected DSG line in respective verification operations is varied (see FIG. 7, FIG. 8, and FIG. 9) such that a pulse is shorter when higher program target states are being verified (see [0072, 0081, 0085]); however, Applicant then suddenly erroneously changes the term “a select voltage” to “a pass voltage” when referring to a flow chart in FIG. 10. This is an error because these two voltages are different and have different meanings in the art; hence, the different names. The term “pass voltage” is recognized by one of ordinary skill in the art to be a voltage applied to unselected word lines as seen in FIG. 7, FIG. 8, and FIG. 9 that is higher than any threshold voltage of all the programmed memory cells (memory cell transistors) such that memory cells on the unselected word line becomes conductive no matter which programmed state each of them may be in whereas “a select voltage” is a voltage applied to a transistor, a select gate transistor or a plurality thereof in the case of this application, that is just high enough to turn ON the transistor(s) that used as drain select transistor(s) (see on-state in [0073]).
It is suggested to amend the specification as follows:
[0009] In some implementations, the first memory cells are triple-level cells programmable to one of seven programmed states P1, P2, P3, P4, P5, P6 and P7 in an ascending order. The first programmed state includes one of Pl, P2 or P3, the second programmed state includes one of P4 or P5, and the third programmed state includes one of P6 or P7.
[0042] In some implementations, all of the unselected memory strings in the same block as the selected memory string are pre-pulsed during the pre-pulse phase. In some other implementations, unselected memory strings in the same finger as the selected memory string are pre-pulsed during the pre-pulse phase, while memory strings in unselected fingers are not pre-pulsed. This can mitigate the coupling effect by unselected memory strings on the selected word line, thereby reducing the time to establish voltages on the selected word line.
[0043] Program time can refer to time spent or needed to perform a program operation. In some implementations, program time can increase due to the time needed for a pre-pulse phase for each verification operation during the program operation. This present disclosure provides techniques to manage program time in a memory device. In some implementations, instead of setting the same duration for pre-pulse phases of different verification operations that verify different programmed states, the duration of pre-pulse phases can vary based on the programmed states to be verified in the respective verification operations. For example, since memory cells in low programmed states (e.g., P1, P2 and P3 of triple-level cells (TLCs)) are more sensitive to HCI effect, a verification operation that verifies a low programmed state can have a long pre-pulse phase. Memory cells in middle programmed states (e.g., P4, P5 of TLCs) can be less sensitive to HCI effect than the memory cells in a low programmed state. Therefore, a verification operation that verifies a middle programmed state can have a shorter pre-pulse phase. Memory cells in high programmed states (e.g., P6, P7 of TLCs) can be even less sensitive to HCI effect. Therefore, a verification operation that verifies a high programmed state can have an even shorter pre-pulse phase, or may not include a pre-pulse phase. As such, by shortening the duration of pre-pulse phases (also referred to as a pre-pulse duration) in verification operations that verify middle and high programmed states, total time needed to perform a program operation can be reduced, and an efficiency of the memory device can be improved. In some implementations, each programmed state of a xLC can have a different pre-pulse duration, where xLC includes a multi-level cell (MLC), a triple-level cell (TLC), a quad-level cell (QLC), or a higher-level cell. In some implementations, programmed states of a xLC can be divided into multiple groups, as the example described above, and different groups have different pre-pulse durations, while each programmed state in a same group shares the same pre-pulse duration.
[0055] FIG. 4 illustrates an example of a schematic diagram of a block 304 including memory sub-blocks 408, 418 according to some aspects of the present disclosure. In some implementations, block 304 can be divided into fingers 402, 404 (e.g., finger 334 of FIG. 3). SSG transistors 110 of memory sub-blocks 408, 418 in the same finger 402, 404 are coupled to the same SSG line 115. For example, as shown in FIG. 4, a first finger 402 includes memory sub-blocks 408, 418. SSG transistors 110 of memory string 408, 418 are coupled to a first SSG line represented by SSG0. A second finger 404 includes memory strings each having a SSG transistor 110 that is coupled to a second SSG line represented by SSG1.
[0056] In some implementations, each finger 402, 404 can include one or more memory sub-blocks 408, 418. DSG transistors 112 in the same memory sub-block 408, 418 are coupled to the same DSG line 113. For example, as shown in FIG. 4, the first finger 402 and the second finger 404 each includes one or more memory sub-blocks . A first memory sub-block 408 in the first finger 402 is coupled to a first DSG line represented by DSG0. A second memory sub-block 418 in the first finger 402 is coupled to a second DSG line represented by DSG1. The second finger 404 can include a third memory sub-block coupled to a third DSG line represented by DSG 2, and a fourth memory sub-block coupled to a fourth DSG line represented by DSG 3.
[0057] In some implementations, memory cells 106 in adjacent memory strings 408, 418 can be coupled through word lines. Example word lines shown in FIG. 4 include Dummy WL, WL1, WL2, WL3, WL4, and WL5 that are between DSG line and SSG line. For example, memory cells 106 of the same vertical position (e.g., along z direction) in adjacent memory sub-blocks 408, 418 are coupled to the same word line.
[0058] In some implementations, the DSG transistors 112 of different strings (e.g., string 108 of FIG. 1) in the same memory sub-block 408, 418 are coupled to different bit lines 116, 126. For example, DSG transistor 112 of a first string of the first memory string 408 is coupled to a first bit line 116, and DSG transistor 112 of a second string of the first memory sub-block 408 is coupled to a second bit line 126. A bit line 116, 126 can connect strings of different memory sub-blocks . For example, the first string of the first memory sub-block 408 and a third string of the second memory sub-block 418 are both coupled to the first bit line 116 through their respective DSG transistors 112.
[0065] FIG. 6A illustrates an example incremental step pulse programming (ISPP) scheme, according to some aspects of the present disclosure. The ISPP scheme 620 can include a plurality of program pulses 630, 640, 650, 660, 670. Each program pulse can have a program voltage Vpgm (e.g., a voltage between 10 V and 30 V), and can have a pulse length (e.g., a time duration between 1 µs and 3- µs) during which the program voltage is applied. In some implementations, a starting or initial program pulse 630 can have a program voltage Vpgm_start, and the program voltages of the following program pulses 640, 650, 660, 670 are each incremented by voltage ΔVpgm. The pulse length of the program pulses 630, 640, 650, 660, 670 can be the same. In some implementations, the memory device can apply several program pulses 630, 640, 650, 660, 670 to program memory cells 106 to a target programmed state.
[0070] FIG. 7 illustrates an example of voltages of components in a block (e.g., block 304 of FIGs. 3-4) during a verification operation 700 of the block, according to some aspects of the present disclosure. A memory string (e.g., the first memory sub-block 408 of FIG. 4) selected for programming in the block is a selected memory string. A memory sub-block (e.g., the second memory sub-block 418 of FIG. 4) deselected for programming in the block is an unselected memory sub-block . A finger (e.g., the first finger 402 in FIG. 4) that includes the selected memory sub-block is a selected finger. A finger (e.g., the second finger 404 in FIG. 4) that does not include selected memory sub-block is an unselected finger.
[0071] In some implementations, selected DSG in selected finger 702 represents a drain select line (e.g., DSG0 in FIG. 4) coupled to DSG transistor of a selected memory sub-block . Unselected DSG in selected finger 704 represents a drain select line (e.g., DSG1 in FIG. 4) coupled to DSG transistor of an unselected memory sub-block in a selected finger. Unselected finger DSG and unselected finger SSG 706 represents a drain select line (e.g., DSG2 and DSG3 in FIG. 4) coupled to DSG transistors of memory sub-blocks in an unselected finger, and also represents a source select line (e.g., SSG1 in FIG. 4) coupled to SSG transistors of memory in an unselected finger. Selected finger SSG 708 represents a source select line (e.g., SSG0 in FIG. 4) coupled to SSG transistors of memory sub-blocks in a selected finger. Unselected WL 710 represents a word line in the block unselected for programming and verification. Selected WL 712 represents a word line in the block selected for programming and verification.
[0073] During the pre-pulse phase 720, a pass voltage is applied to unselected WL 710, and a verification voltage of the first sense phase 724 is applied to selected WL 712. In addition, a select voltage is applied to selected DSG in selected finger 702, unselected DSG in selected finger 704, and selected finger SSG 708. As such, the respective DSG transistor and SSG transistor of both selected and unselected memory strings in the selected finger are switched on. That is, other than selected memory strings, unselected memory strings in the selected finger are also in on-state. Therefore, it is possible to set the channel potential of the unselected memory sub-blocks in the selected finger to the ground voltage Vss, by coupling the channel of such memory strings to a common source line (e.g., common source line 114 in FIG 1). As such, there may not be a large voltage difference in the channel of the unselected memory string (e.g., between the DSG transistor and a memory cell coupled to the selected word line) during sense phases 724, 726, which can mitigate HCI effect.
[0082] During the pre-pulse phase 820 and a first sense phase 824, a first verification voltage is applied to selected WL 812 to verify whether memory cells in the selected memory string have been programmed to a first programmed state (e.g., P4). During a second sense phase 826, a second verification voltage is applied to selected WL 812 to verify whether memory cells in the selected memory string have been programmed to a second programmed state (e.g., P5). In some implementations, the verification operation 800 may not include the second sense phase 826 , or may include a third sense phase after the second sense phase. For example, referring back to FIG. 6B, the verification operation of the 14th or the 15th loop of the ISPP scheme 620 can include a first sense operation verifying whether memory cells are in P4, and a second sense operation verifying whether memory cells are in P5.
[0086] During the pre-pulse phase 920 and a first sense phase 924, a first verification voltage is applied to selected WL 912 to verify whether memory cells in the selected memory string have been programmed to a first programmed state (e.g., P6). During a second sense phase 926, a second verification voltage is applied to selected WL 912 to verify whether memory cells in the selected memory string have been programmed to a second programmed state (e.g., P7). In some implementations, the verification operation 900 may not include the second sense phase 926 , or may include a third sense phase after the second sense phase. For example, referring back to FIG. 6B, the verification operation of the 19th or the 20th loop of the ISPP scheme 620 can include a first sense operation verifying whether memory cells are in P6, and a second sense operation verifying whether memory cells are in P7.
[0089] FIG. 10 illustrates a flow chart of an example process 1000 for performing a program operation in a memory device, according to some aspects of the present disclosure. Process 1000 can be performed by any suitable device or system as described herein, for example, according to the example techniques described with respect to FIGS. 1-9. For example, process 1000 can be performed by a memory device, such as the memory device 100 of FIGs. 1-5 that includes a memory array 101. The memory array 101 can include one or more blocks 304 that each include one or more fingers (e.g., finger 334 of FIG. 3, fingers 402, 404 of FIG. 4). Each finger can include one or more memory strings (e.g., memory string 310 of FIG. 3, memory string 408, 418 of FIG. 4). A selected memory sub-block (e.g., the first memory sub-block 408 of FIG. 4) includes memory cells that are programmed and verified during the program operation. Memory cells in an unselected memory sub-block (e.g., the second memory sub-block 418 of FIG. 4) are not programmed or verified during the program operation. In some implementations, the memory device can also include peripheral circuits (e.g., peripheral circuits 102 of FIG. 1). The memory device can be a part of a memory system, such as memory system 1102 of FIG. 11. The program operation can be performed based on an ISPP scheme (e.g., ISPP scheme 620 of FIG. 6A) that includes a plurality of loops. Each loop includes a program pulse (e.g., program pulse 630 of FIG. 6A) and one or more verification pulses (e.g., verification pulse 635 of FIG. 6A).
[0091] At 1002, during a first loop of a program operation to program a first memory string (e.g., selected memory string 408 of FIG. 4) including first memory cells (e.g., memory cell 106 of FIG. 1), a first verification operation (e.g., verification operation 700 of FIG. 7) is performed. Performing the first verification operation includes: during a first pre-pulse phase (e.g., pre-pulse phase 720 of FIG. 7) of the first verification operation, applying, for a first duration, a select voltage to a first select line (e.g., drain select line DSG1 of FIG. 4) coupled to a first select gate transistor (e.g., DSG transistor) of a second memory string (e.g., unselected memory string 418 of FIG. 4). The first verification operation can verify whether memory cells in the first memory string have been programmed to a low programmed state (e.g., P1, P2, or P3 of TLCs). In some implementations, the second memory string is included in the same finger as the first memory string.
[0092] At 1004, during a second loop of the program operation, a second verification operation (e.g., verification operation 800 of FIG. 8) is performed. The second loop is after the first loop in the ISPP scheme (e.g., ISPP scheme 620 of FIG. 6A). Performing the second verification operation includes: during a second pre-pulse phase (e.g., pre-pulse phase 820 of FIG. 8) of the second verification operation, applying the select voltage to the first select line for a second duration. The second verification operation can verify whether memory cells in the first memory string have been programmed to a middle programmed state (e.g., P4 or P5 of TLCs). The second duration is shorter than the first duration.
[0093] At 1006, during a third loop of the program operation, a third verification operation (e.g., verification operation 900 of FIG. 9) is performed. The third loop is after the second loop in the ISPP scheme. Performing the third verification operation includes: during a third pre-pulse phase (e.g., pre-pulse phase 920 of FIG. 9) of the third verification operation, applying the select voltage to the first select line for a third duration. The third verification operation can verify whether memory cells in the first memory string have been programmed to a high programmed state (e.g., P6 or P7 of TLCs). The third duration is shorter than the second duration. In some implementations, the third verification operation does not include a pre-pulse phase before one or more sense phases (e.g., sense phases 924, 926 of FIG. 9).
Appropriate correction is required.
Drawings
The drawings are objected to because of the following reasons:
Regarding FIG. 10: Each instance of “pass voltage” should be changed to “select voltage”. See objections to the specification above where it is explained why Examiner believes this to be the case.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding each of claims 1, 14, and 20: The embodiments disclosed do not support the claimed durations of a pass voltage but rather only support the claimed durations of a select voltage. As explained above in the objections to the specification and the drawings, an error was made in the flow diagram of FIG. 10, wherein suddenly “a pass voltage” was used instead of “a select voltage” to refer to the voltage whose duration is changed or varied between pre-pulse phases or verification operations. These two terms have different meanings in the art.
The term “pass voltage” is recognized by one of ordinary skill in the art to be a voltage applied to unselected word lines as seen in FIG. 7, FIG. 8, and FIG. 9 that is higher than any threshold voltage of all the programmed memory cells (memory cell transistors) such that memory cells on the unselected word line becomes conductive no matter which programmed state each of them may be in whereas “a select voltage” is a voltage applied to a transistor, a select gate transistor or a plurality thereof in the case of this application, that is just high enough to turn ON the transistor(s) that used as drain select transistor(s) (see on-state in [0073]). Claims 2-13 depend on claim 1. Claims 15-19 depend on claim 14.
Each of dependent claims 4, 8, 11, 12, 16, and 17 refers to pass voltage and likewise need to be fixed.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 3, 4, 5, 7, 11 -12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 3: Since a single program operation operates only on one memory cell per string as is known in the art and illustrated in FIG. 6A and FIG. 4, and the first cells memory cells are in a single first string like that of 108 in FIG. 1 then it is unknown how a second memory cell of the first memory cells would have a verification operation within the same program operation of the first memory cell of the firs memory cells. This confusion might have to do with the erroneous change from a string to mean 108 in FIG. 1 to mean a plurality of strings 408 in FIG. 4 connected to the same drain select line (known as a sub-block in the art). This problem needs cleared up in the specification and the claims.
Regarding claim 4: It in indefinite as to whet operations “the operations” is to refer to.
Regarding claim 5: Since a single program operation operates only on one memory cell per string as is known in the art and illustrated in FIG. 6A and FIG. 4, and the first cells memory cells are in a single first string like that of 108 in FIG. 1 then it is unknown how a third memory cell of the first memory cells would have a verification operation within the same program operation of the first memory cell and the second memory cell of the first memory cells. This confusion might have to do with the erroneous change from a string to mean 108 in FIG. 1 to mean a plurality of strings 408 in FIG. 4 connected to the same drain select line (known as a sub-block in the art). This problem needs cleared up in the specification and the claims.
Regarding claim 7: It in indefinite as to whet operations “the operations” is to refer to. Since a single program operation operates only on one memory cell per string as is known in the art and illustrated in FIG. 6A and FIG. 4, and the first cells memory cells are in a single first string like that of 108 in FIG. 1 then it is unknown how a third memory cell of the first memory cells would have a verification operation within the same program operation of the first memory cell of the first memory cells. This confusion might have to do with the erroneous change from a string to mean 108 in FIG. 1 to mean a plurality of strings 408 in FIG. 4 connected to the same drain select line (known as a sub-block in the art). This problem needs cleared up in the specification and the claims.
Regarding claims 11: The claim refers to “a pass voltage” but since “a pass voltage” was already introduced in claim 1 then it is indefinite as to whether the reference is to refer to the same pass voltage of claim 1 or to a different new pass voltage.
Regarding claim 12: The claim refers to “a pass voltage” but since “a pass voltage” was already introduced in claim 1 and claim 11 then it is indefinite as to whether the reference is to refer to the same pass voltage of claim 1 or of claim 11 or to a different new pass voltage.
Please address any errors in the claims in referring to what is known to be a sub-block in the art incorrectly as a string. Keep in mind a single program operation is executed on a single word line or row which comprises memory cells in non-selected strings or sub-blocks, wherein program iterations or loops are executed as illustrated in FIG. 6A, and a single verification operation may be executed between the program pulses. Be careful NOT to refer to two program or verification operations as the program or verification operation, respectively.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
2013/0322174: [0053] states “In one approach, the SGD transistors are arranged in SGD subsets such as sub-blocks, where each SGD transistor in a SGD subset is connected to a common SGD control line and therefore receives a common voltage”
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY W RADKE whose telephone number is (571)270-1622. The examiner can normally be reached M-F 9-6 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JAY W. RADKE
Primary Examiner
Art Unit 2827
/JAY W. RADKE/Primary Examiner, Art Unit 2827