DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to 04/29/2026 Amendment.
Claims 1-20 are pending and examined.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 7-9, 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 12,511,073 to Song et al. (hereafter Song) in view of US 11,756,612 to Xu (hereafter Xu) with support from US 7,508,715 to Lee (hereafter Lee).
Regarding independent claim 1, Song teaches a memory device, comprising:
an array of memory cells (FIG. 8: Plane A 32A and Plane B 32b), each memory cell being set to one of 2N final levels corresponding to a piece of N-bits data, where N is an integer greater than 2 (see 3:62-65);
word lines respectively coupled to rows of the memory cells (FIG. 6: select gate lines 24a); and
a peripheral circuit coupled to the array of memory cells through the word lines (see FIG. 8) and configured to:
program, in a first pass, a select row of the rows of the memory cells, such that the memory cells in the selected row are inherently set to k intermediate levels, where k is an integer not greater than 2N (FIGS. 11-12: coarse programming, see 8:28-59. Lee supports, in FIG. 14C, coarse programing of a memory cell from level E to a level 420, wherein number of level 420 is less than number of levels A, B, C);
after the first pass, apply voltage pulses to a select word line of the word lines coupled to the select row of the memory cells, wherein an amplitude of the voltage pulses changes over time (FIG. 12: medium programming); and
after applying the voltage pulses, program, in a second pass, the select row of the memory cells, such that the memory cells in the selected row are inherently set to the 2N final levels (FIG. 12: fine programming, see 8:60-9:15. Lee supports, in FIG. 14C, fine programing of the memory cell to levels A, B and C).
Song teaches voltage pulses instead of single voltage pulse. Song suggests a multi-pass programming architecture comprises coarse and fine programming stages, wherein voltage pulses parameters, such as applied voltages, supplied current, duration, and step up increase(s), in the fine programming stage are less than that of coarse programming stage (see 8:60-9:29). Song further suggests an multi-pass programming architecture can utilize coarse, medium and fine programming stages. Each subsequent block of programming stage having a reduced rate of programming relative to the previous block programing stage (9:51-10:7).
Xu teaches a single-pass programming architecture using dynamic start voltage (DSV) to program multilevel memory cells with fewer program verify operation. The DSV comprises applying a single voltage pulse to a select word line, and programming memory cells coupled to selected word line to respective programming levels from the highest to the lowest, wherein an amplitude of the single voltage pulse changes over time (see FIG. 4B, 3:17-47, 11:57-12:20).
Since Song and Xu are both from the same field of endeavor, the purpose disclosed by Xu would have been recognized in the pertinent art of Song.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to apply the DSV programming method of Xu for the medium programming stage in the multi-pass programming architecture of Song in order to save programming time with fewer program verify operation (see FIGS. 4B-4C and 3:17-47).
Regarding dependent claim 2, Xu teaches wherein the amplitude of the single voltage pulse decreases over time (see FIG. 4B).
Regarding dependent claim 3, Xu teaches wherein at least some of the memory cells in the select row are set to m pre-programmed levels by applying the single voltage pulse, where m is an integer not greater than 2N-k (FIG. 4C: e.g. levels L15-L11 are programmed with single voltage pulse 410).
Regarding dependent claim 4, Xu does not explicitly teach wherein the m pre-programmed levels are determined based on a Gray code for programming the select row of the memory cells. However, it would have been obvious to one with ordinary skill in the art to apply Gray code in programming multilevel memory cells in order to minimizing errors in digital system with only one bit changing between consecutive numerical values.
Regarding dependent claim 7, Xu teaches wherein the amplitude of the single voltage pulse comprises m discrete values each lasting for a respective period (see FIG. 4B).
Regarding dependent claim 8, Xu teaches wherein the single voltage pulse has a pulse width that is divided into m periods, and a first memory cell of the at least some of the memory cells set to a highest level of the m pre-programmed levels is programmed in each of the m periods (FIG. 4B: each of the periods corresponding to one of the levels L15-L1 from the highest to the lowest).
Regarding dependent claim 9, Xu teaches wherein the single voltage pulse has a pulse width that is divided into m periods, and a second memory cell of the at least some of the memory cells set to a lowest level of them pre-programmed levels is programmed in a last one of them periods (FIG. 4B: each of the periods corresponding to one of the levels L15-L1 from the highest to the lowest, wherein L1 is programmed last).
Regarding dependent claim 10, Xu teaches wherein the second memory cell is inhibited in rest of the m periods (because all memory cells except those intended to be programmed to the corresponding level are inhibited, see 12:3-20).
Regarding dependent claim 11, Song teaches wherein the peripheral circuit is configured to program the select row of the memory cells, such that the memory cells in the selected row are set to the 2N final levels, immediately after applying the single voltage pulse without applying a verify voltage to the select word line there between (FIG. 12: middle programming is immediately followed with fine programing).
Regarding independent claim 12, Song teaches a method for operating a memory device comprising rows of memory cells (FIG. 8: Plane A 32A and Plane B 32b), each memory cell being set to one of 2N final levels corresponding to a piece of N-bits data, where N is an integer greater than 2 (see 3:62-65), the method comprising:
programming, in a first pass, a select row of the rows of the memory cells, such that the memory cells in the selected row are set to k intermediate levels, where k is an integer not greater than 2N (FIGS. 11-12: coarse programming, see 8:28-59. Lee supports, in FIG. 14C, coarse programing of a memory cell from level E to a level 420, wherein number of level 420 is less than number of levels A, B, C);
after the first pass, apply voltage pulses to a select word line coupled to the select row of the memory cells, wherein an amplitude of the voltage pulses changes over time (FIG. 12: medium programming); and
after applying the voltage pulses, programming, in a second pass, the select row of the memory cells, such that the memory cells in the selected row are set to the 2N final levels (FIG. 12: fine programming, see 8:60-9:15. Lee supports, in FIG. 14C, fine programing of the memory cell to levels A, B and C).
Song teaches voltage pulses instead of single voltage pulse. Song suggests a multi-pass programming architecture comprises coarse and fine programming stages, wherein voltage pulses parameters, such as applied voltages, supplied current, duration, and step up increase(s), in the fine programming stage are less than that of coarse programming stage (see 8:60-9:29). Song further suggests an multi-pass programming architecture can utilize coarse, medium and fine programming stages. Each subsequent block of programming stage having a reduced rate of programming relative to the previous block programing stage (9:51-10:7).
Xu teaches a single-pass programming architecture using dynamic start voltage (DSV) to program multilevel memory cells with fewer program verify operation. The DSV comprises applying a single voltage pulse to a select word line, and programming memory cells coupled to selected word line to respective programming levels from the highest to the lowest, wherein an amplitude of the single voltage pulse changes over time (see FIG. 4B, 3:17-47, 11:57-12:20).
Since Song and Xu are both from the same field of endeavor, the purpose disclosed by Xu would have been recognized in the pertinent art of Song.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to apply the DSV programming method of Xu for the medium programming stage in the multi-pass programming architecture of Song in order to save programming time with fewer program verify operation (see FIGS. 4B-4C and 3:17-47).
Regarding dependent claims 13-19, see rejections applied to claims 2-4, 7-9 and 11.
Regarding independent claim 20, Song teaches a system, comprising:
a memory device configured to store data, the memory device comprising:
an array of memory cells (FIG. 8: Plane A 32A and Plane B 32b), each memory cell being set to one of 2N final levels corresponding to a piece of N-bits data, where N is an integer greater than 2 (see 3:62-65);
word lines respectively coupled to rows of the memory cells (FIG. 6: select gate lines 24a); and
a peripheral circuit coupled to the array of memory cells through the word lines (FIG. 8: elements 34, 36, 38, 40, 42 and 44) and configured to:
program, in a first pass, a select row of the rows of the memory cells, such that the memory cells in the selected row are set to k intermediate levels, where k is an integer not greater than 2N (FIGS. 11-12: coarse programming, see 8:28-59. Lee supports, in FIG. 14C, coarse programing of a memory cell from level E to a level 420, wherein number of level 420 is less than number of levels A, B, C);
after the first pass, apply voltage pulses to a select word line of the word lines coupled to the select row of the memory cells, wherein an amplitude of the voltage pulses changes over time (FIG. 12: medium programming); and
after applying the voltage pulses, program, in a second pass, the select row of the memory cells, such that the memory cells in the selected row are set to the 2N final levels (FIG. 12: fine programming, see 8:60-9:15. Lee supports, in FIG. 14C, fine programing of the memory cell to levels A, B and C); and
a memory controller coupled to the memory device and configured to control the memory device (FIG. 8: control circuitry 46).
Song teaches voltage pulses instead of single voltage pulse. Song suggests a multi-pass programming architecture comprises coarse and fine programming stages, wherein voltage pulses parameters, such as applied voltages, supplied current, duration, and step up increase(s), in the fine programming stage are less than that of coarse programming stage (see 8:60-9:29). Song further suggests an multi-pass programming architecture can utilize coarse, medium and fine programming stages. Each subsequent block of programming stage having a reduced rate of programming relative to the previous block programing stage (9:51-10:7).
Xu teaches a single-pass programming architecture using dynamic start voltage (DSV) to program multilevel memory cells with fewer program verify operation. The DSV comprises applying a single voltage pulse to a select word line, and programming memory cells coupled to selected word line to respective programming levels from the highest to the lowest, wherein an amplitude of the single voltage pulse changes over time (see FIG. 4B, 3:17-47, 11:57-12:20).
Since Song and Xu are both from the same field of endeavor, the purpose disclosed by Xu would have been recognized in the pertinent art of Song.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to apply the DSV programming method of Xu for the medium programming stage in the multi-pass programming architecture of Song in order to save programming time with fewer program verify operation (see FIGS. 4B-4C and 3:17-47).
Allowable Subject Matter
Claims 5-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to dependent claim 5: wherein N equals 4, k equals 4, and the m pre-programmed levels comprise P6, P7, P8, P9, P10, P11, and P14.
With respect to dependent claim 6: wherein N equals 4, k equals 9, and the m pre-programmed levels comprise P3, P4, P6, P7, P9, P11, and P13.
Response to Arguments
Applicant's arguments filed 04/29/2026 have been fully considered but they are not persuasive.
Applicant argues that:
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The Examiner respectfully disagrees with these arguments. Song appears to disclose different programming stages that inherently possess different intermediate program levels. Because the single-pass programming architecture of Xu applies the DSV programming method for final program levels, there is no apparent reason why Song cannot similarly use the DSV programming method for intermediate program levels during its medium programming stage.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VANTHU NGUYEN whose telephone number is (571)272-1881. The examiner can normally be reached M-F: 7:00AM - 3:00PM.
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June 7, 2026
/VANTHU T NGUYEN/Primary Examiner, Art Unit 2824
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