DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I in the reply filed on August 10, 2026, is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “lightly-doped” in claim 7 is a relative term which renders the claim indefinite. The term “lightly-doped” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention.
The term is known in the art. However, the ranges used would be dependent on those who use it and can have overlap with moderate doping levels for other manufacturers, which would cause confusion.
Claim 8 is also rejected because it is dependent on claim 7.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 and 6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et. al. (US 20220102358 A1), hereinafter Park.
Regarding claim 1, Park teaches a memory device (Fig 1 unlabeled/unshown 3D semiconductor memory device, [0026]), comprising: a plurality of silicon cantilever structures (Fig 8 semiconductor pattern SP, [00789) arranged vertically (Fig 8 D3 direction); and a storage cell (Fig 8 storage element DS, [0074]) on an end of each of (Fig 8) the plurality of silicon cantilever structures (Fig 8 semiconductor pattern SP, [00789), each storage cell (Fig 8 storage element DS, [0074]) comprising: a first capacitor structure (See annotated figure) connected to a topside surface (Fig 8) of a corresponding silicon cantilever structure (Fig 8 semiconductor pattern SP, [00789) and comprising: a first plurality of high-K dielectric layer portions (Fig 8 dielectric layer DL in first capacitor structure, [0138]) that are vertically- arranged (Fig 8) and interspersed with (Fig 8) a first plurality of electrode layer portions (Fig 8 electrodes EL1 and EL2 for first capacitor structure, [0138]), wherein each of the first plurality of high-K dielectric layer portions (Fig 8 dielectric layer DL in first capacitor structure, [0138]) is approximately parallel to the topside surface (Fig 8); and a second capacitor structure (See annotated figure) connected to an underside surface (Fig 8) of the corresponding silicon cantilever structure (Fig 8 semiconductor pattern SP, [00789) and comprising: a second plurality of high-K dielectric layer portions (Fig 8 dielectric layer DL in second capacitor structure, [0138]) that are vertically-arranged and interspersed with (Fig 8) a second plurality of electrode layer portions (Fig 8 electrodes EL1 and EL2 for second capacitor structure, [0138]), wherein each of the second plurality of high-K dielectric layer portions (Fig 8 dielectric layer DL in second capacitor structure, [0138]) is approximately parallel to the underside surface (Fig 8).
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Regarding claim 2, Park teaches an inter-tier dielectric layer portion (Fig 8 insulating layers ILD, [0075]) between vertically adjacent storage cells (Fig 8 storage element DS, [0074]) wherein the inter-tier dielectric layer portion (Fig 8 insulating layers ILD, [0075]) is between co-facing bottom electrode layer portions (See annotated figure) of the vertically adjacent storage cells (Fig 8 storage element DS, [0074]).
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Regarding claim 3, Park teaches the first plurality of electrode layer portions (Fig 8 electrodes EL1 and EL2 for first capacitor structure, [0138]) and the second plurality of electrode layer portions (Fig 8 electrodes EL1 and EL2 for second capacitor structure, [0138]) each comprise: a quantity of two bottom electrode layer portions (See annotated figure).
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Regarding claim 4, Park teaches the first plurality of high-K dielectric layer portions (Fig 8 dielectric layer DL in first capacitor structure, [0138]) essentially comprises: a quantity of two high-K dielectric layer portions (See annotated figure), and wherein the second plurality of electrode layer portions (Fig 8 electrodes EL1 and EL2 for second capacitor structure, [0138]) essentially comprises: a quantity of one top electrode layer portion (See annotated figure), and a quantity of two bottom electrode layer portions (See annotated figure).
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Regarding claim 6, Park teaches a transistor gate structure (Figs 4 and 8 gate electrode GE, [0052]) for each of the plurality of silicon cantilever structures (Fig 8 semiconductor pattern SP, [00789) arranged vertically (Fig 8), wherein each transistor gate structure (Figs 4 and 8 gate electrode GE, [0052]) is wrapped around (Fig 4, [0054]) a corresponding silicon cantilever structure (Fig 8 semiconductor pattern SP, [00789).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Park et. al. (US 20220102358 A1), hereinafter Park.
Park teaches the first plurality of high-K dielectric layer portions (Fig 8 dielectric layer DL in first capacitor structure, [0138]) essentially comprises: a quantity of three high-K dielectric layer portions (See annotated figure; Park teaches the dielectric layer may be a stacked structure; this would allow for more than two layers for every portion), and wherein the second plurality of electrode layer portions (Fig 8 electrodes EL1 and EL2 for second capacitor structure, [0138]) essentially comprises: a quantity of two top electrode layer portions (See annotated figure; larger portion and smaller portion), and a quantity of two bottom electrode layer portions (See annotated figure).
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Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Park et. al. (US 20220102358 A1), hereinafter Park, in view of Sun et. al. (CN 114759030 A), hereinafter Sun.
Regarding claim 7, Park teaches each silicon cantilever structure (Fig 8 semiconductor pattern SP, [00789) of the plurality of silicon cantilever structures (Fig 8 semiconductor pattern SP, [00789) comprises: a dopant (Fig 4 impurity region SD2, [0039]; the impurity region is connected to the storage element, [0039]) between the first capacitor structure (See annotated figure of claim 1) and the second capacitor structure (See annotated figure of claim 1).
Park fails to teach the dopant forms a cell contact lightly-doped drain region within the silicon cantilever structure between the first capacitor structure and the second capacitor structure.
However, Sun teaches having a lightly-doped drain region to improve the hot carrier effect of the transistor in the memory device ([n0114]). One having ordinary skill in the art before the effective filing date of the claimed invention would be motivated to have modified Park to incorporate the teachings of Sun by having the dopant being lightly doped to improve the hot carrier effect and that there would have been a reasonable expectation of success. MPEP 2143 (I)(G)
In doing so, the dopant forms a cell contact lightly-doped drain region (Sun, [n0114]) within the silicon cantilever structure (Fig 8 semiconductor pattern SP, [00789) between the first capacitor structure (See annotated figure of claim 1) and the second capacitor structure (See annotated figure of claim 1).
Regarding claim 8, Park as modified in claim 7 teaches for each silicon cantilever structure (Fig 8 semiconductor pattern SP, [00789) of the plurality of silicon cantilever structures (Fig 8 semiconductor pattern SP, [00789): a first liner structure (Fig 8 spacer pattern SPC2 above semiconductor pattern SP, [0114]) above the silicon cantilever structure (Fig 8 semiconductor pattern SP, [00789), and a second liner structure (Fig 8 spacer pattern SPC2 below semiconductor pattern SP, [0114]) below the silicon cantilever structure (Fig 8 semiconductor pattern SP, [00789) and below the first liner structure (Fig 8 spacer pattern SPC2 above semiconductor pattern SP, [0114]) wherein the first liner structure (Fig 8 spacer pattern SPC2 above semiconductor pattern SP, [0114]) and the second liner structure (Fig 8 spacer pattern SPC2 below semiconductor pattern SP, [0114]) have substantially similar widths (Fig 8 the spacer patterns in the D2 direction appear to have substantially similar widths).
Conclusion
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALVIN L LEE whose telephone number is (703)756-1921. The examiner can normally be reached Monday - Friday 8:30 am - 5 pm (ET).
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/ALVIN L LEE/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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