DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to independent claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Allowable Subject Matter
Claim 4-6, 12, and 15-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and all 35 USC § 112 rejections are overcome.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 7-10, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Balakrishnan (US 2024/0220379 A1), and further in view of Wikipedia “register renaming” page from date 12/16/2023, retrieved using the WayBackMachine, hereafter referred to as WBM121623waw.
For claim 1,
Balakrishnan teaches an apparatus comprising: a first register; a second register; and at least one controller configured to: update data from a source page in the first register based on error correction of the data; and [] (see abstract, paragraphs [0027], [0014], [0044], and other locations view memory controller as said controller; controller accesses memory made of pages, using page table; memory controller uses error registers and ECS to scrub; scrubbing means correcting error in memory, correcting errors means updating; error register(s) are counting the errors encountered while scrubbing; Balakrishnan also teaches CPU).
Balakrishnan does not explicitly teach “update data in the second register based a write that occurs to the source page during the error correction”
However, WBM121623waw teaches update data in the second register based a write that occurs to the source page during the error correction (see WAW section: WAW is used during error correction: if an error is caught while an instruction is modifying a register, the register is updated based on the last write in the program order)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Balakrishnan to include “update data in the second register based a write that occurs to the source page during the error correction”, as taught by WBM121623waw, because each one of Balakrishnan and WBM121623waw teach a general-purpose CPU and memory therefore they are analogous arts and because in processors, register are typically updated during error correction (see WAW section).
For claim 2,
The combination of Balakrishnan and WBM121623waw teaches the limitations of claim 1 for the reasons above.
Balakrishnan further teaches error correction circuitry, wherein the error correction is performed by the error correction circuitry (see [0027] and other locations: ECC circuit).
For claim 7,
The combination of Balakrishnan and WBM121623waw teaches the limitations of claim 1 for the reasons above.
Balakrishnan further teaches a first data path used in read and write operations for a plurality of banks (see figure 1, [0032], [0023-0025], and other locations: buses are data paths), and a second data path configured to connect the first register to error correction circuitry (see [0044] and other locations: memory controller, data flows from ECC to error registers), wherein a bandwidth of the second data path is less than a bandwidth of the first data path (bus has smaller/bit width than ECC).
For claim 8,
The combination of Balakrishnan and WBM121623waw teaches the limitations of claim 1 for the reasons above.
Balakrishnan further teaches the source page is in a wear-leveling pool; the apparatus further comprises error correction circuitry configured to provide a signal; and movement of data in the wear-leveling pool is modified based on the signal (see [0003] and other locations: replacing memory rows after too many errors (wear) is from a pool/spare; threshold passing is the signal).
For claim 9,
The combination of Balakrishnan and WBM121623waw teaches the limitations of claim 1 for the reasons above.
Balakrishnan further teaches the source page is in a wear-leveling pool; and the apparatus further comprises first error correction circuitry configured to service read and write operations in response to commands from a host device, and second error correction circuitry configured to service scrub operations during wear-leveling for the pool (see [0002-0024], [0049], and other locations: host can operate in multiple modes, all use error correction; different modes means different circuits).
For claim 10,
The combination of Balakrishnan and WBM121623waw teaches the limitations of claim 1 for the reasons above.
Balakrishnan further teaches the at least one controller is further configured to transfer code words from the first register to an error correction code (ECC) engine for scrubbing, and transfer scrubbed code words from the ECC engine to the first register (see rejection to claim 1: replace designation of first and second register; view now the MDR in which all data goes through as said first register and the other register as said second register).
For claims 18 and 20,
The claims recite essentially similar limitations from claim 1. Claims 18 and 20 are a method.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 11 and 13-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Curley (US 2015/0318058 A1).
For claim 11, Curley teaches an apparatus comprising: at least one memory array; and at least one controller configured to: perform read and write operations for first data in the memory array (see figure 2, paragraphs [0017], and other locations: RAID controller system includes said) using error correction; and scrub second data in the memory array during the read and write operations (see [0002], [0042-0043], [0064], and other locations: scrubbing is done in the background and concurrently),wherein the read and write operations use first error correction circuitry (scrubing always uses read write and error correction circuitry)
For claim 13, Curley teaches the limitations of claim 11 for the reasons above and further teaches the memory array is configured in a volatile memory device, and the second data is scrubbed as part of an error check and scrub (ECS) operation (see [0002-0003], and other locations).
For claim 14, Curley teaches the limitations of claim 11 for the reasons above and further teaches determine that the first data is targeted for writing to a first page, and the second data is stored in the first page when the scrubbing is performed; temporarily store the first data; and after the scrubbing is complete, move the first data to the first page or a second page in the memory array (see [0036-0037], and other locations: view buffers as said temporary memory).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YAIR LEIBOVICH whose telephone number is (571)270-3796. The examiner can normally be reached 8:00am-5:00pm.
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/YAIR LEIBOVICH/Primary Examiner, Art Unit 2114
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