DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 11/4/2025, with respect to allowability of claims 1-10, have been fully considered but they are not persuasive: Applicant amended claim 1 by deleting the “move data from a source page to the first and second registers” limitations. This changes the scope of the claim, as explained in the new antecedent basis rejection and the new art rejection below, and the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument
Applicant's arguments filed 11/4/2025, with respect to claims 11-17, have been fully considered but they are not persuasive:
Applicant essentially argues that “Curley does not teach or suggest read and write operations and scrubbing being performed at the same time” because paragraph [0042] recites that memory scrub engine processes memory addresses in a sequential manner through an entire memory rank, which is not scrubbing data during read and write, as claimed. Also, Applicant essentially argues that Paragraph [0043] describes that a single store writes to an address in a rank sometime before the memory scrub engine starts scrubbing the rank. Thus, the write operation is before (not during) scrubbing. Applicant stated that [0002] [0017], and [0064] do not remedy the above deficiencies.
Applicant’s argument is not persuasive because (i)the sequential processing of memory addresses occur within one rank scrubbing; same paragraph recites that te scrub operation is performed in the background, and on multiple memory ranks. This means that during regular operations (memory read/write), additional operations (scrub) are performed in the background. Both regular and background operations involve read/write; (ii) a single store write to an address in a rank sometime before the memory scrub, does not mean that scrubs do not continue to occur in the background, i.e., during; (iii) paragraphs [0002] [0017] specify the different hardware circuits in different locations in the system, that enable them to operate in parallel, which allows them to execute concurrently; paragraph [0064] explicitly recites that operations in different blocks can operate concurrently (i.e. during).
For claims 18-20, applicant amended claim 18, resulting in new grounds of rejection.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-10 and 20 are rejected under 35 U.S.C. 112(b), as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, regards as the invention.
For claims 1 and 4, the term “the data in the second register” lacks sufficient antecedent basis in the claim. Applicant deleted the limitation that moves data into the second register. Thus, the data in the second register cannot be the data in the first register, either before or after the error correction because it was not moved there. The claim is now interpreted such that the second register has a separate functionality”.
For claim 20, the term “the data” is unclear and thus indefinite because first and second data were declared earlier, and so it is unclear to which the claim refers to.
Dependent claims inherit rejections.
Allowable Subject Matter
Claim 4-6 and 15-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and all 35 USC § 112 rejections are overcome.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 7-10, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Balakrishnan (US 2024/0220379 A1), and further in view of Wikipedia “Memory address register” page from date 2/13/2024, retrieved using the WayBackMachine, hereafter referred to as WBM021324mar.
For claim 1,
Balakrishnan teaches an apparatus comprising: a first register; a second register; and at least one controller configured to: update data from a source page in the first register based on error correction of the data; and [] (see abstract, paragraphs [0027], [0014], [0044], and other locations view memory controller as said controller; controller accesses memory made of pages, using page table; memory controller uses error registers and ECS to scrub; scrubbing means correcting error in memory, correcting errors means updating; error register(s) are counting the errors encountered while scrubbing; Balakrishnan also teaches CPU).
Balakrishnan does not explicitly teach “update the data in the second register based on a write that occurs to the source page”
However, WBM021324mar teaches update the data in the second register based a write that occurs to the source page (see 2nd paragraph: view MDR as said second register, which is updated every write to memory; every CPU has MAR and MDR, as basic building blocks)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Balakrishnan to include “update the data in the second register based on a write that occurs to the source page”, as taught by WBM021324mar, because each one of Balakrishnan and WBM021324mar teach a general-purpose CPU and memory therefore they are analogous arts and because every CPU includes such register as a basic building block (see 2nd paragraph).
For claim 2,
The combination of Balakrishnan and WBM021324mar teaches the limitations of claim 1 for the reasons above.
Balakrishnan further teaches error correction circuitry, wherein the error correction is performed by the error correction circuitry (see [0027] and other locations: ECC circuit).
For claim 3,
The combination of Balakrishnan and WBM021324mar teaches the limitations of claim 1 for the reasons above.
Balakrishnan further teaches the write occurs during the error correction (see locations pointed to above and figures 1-2: CPU and memory controller work in parallel).
For claim 7,
The combination of Balakrishnan and WBM021324mar teaches the limitations of claim 1 for the reasons above.
Balakrishnan further teaches a first data path used in read and write operations for a plurality of banks (see figure 1, [0032], [0023-0025], and other locations: buses are data paths), and a second data path configured to connect the first register to error correction circuitry (see [0044] and other locations: memory controller, data flows from ECC to error registers), wherein a bandwidth of the second data path is less than a bandwidth of the first data path (bus has smaller/bit width than ECC).
For claim 8,
The combination of Balakrishnan and WBM021324mar teaches the limitations of claim 1 for the reasons above.
Balakrishnan further teaches the source page is in a wear-leveling pool; the apparatus further comprises error correction circuitry configured to provide a signal; and movement of data in the wear-leveling pool is modified based on the signal (see [0003] and other locations: replacing memory rows after too many errors (wear) is from a pool/spare; threshold passing is the signal).
For claim 9,
The combination of Balakrishnan and WBM021324mar teaches the limitations of claim 1 for the reasons above.
Balakrishnan further teaches the source page is in a wear-leveling pool; and the apparatus further comprises first error correction circuitry configured to service read and write operations in response to commands from a host device, and second error correction circuitry configured to service scrub operations during wear-leveling for the pool (see [0002-0024], [0049], and other locations: host can operate in multiple modes, all use error correction; different modes means different circuits).
For claim 10,
The combination of Balakrishnan and WBM021324mar teaches the limitations of claim 1 for the reasons above.
Balakrishnan further teaches the at least one controller is further configured to transfer code words from the first register to an error correction code (ECC) engine for scrubbing, and transfer scrubbed code words from the ECC engine to the first register (see rejection to claim 1: replace designation of first and second register; view now the MDR in which all data goes through as said first register and the other register as said second register).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 11-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Curley (US 2015/0318058 A1).
For claim 11, Curley teaches an apparatus comprising: at least one memory array; and at least one controller configured to: perform read and write operations for first data in the memory array (see figure 2, paragraphs [0017], and other locations: RAID controller system includes said) using error correction; and scrub second data in the memory array during the read and write operations (see [0002], [0042-0043], [0064], and other locations: scrubbing is done in the background and concurrently).
For claim 12, Curley teaches the limitations of claim 11 for the reasons above and further teaches the read and write operations use first error correction circuitry, and the scrubbing uses second error correction circuitry (see [0002], [0016], and other locations).
For claim 13, Curley teaches the limitations of claim 11 for the reasons above and further teaches the memory array is configured in a volatile memory device, and the second data is scrubbed as part of an error check and scrub (ECS) operation (see [0002-0003], and other locations).
For claim 14, Curley teaches the limitations of claim 11 for the reasons above and further teaches determine that the first data is targeted for writing to a first page, and the second data is stored in the first page when the scrubbing is performed; temporarily store the first data; and after the scrubbing is complete, move the first data to the first page or a second page in the memory array (see [0036-0037], and other locations: view buffers as said temporary memory).
Claims 18-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Balakrishnan (US 2024/0220379 A1).
For claim 18, Balakrishnan teaches a method comprising: scrubbing first data for a source page of a memory array (see [0027], [0036], [0038], and other locations: system working with pages and also contains a scrubber; view bank as said array); and performing an operation to write second data to the source page during the scrubbing (see [0044] and other locations: view scrubbing occurs in the background as said during).
For claim 19, Balakrishnan teaches the limitations of claim 18 for the reasons above and further teaches the second data being written is stored at a temporary storage location during the scrubbing (see [0052] and other locations: view buffer for temporary in case of migration as said).
For claim 20, Balakrishnan teaches the limitations of claim 19 for the reasons above and further teaches the second data is written from the temporary storage location to a target page (see locations pointed to above: memory organized in pages and so from temp to regular memory page) after the data is scrubbed (see locations pointed to above: scrubbing occurs in the background and so the two operation types are not synchronized and occur before/after/during).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Google AI search query showing that every general-purpose processor in 2015 addressed memory organized in pages.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/YAIR LEIBOVICH/Primary Examiner, Art Unit 2114