Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-10 and 18-27 were previously examined.
Claims 1-10 and 18-27 are pending in this action.
Response to Arguments
Applicant's arguments for claims 1-17 and 21-27 filed on March 17, 2026 have been fully considered but they are not persuasive.
Applicant’s arguments:
On page 1 of the remark, Applicant the explained that Figure 5, O'Connell describes access of a DRAM memory. Paragraph 37 of O'Connell describes that an ECC engine monitors for an error. Paragraph 39 of O'Connell describes that if the ECC engine flags an error, the failed address location is compared to list of previously failed addresses. This list includes soft error addresses. Based on this comparison, O'Connell describes various actions that can be taken. These actions include queuing hard error repair, or determining there is an un-repairable hard error.
Then Applicant came to conclusion that the prior art of record do not disclose “in particular, claim 1 recites detecting whether an error exists. In response to detecting a first error for a first portion of a memory array, a first location of the first portion is recorded”.
In Responses:
Examiner disagreed with Applicant’s conclusion “detecting whether an error exists. In response to detecting a first error for a first portion of a memory array, a first location of the first portion is recorded” as recited in claim 1.
Claim 1 recites a limitation “to detect whether an error exists in data stored in each of access portion. However, it does not recite a method of detecting a first error in a first portion at all. Therefore, claim 1 cannot detect a first error for a first portion. Thus, claim 1 cannot perform “In response to detecting a first error for a first portion of a memory array, a first location of the first portion is recorded” because it does not detect a first error.
As such, the prior arts of O’Connell discloses the requirement of claim 1.
In Responses:
Examiner disagreed.
O’Connell in figure 5 discloses (1) at step 520 a method detecting whether an error exists in the data where a portion is accessed in the eDRAM, (2) at step 540 when the error exists in the accessed portion is YES then (3) stored the address in the list. The accessed portion of O’Connell is the first portion because it is the first portion that being detected.
(O’Connell, [0039] clearly discloses of method of “capturing (which is means to store) the failed address of failed location and [0040] also to store this failed address location in the stored list of SER address)
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As such, the rejection is maintained.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 18-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
In analyzing under step 1, is the claim to a process, machine manufacture or composition of matter? Yes.
In analyzing under step 2A Prong One, Does the claim recite an abstract idea law of nature or natural phenomenon? Yes.
The claim(s) 18-20 recite(s) the abstract limitations such as “in response to receiving an activate command, sensing a first page of data and a parity stored in the first page; computing a first parity for the first page; and comparing the first parity to the stored parity” is a process that, under its broadest reasonable interpretation, covers performance of the limitation under mathematical/and or mental processes .
If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation under mathematical or mental processes but for the recitation of generic computer components and software module, then it falls within the “Mathematical Processes” and/or “Mental Process” grouping of abstract ideas.
The generic processes or a mental process can respond to an active command then (1) read (or sensing) first data and parity from the first page of the memory, then (2) computing a first parity using first data (based on mathematical calculation) and comparing the computed first parity with the previous stored parity (based on mathematical calculation). The recited claim 18 does not improve the method at all.
Dependent claim 19 only add an address to a scrub queue but does not perform any scrubbing at all. As such it does not improve the method at all.
Dependent claim 20 recite a method of computing second parity (based on mathematical calculation) and writing the data and parity in some memory. As such it does not improve the method or system at all.
Accordingly, the claims 18-20 recite an abstract limitation.
In analyzing under step 2A Prong Two, Does the claim recite additional elements that integrate the judicial exception into a practical application? NO.
This judicial exception is not integrated into a practical application because the claims recite a generic processor for calculating and comparing parity. The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because a generic processor and software module which are high level of generality performing code generation. Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea.
In analyzing under step 2B, does the claim recite additional elements that amount to significantly more than the judicial exception? NO
Claims 18-20 do not recite any additional elements for calculating and comparing parity. Accordingly, the additional generic elements do not amount to significantly more than the judicial exception because a generic processor and software module which are high level of generality calculating parity and comparing parity
The claim is directed to an abstract idea.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 and 18-27 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Any claim not specifically mentioned, is rejected due to its dependency on a rejected claim.
Claims 1 and 21 recite the limitation "a first error". There is insufficient antecedent basis for this limitation in the claim. The previous limitation does not mention a first data. As such, it is unclear where the first error.
Claims 1 and 21 recite the limitation "a first portion". There is insufficient antecedent basis for this limitation in the claim. The previous limitation does not mention a first portion. As such, it is unclear where the first portion.
Claims 1 and 21 recite the limitation "a first location". There is insufficient antecedent basis for this limitation in the claim. The previous limitation does not mention a first location. As such, it is unclear where the first location.
Claims 1 and 21 recite a limitation such as “in response to detecting a first error for a first portion, record a first location of the first portion”
The recited limitation such as “in response to detecting a first error for a first portion, record a first location of the first portion” renders this limitation indefinite because the previous limitation does not perform any detection on “a first error for a first portion” at all. As such, it is unclear how it can response when detecting a first error at all. When or where does it detect first error in a first portion?
The recited condition limitation such as “in response to detecting a first error for a first portion, record a first location of the first portion” renders this limitation indefinite because it is unclear what happens when it does not detecting a first error for a first portion. It is unclear whether any record is performed.
Claims 2 and 22 recite the limitation "the controller". There is insufficient antecedent basis for this limitation in the claim. The previous claim 1 and 21 recite “at least one controller” and not “a controller”. As such, it is unclear which controller is referring to.
Claim 18 recites the limitation " in response to receiving an activate command".
The recited limitation such as “in response to receiving an activate command" renders this limitation indefinite because it is unclear what happens when NOT receiving an active command. It is unclear whether method of “sensing a first page …and a parity…” are performed when “NOT receiving an active command”. It is unclear whether any computing a first parity and comparing the first parity are even performed for a condition “Not receiving an active command”
There is insufficient antecedent basis for this limitation in the claim. The previous limitation recites “sensing a parity stored”
Claim 18 recites the limitation "the stored parity". There is insufficient antecedent basis for this limitation in the claim. The previous limitation recites “sensing a parity stored”. It does not recite “sensing a stored parity”
Claim 19 recite the limitation "a physical address of the first page". There is insufficient antecedent basis for this limitation in the claim. The previous limitation does not recite any “a physical address of the first page”
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 6-7, 9-10, 21-22, 24-27 is/are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by O’Connell (US 2011/0,041,016)
As per claim 1:
O’Connell discloses:
An apparatus comprising:
(O’Connell, Fig. 1, System 100, ECC Engine 120-1-3, eDRAM 120-1-2, Failed Address Engineer 120-2-2)
error detection circuitry; and at least one controller configured to:
(O’Connell, Fig. 1, System 100, ECC Engine 120-1-3, eDRAM 120-1-2, Failed Address Engineer 120-2-2)
access portions of a memory array;
(O’Connell, Fig. 5, Access to eDRAM 120-1-1 (510), ECC error has been flagged? (520), Store the flagged address to the list of SER address (560))
detect, using the error detection circuitry,
(O’Connell, Fig. 5, Access to eDRAM 120-1-1 (510), ECC error has been flagged? (520), Store the flagged address to the list of SER address (560))
(O’Connell, Fig. 5, Access to eDRAM 120-1-1 (510), ECC error has been flagged? (520) == YES, Store the flagged address to the list of SER address (560))
(O’Connell, [0038] In block 520, failed address engine 120-2-2 determines if ECC engine 120-1-3 has flagged an error. If ECC engine 120-1-3 has not flagged an error, failed address engine 120-2-2 100 in block 530 functions as usual, and system 100 continues to operate normally)
whether an error exists in data stored in each accessed portion; and
(O’Connell, Fig. 5, Access to eDRAM 120-1-1 (510), ECC error has been flagged? (520) == YES, Store the flagged address to the list of SER address (560))
(O’Connell, [0038] In block 520, failed address engine 120-2-2 determines if ECC engine 120-1-3 has flagged an error. If ECC engine 120-1-3 has not flagged an error, failed address engine 120-2-2 100 in block 530 functions as usual, and system 100 continues to operate normally)
in response to detecting a first error for a first portion, record a first location of the first portion.
(O’Connell, Fig. 5, Access to eDRAM 120-1-1 (510), ECC error has been flagged? (520) == YES, Store the flagged address to the list of SER address (560))
(O’Connell, [0039] If, however, ECC engine 120-1-3 has flagged an error, and therefore captured the failed address of failed location 240-5, failed address engine 120-2-2 in block 540, receiving the failed address location 240-5 from ECC engine 120-1, compares the failed address location 240-5 to a list of previously failed addresses, which in effect, includes the list of soft error (e.g., SER) addresses)
(O’Connell, [0040] If there is not a match (e.g., the failed address location 240-5 is not in the stored list of SER addresses), failed address engine 120-2-2, recognizing this is a new failure location, considers the error as a soft error, and, in block 560, stores this failed address location 240-5 in the stored list of SER addresses)
As per claim 2:
O’Connell further discloses:
further comprising error correction circuitry, wherein the controller is further configured to correct the detected first error using the error correction circuitry.
(O’Connell, Fig. 5, Correct SER failure (570))
(O’Connell, [0041] Failed address engine 120-2-2 in block 570 corrects the SER failure)
As per claim 3:
O’Connell further discloses:
wherein a number of bit errors that can be corrected by the error correction circuitry is greater than or equal to a number of bit errors that can be detected by the error detection circuitry.
(O’Connell, Fig. 5, Correct SER failure (570))
(O’Connell, [0041] Failed address engine 120-2-2 in block 570 corrects the SER failure)
(O’Connell, Fig. 5, Correct the redundant location (595))
(O’Connell [0045] … once the redundant row 210, the redundant word 210-1, or the redundant column 410, has been identified, the redundant location 210-5 does not necessarily include the correct data. Failed address engine 120-2-2 in block 595 corrects the data in redundant location 210-5. Depending on applications, redundancy engine 120-1-2 queues for an overwrite of the redundant location 210-5 or redundancy engine 120-1-2 overwrites the data in redundant location 210-5 as appropriate. In the case of column swapping in FIG. 400, redundancy engine 120-1-2 overwrites all cells in redundant column 410. Alternatively, redundancy engine 120-1-2 uses the corrected data and the address of failed location 240-5 provided by ECC engine 120-1-3 to flip the logic state of the data in redundant location 210-5.
(O’Connell [0046] Once redundant location 210-5 is written with the corrected data, i.e., the error has been completely repaired, failed address engine 120-2-2 in block 598 tags the failed location 240-5 as completely repaired)
As per claim 4:
O’Connell further discloses:
the controller is further configured to perform memory management for a memory device that includes the memory array; and the memory management includes correcting the first error using the error correction circuitry.
(O’Connell, Fig. 5, Correct SER failure (570))
(O’Connell, [0041] Failed address engine 120-2-2 in block 570 corrects the SER failure)
(O’Connell, Fig. 5, Correct the redundant location (595))
(O’Connell [0045] … once the redundant row 210, the redundant word 210-1, or the redundant column 410, has been identified, the redundant location 210-5 does not necessarily include the correct data. Failed address engine 120-2-2 in block 595 corrects the data in redundant location 210-5. Depending on applications, redundancy engine 120-1-2 queues for an overwrite of the redundant location 210-5 or redundancy engine 120-1-2 overwrites the data in redundant location 210-5 as appropriate. In the case of column swapping in FIG. 400, redundancy engine 120-1-2 overwrites all cells in redundant column 410. Alternatively, redundancy engine 120-1-2 uses the corrected data and the address of failed location 240-5 provided by ECC engine 120-1-3 to flip the logic state of the data in redundant location 210-5.
(O’Connell [0046] Once redundant location 210-5 is written with the corrected data, i.e., the error has been completely repaired, failed address engine 120-2-2 in block 598 tags the failed location 240-5 as completely repaired)
As per claim 6:
O’Connell further discloses:
wherein the error detection circuitry is configured to determine a parity for the data stored in each accessed portion.
(O’Connell, Abstract< Redundancy including extra rows and/or columns of memory cells is added to the memory, and ECC parity is used to detect errors. When an error occurs at a location the first time, it is assumed to be a soft error, the data is corrected in this location, and the address of the erroneous cell (e.g., the failed address) is stored in a list))
(O’Connell, [0020], Generally, when an error occurs in eDRAM 120-1-1, ECC engine 120-1-3, based on the data and associated parity bits, recognizes an error arises, identifies the address of the failed bit, and flags that error. In an embodiment, ECC engine 120-1-3 uses six parity bits to correct a single error in a data word of 32 bits and seven parity bits to correct a single error and detect a double error)
As per claim 7:
O’Connell further discloses:
wherein the first portion is a row of the memory array, the row stores a first parity of data written to the row, and the first parity is compared to a second parity determined by the error detection circuitry when data is read from the row.
(O’Connell, Abstract< Redundancy including extra rows and/or columns of memory cells is added to the memory, and ECC parity is used to detect errors. When an error occurs at a location the first time, it is assumed to be a soft error, the data is corrected in this location, and the address of the erroneous cell (e.g., the failed address) is stored in a list))
(O’Connell, [0020], Generally, when an error occurs in eDRAM 120-1-1, ECC engine 120-1-3, based on the data and associated parity bits, recognizes an error arises, identifies the address of the failed bit, and flags that error. In an embodiment, ECC engine 120-1-3 uses six parity bits to correct a single error in a data word of 32 bits and seven parity bits to correct a single error and detect a double error)
As per claim 9:
O’Connell further discloses:
wherein the accessed portions are pages storing code words, and each page stores a parity determined using the code words stored in the page.
(O’Connell, Abstract< Redundancy including extra rows and/or columns of memory cells is added to the memory, and ECC parity is used to detect errors. When an error occurs at a location the first time, it is assumed to be a soft error, the data is corrected in this location, and the address of the erroneous cell (e.g., the failed address) is stored in a list))
(O’Connell, [0020], Generally, when an error occurs in eDRAM 120-1-1, ECC engine 120-1-3, based on the data and associated parity bits, recognizes an error arises, identifies the address of the failed bit, and flags that error. In an embodiment, ECC engine 120-1-3 uses six parity bits to correct a single error in a data word of 32 bits and seven parity bits to correct a single error and detect a double error)
As per claim 10:
O’Connell further discloses:
wherein the first error is detected by comparing a parity stored with code words in a first page to a parity computed for the code words when the first page is activated.
(O’Connell, Abstract< Redundancy including extra rows and/or columns of memory cells is added to the memory, and ECC parity is used to detect errors. When an error occurs at a location the first time, it is assumed to be a soft error, the data is corrected in this location, and the address of the erroneous cell (e.g., the failed address) is stored in a list))
(O’Connell, [0020], Generally, when an error occurs in eDRAM 120-1-1, ECC engine 120-1-3, based on the data and associated parity bits, recognizes an error arises, identifies the address of the failed bit, and flags that error. In an embodiment, ECC engine 120-1-3 uses six parity bits to correct a single error in a data word of 32 bits and seven parity bits to correct a single error and detect a double error)
(O’Connell, [0034] FIG. 4 shows an eDRAM 400 as a third embodiment of eDRAM 120-1-1. eDRAM 400, as compared to eDRAM 200 or 300, includes a plurality of redundant cells and associated circuitry such as bit lines, sense amplifiers, etc., used to repair an error on a bit line and/or bit-line sense amplifier area)
As per claims 11-17: Cancelled)
As per claim 21:
O’Connell discloses:
An apparatus comprising: a memory array; and at least one controller configured to:
(O’Connell, Fig. 1, System 100, ECC Engine 120-1-3, eDRAM 120-1-2, Failed Address Engineer 120-2-2)
detect whether an error exists in data stored in the memory array; and
(O’Connell, Fig. 1, System 100, ECC Engine 120-1-3, eDRAM 120-1-2, Failed Address Engineer 120-2-2)
(O’Connell, Fig. 5, Access to eDRAM 120-1-1 (510), ECC error has been flagged? (520), Store the flagged address to the list of SER address (560))
(O’Connell, Fig. 5, Access to eDRAM 120-1-1 (510), ECC error has been flagged? (520) == YES, Store the flagged address to the list of SER address (560))
(O’Connell, [0038] In block 520, failed address engine 120-2-2 determines if ECC engine 120-1-3 has flagged an error. If ECC engine 120-1-3 has not flagged an error, failed address engine 120-2-2 100 in block 530 functions as usual, and system 100 continues to operate normally)
in response to detecting a first error, record a first location.
(O’Connell, Fig. 5, Access to eDRAM 120-1-1 (510), ECC error has been flagged? (520) == YES, Store the flagged address to the list of SER address (560))
(O’Connell, [0039] If, however, ECC engine 120-1-3 has flagged an error, and therefore captured the failed address of failed location 240-5, failed address engine 120-2-2 in block 540, receiving the failed address location 240-5 from ECC engine 120-1, compares the failed address location 240-5 to a list of previously failed addresses, which in effect, includes the list of soft error (e.g., SER) addresses)
(O’Connell, [0040] If there is not a match (e.g., the failed address location 240-5 is not in the stored list of SER addresses), failed address engine 120-2-2, recognizing this is a new failure location, considers the error as a soft error, and, in block 560, stores this failed address location 240-5 in the stored list of SER addresses)
As per claim 22:
O’Connell further discloses:
wherein the controller is further configured to: perform memory management for a memory device that includes the memory array, wherein the memory management includes correcting the first error.
(O’Connell, Fig. 5, Correct SER failure (570))
(O’Connell, [0041] Failed address engine 120-2-2 in block 570 corrects the SER failure)
As per claim 24:
O’Connell further discloses:
wherein the controller is further configured to determine a parity for data stored in a portion of the memory array for which the first error is detected.
(O’Connell, Abstract< Redundancy including extra rows and/or columns of memory cells is added to the memory, and ECC parity is used to detect errors. When an error occurs at a location the first time, it is assumed to be a soft error, the data is corrected in this location, and the address of the erroneous cell (e.g., the failed address) is stored in a list))
(O’Connell, [0020], Generally, when an error occurs in eDRAM 120-1-1, ECC engine 120-1-3, based on the data and associated parity bits, recognizes an error arises, identifies the address of the failed bit, and flags that error. In an embodiment, ECC engine 120-1-3 uses six parity bits to correct a single error in a data word of 32 bits and seven parity bits to correct a single error and detect a double error)
As per claim 25:
O’Connell further discloses:
wherein the first error is detected by comparing a parity stored with code words in a first page to a parity computed for the code words when the first page is activated.
(O’Connell, Abstract< Redundancy including extra rows and/or columns of memory cells is added to the memory, and ECC parity is used to detect errors. When an error occurs at a location the first time, it is assumed to be a soft error, the data is corrected in this location, and the address of the erroneous cell (e.g., the failed address) is stored in a list))
(O’Connell, [0020], Generally, when an error occurs in eDRAM 120-1-1, ECC engine 120-1-3, based on the data and associated parity bits, recognizes an error arises, identifies the address of the failed bit, and flags that error. In an embodiment, ECC engine 120-1-3 uses six parity bits to correct a single error in a data word of 32 bits and seven parity bits to correct a single error and detect a double error)
As per claim 26:
O’Connell further discloses:
wherein the first error is for a row of the memory array, the row stores a first parity of data written to the row, and the first parity is compared to a second parity when data is read from the row.
(O’Connell, Abstract< Redundancy including extra rows and/or columns of memory cells is added to the memory, and ECC parity is used to detect errors. When an error occurs at a location the first time, it is assumed to be a soft error, the data is corrected in this location, and the address of the erroneous cell (e.g., the failed address) is stored in a list))
(O’Connell, [0020], Generally, when an error occurs in eDRAM 120-1-1, ECC engine 120-1-3, based on the data and associated parity bits, recognizes an error arises, identifies the address of the failed bit, and flags that error. In an embodiment, ECC engine 120-1-3 uses six parity bits to correct a single error in a data word of 32 bits and seven parity bits to correct a single error and detect a double error)
As per claim 27:
O’Connell further discloses:
wherein the first error is for a first portion, and the controller is further configured to access the first portion by activating a row of the memory array to read or write data stored on the activated row.
(O’Connell, Fig. 5, Access to eDRAM 120-1-1 (510), ECC error has been flagged? (520), Store the flagged address to the list of SER address (560))
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over O’Connell (US 2011/0,041,016), and further in view of Park et al. (US 2024/0,202,069)
As per claim 5:
O’Connell further discloses:
further comprising a queue to store locations of the memory array for which errors in stored data are detected, wherein the queue includes the first location, and
(O’Connell, Fig. 5, Queue hard error (590))
wherein the controller is further configured to correct errors at the stored locations during a
(O’Connell, Fig. 5, Correct the redundant location (595))
(O’Connell [0045] … once the redundant row 210, the redundant word 210-1, or the redundant column 410, has been identified, the redundant location 210-5 does not necessarily include the correct data. Failed address engine 120-2-2 in block 595 corrects the data in redundant location 210-5. Depending on applications, redundancy engine 120-1-2 queues for an overwrite of the redundant location 210-5 or redundancy engine 120-1-2 overwrites the data in redundant location 210-5 as appropriate. In the case of column swapping in FIG. 400, redundancy engine 120-1-2 overwrites all cells in redundant column 410. Alternatively, redundancy engine 120-1-2 uses the corrected data and the address of failed location 240-5 provided by ECC engine 120-1-3 to flip the logic state of the data in redundant location 210-5)
(O’Connell [0046] Once redundant location 210-5 is written with the corrected data, i.e., the error has been completely repaired, failed address engine 120-2-2 in block 598 tags the failed location 240-5 as completely repaired)
O’Connell does not disclose:
Scrub operation.
Park discloses
Scrub operation.
(Park Fig. 4, Check Fail Information S20)
(Park Fig. 4, Set Scrubbing Cycle according to Fail Information S30)
(Park Fig. 4, Scrub Engine Start S40)
(Park [0063] The memory controller 10 checks fail information when the patrol scrubbing operation is activated (S20). In accordance with some example embodiments, the fail information includes error information monitored by the ECC engine 100. For example, the fail information may include an error count value, which is the number of times of an error that has been detected, and an address of the memory cell in which the error has been detected)
It would have been obvious before the effective filing date of the claimed to a person having ordinary skill in the art to incorporate Park’s method of scrubbing according to stored fail information of O’Connell in order to prevent an unrecoverable error and to lower failure rate of the memory system.
(Park, [0069] Thus, the memory system may prevent an unrecoverable error from occurring in the scrubbing operation by maintaining or re-adjusting the scrubbing cycle in accordance with the fail information. Accordingly, performance drop and failure rate of the memory system may be lowered)
As per claim 23:
O’Connell further discloses:
wherein the controller is further configured to: store locations of the memory array for which errors in stored data are detected, the stored locations including the first location; and correct errors at the stored locations during a
(O’Connell, Fig. 5, Access to eDRAM 120-1-1 (510), ECC error has been flagged? (520) == YES, Store the flagged address to the list of SER address (560))
(O’Connell, [0039] If, however, ECC engine 120-1-3 has flagged an error, and therefore captured the failed address of failed location 240-5, failed address engine 120-2-2 in block 540, receiving the failed address location 240-5 from ECC engine 120-1, compares the failed address location 240-5 to a list of previously failed addresses, which in effect, includes the list of soft error (e.g., SER) addresses)
O’Connell does not disclose:
Scrub operation.
Park discloses
Scrub operation.
(Park Fig. 4, Check Fail Information S20)
(Park Fig. 4, Set Scrubbing Cycle according to Fail Information S30)
(Park Fig. 4, Scrub Engine Start S40)
(Park [0063] The memory controller 10 checks fail information when the patrol scrubbing operation is activated (S20). In accordance with some example embodiments, the fail information includes error information monitored by the ECC engine 100. For example, the fail information may include an error count value, which is the number of times of an error that has been detected, and an address of the memory cell in which the error has been detected)
It would have been obvious before the effective filing date of the claimed to a person having ordinary skill in the art to incorporate Park’s method of scrubbing according to stored fail information of O’Connell in order to prevent an unrecoverable error and to lower failure rate of the memory system.
(Park, [0069] Thus, the memory system may prevent an unrecoverable error from occurring in the scrubbing operation by maintaining or re-adjusting the scrubbing cycle in accordance with the fail information. Accordingly, performance drop and failure rate of the memory system may be lowered)
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over O’Connell (US 2011/0,041,016), and further in view of Rao (US 2009/0,103,386)
As per claim 8:
O’Connell further discloses:
wherein accessing portions of the memory array comprises activated row.
(O’Connell, Abstract< Redundancy including extra rows and/or columns of memory cells is added to the memory, and ECC parity is used to detect errors. When an error occurs at a location the first time, it is assumed to be a soft error, the data is corrected in this location, and the address of the erroneous cell (e.g., the failed address) is stored in a list))
(O’Connell, [0020], Generally, when an error occurs in eDRAM 120-1-1, ECC engine 120-1-3, based on the data and associated parity bits, recognizes an error arises, identifies the address of the failed bit, and flags that error. In an embodiment, ECC engine 120-1-3 uses six parity bits to correct a single error in a data word of 32 bits and seven parity bits to correct a single error and detect a double error)
O’Connell discloses a method for accessing address for writing and reading.
However, O’Connell does not disclose a method for accessing address for writing and reading by activating row.
Rao discloses:
a method for accessing address for writing and reading by activating row.
(Rao [0023] Sense amplifier and precharge circuit 112 may be configured to precharge a plurality of bit lines corresponding to the memory cells to be accessed. Row decoder 114 may activate row lines corresponding to the memory cells to be accessed and column decoder 110 in conjunction with precharge and sense amplifier circuit 112 may act to either read or write data to the memory cells corresponding to the memory cells to be accessed. In other embodiments where the access command is a precharge command, no read or write operation may be performed)
(Rao, Fig. 4)
It would have been obvious before the effective filing date of the claimed to a person having ordinary skill in the art to incorporate a well-known method accessing address/row for writing and reading by activating row of Rao into the system in order to perform write and read access of O’Connell. This method is very well-known in the art.
(Rao [0023] Sense amplifier and precharge circuit 112 may be configured to precharge a plurality of bit lines corresponding to the memory cells to be accessed. Row decoder 114 may activate row lines corresponding to the memory cells to be accessed and column decoder 110 in conjunction with precharge and sense amplifier circuit 112 may act to either read or write data to the memory cells corresponding to the memory cells to be accessed. In other embodiments where the access command is a precharge command, no read or write operation may be performed)
(Rao, Fig. 4)
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over O’Connell (US 2011/0,041,016), in view of Berman et al. (US 2018/0,081,754)
As per claim 18:
O’Connell discloses:
A method comprising:
in response to receiving an activate command, sensing a first page of data and a parity stored in the first page;
(O’Connell, Abstract< Redundancy including extra rows and/or columns of memory cells is added to the memory, and ECC parity is used to detect errors. When an error occurs at a location the first time, it is assumed to be a soft error, the data is corrected in this location, and the address of the erroneous cell (e.g., the failed address) is stored in a list))
(O’Connell, [0020], Generally, when an error occurs in eDRAM 120-1-1, ECC engine 120-1-3, based on the data and associated parity bits, recognizes an error arises, identifies the address of the failed bit, and flags that error. In an embodiment, ECC engine 120-1-3 uses six parity bits to correct a single error in a data word of 32 bits and seven parity bits to correct a single error and detect a double error)
O’Connell does not disclose:
computing a first parity for the first page; and comparing the first parity to the stored parity.
Berman discloses:
computing a first parity for the first page; and comparing the first parity to the stored parity.
(Berman, [0034] Read flow is modified such that after internal array-to-page buffer sensing, and error checking and correction (ECC) encoder on the memory device (e.g., a NAND memory device) calculate the parity, compare it to the one that was read from the array, and transmits the differential … between the two parity blocks along with the data)
(Berman, [0038]… ECC encoder 201 applies the calculated parity as a first input to a subtractor 204. The page buffer 202 applies the parity portion as a second input to the subtractor 204. The subtractor 204 performs a subtraction operation on the first input (e.g., the calculated parity) and the second input (e.g., the parity portion) to generate a parity difference)
It would have been obvious before the effective filing date of the claimed to a person having ordinary skill in the art to incorporate a well-known method of Berman’s of computing a parity and comparing the parity to the stored parity in order to determine the different between parities.
(Berman, [0034] Read flow is modified such that after internal array-to-page buffer sensing, and error checking and correction (ECC) encoder on the memory device (e.g., a NAND memory device) calculate the parity, compare it to the one that was read from the array, and transmits the differential … between the two parity blocks along with the data)
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over O’Connell (US 2011/0,041,016), in view of Berman et al. (US 2018/0,081,754), and further in view of Park et al. (US 2024/0,202,069)
As per claim 19:
O’Connell-Berman further discloses:
further comprising in response to determining that the first
(O’Connell, Abstract< Redundancy including extra rows and/or columns of memory cells is added to the memory, and ECC parity is used to detect errors. When an error occurs at a location the first time, it is assumed to be a soft error, the data is corrected in this location, and the address of the erroneous cell (e.g., the failed address) is stored in a list))
(O’Connell, [0020], Generally, when an error occurs in eDRAM 120-1-1, ECC engine 120-1-3, based on the data and associated parity bits, recognizes an error arises, identifies the address of the failed bit, and flags that error. In an embodiment, ECC engine 120-1-3 uses six parity bits to correct a single error in a data word of 32 bits and seven parity bits to correct a single error and detect a double error)
adding a physical address of the first page to a
(O’Connell, Fig. 5, Correct SER failure (570))
(O’Connell, [0041] Failed address engine 120-2-2 in block 570 corrects the SER failure)
(O’Connell, Fig. 5, Correct the redundant location (595))
(O’Connell [0045] … once the redundant row 210, the redundant word 210-1, or the redundant column 410, has been identified, the redundant location 210-5 does not necessarily include the correct data. Failed address engine 120-2-2 in block 595 corrects the data in redundant location 210-5. Depending on applications, redundancy engine 120-1-2 queues for an overwrite of the redundant location 210-5 or redundancy engine 120-1-2 overwrites the data in redundant location 210-5 as appropriate. In the case of column swapping in FIG. 400, redundancy engine 120-1-2 overwrites all cells in redundant column 410. Alternatively, redundancy engine 120-1-2 uses the corrected data and the address of failed location 240-5 provided by ECC engine 120-1-3 to flip the logic state of the data in redundant location 210-5.
(O’Connell [0046] Once redundant location 210-5 is written with the corrected data, i.e., the error has been completely repaired, failed address engine 120-2-2 in block 598 tags the failed location 240-5 as completely repaired)
Berman further disclose:
determining that the first parity does not match the stored parity,
(Berman, [0034] Read flow is modified such that after internal array-to-page buffer sensing, and error checking and correction (ECC) encoder on the memory device (e.g., a NAND memory device) calculate the parity, compare it to the one that was read from the array, and transmits the differential … between the two parity blocks along with the data)
(Berman, [0038]… ECC encoder 201 applies the calculated parity as a first input to a subtractor 204. The page buffer 202 applies the parity portion as a second input to the subtractor 204. The subtractor 204 performs a subtraction operation on the first input (e.g., the calculated parity) and the second input (e.g., the parity portion) to generate a parity difference)
O’Connell-Berman does not disclose:
Scrub operation.
Park discloses
Scrub operation.
(Park Fig. 4, Check Fail Information S20)
(Park Fig. 4, Set Scrubbing Cycle according to Fail Information S30)
(Park Fig. 4, Scrub Engine Start S40)
(Park [0063] The memory controller 10 checks fail information when the patrol scrubbing operation is activated (S20). In accordance with some example embodiments, the fail information includes error information monitored by the ECC engine 100. For example, the fail information may include an error count value, which is the number of times of an error that has been detected, and an address of the memory cell in which the error has been detected)
It would have been obvious before the effective filing date of the claimed to a person having ordinary skill in the art to incorporate Park’s method of scrubbing according to stored fail information of O’Connell in order to prevent an unrecoverable error and to lower failure rate of the memory system.
(Park, [0069] Thus, the memory system may prevent an unrecoverable error from occurring in the scrubbing operation by maintaining or re-adjusting the scrubbing cycle in accordance with the fail information. Accordingly, performance drop and failure rate of the memory system may be lowered)
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over O’Connell (US 2011/0,041,016), in view of Berman et al. (US 2018/0,081,754), and further in view of Rao (US 2009/0,103,386)
As per claim 20:
O’Connell-Berman further discloses:
in response to receiving a
computing a second parity for the first page of data; and writing the first page of data and the second parity.
(Berman, [0034] Read flow is modified such that after internal array-to-page buffer sensing, and error checking and correction (ECC) encoder on the memory device (e.g., a NAND memory device) calculate the parity, compare it to the one that was read from the array, and transmits the differential … between the two parity blocks along with the data)
(Berman, [0038]… ECC encoder 201 applies the calculated parity as a first input to a subtractor 204. The page buffer 202 applies the parity portion as a second input to the subtractor 204. The subtractor 204 performs a subtraction operation on the first input (e.g., the calculated parity) and the second input (e.g., the parity portion) to generate a parity difference)
However, O’Connell-Berman does not disclose a method for precharging.
Rao discloses:
a method for precharging.
(Rao [0023] Sense amplifier and precharge circuit 112 may be configured to precharge a plurality of bit lines corresponding to the memory cells to be accessed. Row decoder 114 may activate row lines corresponding to the memory cells to be accessed and column decoder 110 in conjunction with precharge and sense amplifier circuit 112 may act to either read or write data to the memory cells corresponding to the memory cells to be accessed. In other embodiments where the access command is a precharge command, no read or write operation may be performed)
(Rao, Fig. 4)
It would have been obvious before the effective filing date of the claimed to a person having ordinary skill in the art to incorporate a well-known method accessing address/row for writing and reading by activating row of Rao into the system in order to perform write and read access of O’Connell. This method is very well-known in the art.
(Rao [0023] Sense amplifier and precharge circuit 112 may be configured to precharge a plurality of bit lines corresponding to the memory cells to be accessed. Row decoder 114 may activate row lines corresponding to the memory cells to be accessed and column decoder 110 in conjunction with precharge and sense amplifier circuit 112 may act to either read or write data to the memory cells corresponding to the memory cells to be accessed. In other embodiments where the access command is a precharge command, no read or write operation may be performed)
(Rao, Fig. 4)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Berman et al. (US 2018/0,081,754) in [0034]-[0038] discloses a method of reading data, calculating the parity, comparing it to the one that was read from the array, and transmits the differential … between the two parity blocks along with the data)
Ruckerbauer (US2007/0,028,146) discloses a method of reading data, calculating the parity, comparing the calculated parity with the stored parity.
(Ruckerbaue [0059] During the reading out of the data bits, the corresponding parity bit is--anew--calculated and compared with the stored parity bit. If a difference results, an error has occurred)
Jamil et al. (US 2004/0,193,992) discloses a method of reading data, calculating the parity, comparing the calculated parity with the stored parity.
(Jamil [0020] When data is read from the TLB array, that data is typically used to generate a parity bit and the parity bit generated is compared to a previously computed and stored parity bit to detect an error)
Shellhamer (US 2009/0,259,882) in [0052] discloses a method of reading data, calculating the parity, comparing the calculated parity with the stored parity.
(Shellhamer [0052] …Verify utilities for parity-based arrays read data, calculate parity, and compare to stored parity. …. The scrub utilities perform the same comparison as verify utilities, plus they also may perform reading/comparing metadata in addition to the user data, reset SMART data (clears drive reports after processing any available data), and create a record of all data miscompares)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THIEN DANG NGUYEN whose telephone number is (571)272-9189. The examiner can normally be reached Monday-Friday 7 AM - 3:30 PM.
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/Thien Nguyen/ Primary Examiner, Art Unit 2111