DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments have been considered but are moot in view of the new grounds of rejection set forth below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over Arai (US 11404362 B2) in view of Nishiyama et al. (US 20240413064 A1)
Regarding Claim 1 – Arai discloses a printed circuit board (Fig 1A; 10) comprising: a wiring portion including one or more insulating layers (Fig 1A; insulation layers 25, 26, 31, 41), one or more wiring layers respectively disposed on or in the one or more insulating layers (Fig 1A; wiring layers 30, 32, 40, 42), a first pad disposed on a lowermost insulating layer of the one or more insulating layers (Figs 1A, 3B; external connection pad P1; Arai [Description] states “The solder resist layer 33 includes an opening 33X partially exposing the lower surface of the wiring layer 32 as an external connection pad P1”), and a second pad disposed on an uppermost insulating layer of the one or more insulating layers (Fig 1A; exposed upper wiring layer 42 region in opening 43X; Arai states “The solder resist layer 43 includes an opening 43X partially exposing the upper surface of the wiring layer 42”); a first solder resist layer disposed on a lower side of the wiring portion to cover at least a portion of the first pad, the first solder resist layer having a first opening, on the first pad (Figs 1A, 3B; 33); a second solder resist layer disposed on an upper side of the wiring portion to cover at least a portion of the second pad (Figs 1A, 3B; 43); a first surface treatment layer disposed on at least a portion of the first pad (Fig 1A; diffusion prevention layer 34 on external connection pads P1).
Arai does not explicitly disclose a barrier layer disposed on the first solder resist layer wherein a thickness of the barrier layer is less than a thickness of the first pad.
Nishiyama teaches a barrier layer (Fig 1; 51) disposed on the first solder resist layer (Fig 1; 13) wherein a thickness of the barrier layer is less than a thickness of the first pad (Figs 1, 3A; 32, 51, 52; Nishiyama [0026-0027] states “The second layer 52 may have a thickness greater than a thickness of the first layer 51” where 52 forms the conductive body within pad region 32).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Arai with a barrier layer disposed on the first solder resist layer wherein a thickness of the barrier layer is less than a thickness of the first pad as taught by Nishiyama to get the benefit of improved adhesion between the connection structure and the solder resist and to suppress copper migration, thereby reducing peeling and migration induced short circuits (Nishiyama [0042-0043]).
Regarding Claim 5 – Arai in view of Nishiyama teaches the printed circuit board of claim 1, wherein the second solder resist layer has a second opening disposed on the second pad (Fig 1A; opening 43X; Arai quoted above).
Regarding Claim 6 – Arai in view of Nishiyama teaches the printed circuit board of claim 5, further comprising: a metal post disposed in the second opening, the metal post disposed on at least a portion of the second pad (Arai Figs 1A-1B; 70, 66; Arai teaches that opening 43X is filled with metal layer 66 and states “Each metal post 70 is, for example, formed integrally with the metal layer 66”).
Regarding Claim 7 – Arai in view of Nishiyama teaches the printed circuit board of claim 6, further comprising: a second surface treatment layer disposed on the metal post (Fig 1B; Arai states “An outer coating plating layer 80 is formed on the upper surface and side surface of each connection terminal 52” and that the layer 80 “entirely covers”/ “continuously covers” those surfaces).
Regarding Claim 8 – Arai in view of Nishiyama teaches the printed circuit board of claim 6, further comprising: a first semiconductor chip disposed on the metal post; and a connection member connecting the metal post and the first semiconductor chip to each other (Arai Fig 23; Arai states “a connection terminal 92 of a semiconductor element 91 is flip-chip-bonded… [and] is connected by a solder layer 93 to the surface-processed layer 210 on the metal post 70”).
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Arai (US 11404362 B2) in view of Nishiyama et al. (US 20240413064 A1) and in further view of Nalla et al. (US 20100276185 A1)
Regarding Claim 2 – Arai in view of Nishiyama teaches the printed circuit board of claim 1, but does not explicitly disclose wherein the barrier layer is disposed on a lower surface of the first solder resist layer.
Nalla teaches the barrier layer is disposed on a lower surface of the first solder resist layer (Fig 1; 130, 131, 120, 122; Nalla [0015] states “conformal barrier layer 130 having a portion 131 over surface 122 of solder resist layer 120”).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Arai in view of Nishiyama with the barrier layer is disposed on a lower surface of the first solder resist layer as taught by Nalla to simplify fabrication by forming the barrier layer in a single processing step (Nalla [0020]).
Regarding Claim 3 – Arai in view of Nishiyama and Nalla teaches the printed circuit board of claim 2, wherein the barrier layer is disposed along an inner wall of the first opening and at least a portion of the first surface treatment layer (Fig 1; 130, 132, 121, 160; Nalla [0015-0018]).
Claims 4, 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Arai (US 11404362 B2) in view of Nishiyama et al. (US 20240413064 A1) and in further view of Ono et al. (US 6217987 B1)
Regarding Claim 4 – Arai in view of Nishiyama teaches the printed circuit board of claim 1, but fail to disclose wherein the first solder resist layer covers at least a portion of an upper surface of the first pad.
Ono teaches the first solder resist layer covers at least a portion of an upper surface of the first pad (Figs 23-24; Ono states “the opening size of the opening portion may be made smaller than the diameter of the pad so as to cover the peripheral edge of the pad with the solder resist”).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Arai in view of Nishiyama with the first solder resist layer covers at least a portion of an upper surface of the first pad as taught by Ono to restrain the pad with the solder resist and prevent peeling of the pad as expressly taught by Ono.
Regarding Claim 9 – Arai in view of Nishiyama teaches the printed circuit board of claim 1, but fails to disclose wherein a thickness of the barrier layer is less than a thickness of the first surface treatment layer.
Ono teaches a thickness of the barrier layer is less than a thickness of the first surface treatment layer (Figs 23-24; Ono states “It is desirable that the thickness of the nickel layer is 0.5-7 μm and the thickness of the gold layer is 0.01-0.06 μm”). Nishiyama teaches that first layer 51 has a thickness of 10 nm to 100 nm (Nishiyama [0035]). Thus, the nickel layer of Ono’s surface treatment is thicker than the barrier layer of Nishiyama
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Arai in view of Nishiyama with a thickness of the barrier layer is less than a thickness of the first surface treatment layer as taught by Ono to improve adhesion of the surface treatment to the pad and adhesion to the solder body.
Regarding Claim 10 – Arai in view of Nishiyama and Ono teaches the printed circuit board of claim 9, wherein the thickness of the barrier layer is less than 100 nm (Nishiyama Fig 3A; Nishiyama [0035] teaches that 51 has a thickness in a range of 10 nm to 100 nm).
Claims 11-12, 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over Arai (US 11404362 B2) in view of Nishiyama et al. (US 20240413064 A1) and Pankow et al. (US 20130009264 A1)
Regarding Claim 11 – Arai discloses a printed circuit board (Fig 1A; 10) comprising: a wiring portion including one or more insulating layers (Fig 1A; insulation layers 25, 26, 31, 41), one or more wiring layers respectively disposed on or in the one or more insulating layers (Fig 1A; wiring layers 30, 32, 40, 42), a first pad disposed on a lowermost insulating layer of the one or more insulating layers (Figs 1A, 3B; external connection pad P1; Arai [Description] states “The solder resist layer 33 includes an opening 33X partially exposing the lower surface of the wiring layer 32 as an external connection pad P1”), and a second pad disposed on an uppermost insulating layer of the one or more insulating layers (Fig 1A; exposed upper wiring layer 42 region in opening 43X; Arai states “The solder resist layer 43 includes an opening 43X partially exposing the upper surface of the wiring layer 42”); a first solder resist layer disposed on a lower side of the wiring portion to cover at least a portion of the first pad, the first solder resist layer having a first opening, on the first pad (Figs 1A, 3B; 33); a second solder resist layer disposed on an upper side of the wiring portion to cover at least a portion of the second pad (Figs 1A, 3B; 43); a first surface treatment layer disposed on at least a portion of the first pad (Fig 1A; diffusion prevention layer 34 on external connection pads P1); and a barrier layer disposed on the first solder resist layer (Fig 4B; layer 35 on 33; Arai states “The seed layer 35 continuously covers… the entire lower surface of the solder resist layer 33”).
Arai does not explicitly disclose wherein a barrier layer disposed on the first solder resist layer, wherein the barrier layer includes an inorganic oxide film.
Nishiyama teaches a barrier layer (Fig 1; 51) disposed on the first solder resist layer (Fig 1; 13).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Arai with a barrier layer disposed on the first solder resist layer as taught by Nishiyama to get the benefit of improved adhesion between the connection structure and the solder resist and to suppress copper migration, thereby reducing peeling and migration induced short circuits (Nishiyama [0042-0043]).
Pankow teaches the barrier layer includes an inorganic oxide film (Fig 1; 106; Pankow [0036] states “may also include a barrier layer 106 deposited on the ALD interfacial layer 104” and “a barrier layer fabricated from a silicon dioxide, silicon oxynitride or silicon nitride”).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Arai with the barrier layer includes an inorganic oxide film as taught by to obtain Pankow’s expressly taught physical and chemical barrier protection against moisture.
Regarding Claim 12 – Arai in view of Nishiyama and Pankow teaches the printed circuit board of claim 11, wherein the barrier layer includes at least one of Al2O3, TiO2, ZnO, and SiO2 (Fig 1; 106; Pankow [0036] quoted above).
Regarding Claim 15 – Arai in view of Nishiyama and Pankow teaches the printed circuit board of claim 12, further comprising: a metal post disposed on at least a portion of the second pad (Arai Figs 1A-1B; 70, 66; Arai [0057-0059]).
Regarding Claim 16 – Arai in view of Nishiyama and Pankow teaches the printed circuit board of claim 11, wherein a thickness of the barrier layer is less than a thickness of the first pad (Figs 1, 3A; 32, 51, 52; Nishiyama [0026-0027]).
Regarding Claim 17 – Arai in view of Nishiyama and Pankow teaches the printed circuit board of claim 11, wherein the second solder resist layer has a second opening disposed on the second pad (Fig 1A; opening 43X; Arai quoted above).
Regarding Claim 18 – Arai in view of Nishiyama and Pankow teaches the printed circuit board of claim 11, wherein the first and second solder resist layers include a thermosetting resin, wherein an inorganic filler is dispersed in the thermosetting resin (Fig 1A; 33, 43; Arai teaches a resin material obtained by mixing filler such as silica or alumina with a thermosetting resin and teaches solder resist layers 33 and 43 may comprise the same insulative material).
Regarding Claim 19 – Arai in view of Nishiyama and Pankow teaches the printed circuit board of claim 11, wherein the first and second solder resist layers include a photosensitive insulating resin (Figs 1A, 3B; solder resist layers 33 and 43; Arai states “The material of the solder resist layer 33 may be… an insulative resin of which the main component is a photosensitive insulative resin such as a phenol resin or a polyimide resin” and “The material of the solder resist layer 43 may be… an insulative resin of which the main component is a photosensitive insulative resin such as a phenol resin or a polyimide resin”).
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Arai (US 11404362 B2) in view of Nishiyama et al. (US 20240413064 A1) and Pankow et al. (US 20130009264 A1) and in further view of Nalla et al. (US 20100276185 A1)
Regarding Claim 13 – Arai in view of Nishiyama and Pankow teaches the printed circuit board of claim 11, but does not explicitly disclose wherein the barrier layer is disposed on a lower surface of the first solder resist layer.
Nalla teaches the barrier layer is disposed on a lower surface of the first solder resist layer (Fig 1; 130, 131, 120, 122; Nalla [0015] states “conformal barrier layer 130 having a portion 131 over surface 122 of solder resist layer 120”).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Arai in view of Nishiyama and Pankow with the barrier layer is disposed on a lower surface of the first solder resist layer as taught by Nalla to simplify fabrication by forming the barrier layer in a single processing step (Nalla [0020]).
Regarding Claim 14 – Arai in view of Nishiyama, Pankow, and Nalla teaches the printed circuit board of claim 13, wherein the barrier layer is disposed along an inner wall of the first opening and at least a portion of the first surface treatment layer (Fig 1; 130, 132, 121, 160; Nalla [0015-0018]).
Conclusion
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/ADITYA SHARMA/Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
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